# MgCpld

The top is defined in HDL source file TopCpld.vhd.

## P5 Content

### Register map supplied for open-source projects

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# MgCpld

This regmap has readablestrobes="true", so all strobe bits are readable by default. This attribute should only be used for older regmaps to maintain compatibility with previous versions of XmlParse. New regmaps should either use the 'clearable' attribute or should explicitly define readable bits in the same bit position as the strobe bits.

## PsSpi_CpldRegisters

These registers are accessed via the PS SPI interface to the CPLD. They are all internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock MUST idle LOW before and after the transaction. CPOL=CPHA=0. To access these registers, use the chip select line named "CPLD-PS-SPI-SLE-33" as an active-low select.

### Offset 0x0000: SignatureReg Register (R)

(show extended info)

SignatureReg
offset=0x0000

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

This register contains the device signature.

Bits | Name
15..0 | ProductSignature Represents the product family name/number. This field reads back as 0xCAFE.

### Offset 0x0001: MinorRevReg Register (R)

(show extended info)

MinorRevReg
offset=0x0001

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

This register contains the device revision numeric code.

Bits | Name
15..0 | CpldMinorRevision Contains minor revision code (0,1,2,...).

### Offset 0x0002: MajorRevReg Register (R)

(show extended info)

MajorRevReg
offset=0x0002

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

This register contains the major revision value.

Bits | Name
15..0 | CpldMajorRevision Contains major revision code.

### Offset 0x0003: BuildCodeLSB Register (R)

(show extended info)

BuildCodeLSB
offset=0x0003

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Build code... right now it's the date it was built. LSB in this register.

Bits | Name
15..8 | BuildCodeDD Contains build code day code.
7..0 | BuildCodeHH Contains build code hour code.

### Offset 0x0004: BuildCodeMSB Register (R)

(show extended info)

BuildCodeMSB
offset=0x0004

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Build code... right now it's the date it was built. MSB in this register.

Bits | Name
15..8 | BuildCodeYY Contains build code revision year code.
7..0 | BuildCodeMM Contains build code month code.

### Offset 0x0005: Scratch Register (R|W)

(show extended info)

Scratch
offset=0x0005

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..0 | ScratchVal Contains scratch value for testing. The state of this register has no effect on any other operation in the CPLD.

### Offset 0x0010: CpldControl Register (W)

(show extended info)

CpldControl
offset=0x0010

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..8 | Reserved
7..1 | Reserved
0w | CpldReset Asserting this bit resets all the CPLD logic. This reset will return all registers on the PS SPI interface to their default state! To use this reset correctly, first write CpldReset to '1', then write it to '0'. Registers will be reset on the _falling_ edge of CpldReset.

### Offset 0x0011: LmkControl Register (R|W)

(show extended info)

LmkControl
offset=0x0011

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..8 | Reserved
7..5 | Reserved
4 | VcxoControl Setting this bit to '0' will allow the Phase DAC to exclusively control the VCXO voltage. Defaults to '1', which allows the Phase DAC to adjust the voltage (but the LMK still has control as well).
3..0 | Reserved

### Offset 0x0012: LoStatus Register (R)

(show extended info)

LoStatus
offset=0x0012

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..8 | Reserved
7..5 | Reserved
4 | TxLoLockDetect Live lock detect status from the TX LO.
3..1 | Reserved
0 | RxLoLockDetect Live lock detect status from the RX LO.

### Offset 0x0013: MykonosControl Register (R|W)

(show extended info)

MykonosControl
offset=0x0013

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..8 | Reserved
7..1 | Reserved
0 | MykonosReset Drives the Mykonos hard reset line. Defaults to de-asserted. Write a '1' to assert the reset, and a '0' to de-assert.

## PlSpi_FrontEndControl

These registers are accessed via the PL SPI interface to the CPLD. They are all internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock MUST idle LOW before and after the transaction. CPOL=CPHA=0. To access these registers, use the chip select line named "CPLD-PL-SPI-LE-25" as an active-low select.
The ATR bits ultimately control which of these registers actually control the RF front end.

### Rx1Switch1 Enumeration

Value | Name
0 | TxRxInput
1 | RxLoCalInput
2 | TrxSwitchOutput
3 | Rx2Input

This enumerated type is defined in HDL source file TopCpld.vhd.

### Rx1Switch2 Enumeration

Value | Name
0 | ShutdownSw2
1 | LowerFilterBankToSwitch3
2 | BypassPathToSwitch6
3 | UpperFilterBankToSwitch4

This enumerated type is defined in HDL source file TopCpld.vhd.

### Rx1Switch3 Enumeration

Value | Name
0 | Filter2100x2850MHz
1 | Filter0490LpMHz
2 | Filter1600x2250MHz
4 | Filter0440x0530MHz
5 | Filter0650x1000MHz
6 | Filter1100x1575MHz
7 | ShutdownSw3

This enumerated type is defined in HDL source file TopCpld.vhd.

### Rx1Switch4 Enumeration

Value | Name
1 | Filter2100x2850MHzFrom
2 | Filter1600x2250MHzFrom
4 | Filter2700HpMHz

This enumerated type is defined in HDL source file TopCpld.vhd.

### Rx1Switch5 Enumeration

Value | Name
1 | Filter0440x0530MHzFrom
2 | Filter1100x1575MHzFrom
4 | Filter0490LpMHzFrom
8 | Filter0650x1000MHzFrom

This enumerated type is defined in HDL source file TopCpld.vhd.

### Rx1Switch6 Enumeration

Value | Name
1 | LowerFilterBankFromSwitch5
2 | UpperFilterBankFromSwitch4
4 | BypassPathFromSwitch2

This enumerated type is defined in HDL source file TopCpld.vhd.

### TrxSwitch Enumeration

Value | Name
0 | FromLowerFilterBankTxSw1
1 | FromTxUpperFilterBankLp6400MHz
2 | RxChannelPath
3 | BypassPathToTxSw3

This enumerated type is defined in HDL source file TopCpld.vhd.

### TxSwitch1 Enumeration

Value | Name
0 | ShutdownTxSw1
1 | FromTxFilterLp1700MHz
2 | FromTxFilterLp3400MHz
3 | FromTxFilterLp0800MHz

This enumerated type is defined in HDL source file TopCpld.vhd.

### TxSwitch2 Enumeration

Value | Name
1 | ToTxFilterLp3400MHz
2 | ToTxFilterLp1700MHz
4 | ToTxFilterLp0800MHz
8 | ToTxFilterLp6400MHz

This enumerated type is defined in HDL source file TopCpld.vhd.

### TxSwitch3 Enumeration

Value | Name
0 | ToTxFilterBanks
1 | BypassPathToTrxSw

This enumerated type is defined in HDL source file TopCpld.vhd.

### Offset 0x0040: PlScratch Register (R|W)

(show extended info)

PlScratch
offset=0x0040

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..0 | PlScratchVal Contains scratch value for testing. The state of this register has no effect on any other operation in the CPLD.

### Offset 0x0041: PlCpldControl Register (W)

(show extended info)

PlCpldControl
offset=0x0041

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Bits | Name
15..8 | Reserved
7..1 | Reserved
0w | PlCpldReset Asserting this bit resets all the CPLD logic on the PL SPI interface. This reset will return all registers to their default state! To use this reset correctly, first write PlCpldReset to '1', then write it to '0'. Registers will be reset on the _falling_ edge of PlCpldReset.

### Offset 0x0050: TxCh1_Idle Register (R|W)

(show extended info)

TxCh1_Idle
offset=0x0050

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel TX 1 when the ATR bits are configured: TX = 0, RX = don't-care.

Bits | Name
15 | Reserved
14 | Ch1MykEnTx Drives the Mykonos input port TX1_ENABLE.
13 | Ch1TxLed Red/Green combo LED for the TRX channel.
12..11 | Ch1SwTrx TRX switch control. The values for this bitfield are in the TrxSwitch table. (show here)
Value | Name
0 | FromLowerFilterBankTxSw1
1 | FromTxUpperFilterBankLp6400MHz
2 | RxChannelPath
3 | BypassPathToTxSw3
This enumerated type is defined in HDL source file TopCpld.vhd.
10 | Ch1TxPaEn Write a '1' to enable the TX path PA in between TX switches 2 and 3.
9 | Ch1TxAmpEn Write a '1' to enable the TX path Amp in between TX switches 3 and 4. The path (from Mykonos) is: TxSw4 -> Amp -> DSA -> TxSw3.
8 | Ch1TxMixerEn Write a '1' to enable the lowband mixer. Note that Ch1TxLowbandMixerPathSelect must be properly configured to select the mixer path.
7 | Ch1TxLowbandMixerPathSelect Controls Switches 4 and 5. Write a '1' to select the Lowband Mixer path. Writing '0' will select the bypass path around the mixer. Default is '0'. Note: Individual control over these switches was removed as an optimization to allow all TX controls to fit in one 16 bit register.
6 | Ch1TxSw3 Controls Switch 3. Bypasses the filter bank and PA, or doesn't. The values for this bitfield are in the TxSwitch3 table. (show here)
Value | Name
0 | ToTxFilterBanks
1 | BypassPathToTrxSw
This enumerated type is defined in HDL source file TopCpld.vhd.
5..2 | Ch1TxSw2 Controls Switch 2. Filter bank distribution switch. The values for this bitfield are in the TxSwitch2 table. (show here)
Value | Name
1 | ToTxFilterLp3400MHz
2 | ToTxFilterLp1700MHz
4 | ToTxFilterLp0800MHz
8 | ToTxFilterLp6400MHz
This enumerated type is defined in HDL source file TopCpld.vhd.
1..0 | Ch1TxSw1 Controls Switch 1. Filter bank receive switch. The values for this bitfield are in the TxSwitch1 table. (show here)
Value | Name
0 | ShutdownTxSw1
1 | FromTxFilterLp1700MHz
2 | FromTxFilterLp3400MHz
3 | FromTxFilterLp0800MHz
This enumerated type is defined in HDL source file TopCpld.vhd.

### Offset 0x0051: RxCh1_0_Idle Register (R|W)

(show extended info)

RxCh1_0_Idle
offset=0x0051

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 1 when the ATR bits are configured: TX = don't-care, RX = 0.

Bits | Name
15..14 | Reserved
13..10 | Ch1RxSw5 Controls Switch 5. Lower filter bank receive switch. The values for this bitfield are in the Rx1Switch5 table. (show here)
Value | Name
1 | Filter0440x0530MHzFrom
2 | Filter1100x1575MHzFrom
4 | Filter0490LpMHzFrom
8 | Filter0650x1000MHzFrom
This enumerated type is defined in HDL source file TopCpld.vhd.
9..7 | Ch1RxSw4 Controls Switch 4. Upper filter bank receive switch. The values for this bitfield are in the Rx1Switch4 table. (show here)
Value | Name
1 | Filter2100x2850MHzFrom
2 | Filter1600x2250MHzFrom
4 | Filter2700HpMHz
This enumerated type is defined in HDL source file TopCpld.vhd.
6..4 | Ch1RxSw3 Controls Switch 3. Lower filter bank transmit switch. The values for this bitfield are in the Rx1Switch3 table. (show here)
Value | Name
0 | Filter2100x2850MHz
1 | Filter0490LpMHz
2 | Filter1600x2250MHz
4 | Filter0440x0530MHz
5 | Filter0650x1000MHz
6 | Filter1100x1575MHz
7 | ShutdownSw3
This enumerated type is defined in HDL source file TopCpld.vhd.
3..2 | Ch1RxSw2 Controls Switch 2. First filter switch. Selects between bypass path and the upper/lower filter banks. The values for this bitfield are in the Rx1Switch2 table. (show here)
Value | Name
0 | ShutdownSw2
1 | LowerFilterBankToSwitch3
2 | BypassPathToSwitch6
3 | UpperFilterBankToSwitch4
This enumerated type is defined in HDL source file TopCpld.vhd.
1..0 | Ch1RxSw1 Controls Switch 1. Selects between the cal, bypass, RX2, and TRX paths. The values for this bitfield are in the Rx1Switch1 table. (show here)
Value | Name
0 | TxRxInput
1 | RxLoCalInput
2 | TrxSwitchOutput
3 | Rx2Input
This enumerated type is defined in HDL source file TopCpld.vhd.

### Offset 0x0052: RxCh1_1_Idle Register (R|W)

(show extended info)

RxCh1_1_Idle
offset=0x0052

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 1 when the ATR bits are configured: TX = don't-care, RX = 0.

Bits | Name
15..11 | Reserved
10 | Ch1MykEnRx Drives the Mykonos input port RX1_ENABLE.
9 | Ch1RxLed Red/Green combo LED for the TRX channel.
8 | Ch1Rx2Led Green LED for RX2 channel.
7 | Ch1RxLna2En Write a '1' to enable the RX path LNA2 between RxSw5 and RxSw6.
6 | Ch1RxLna1En Write a '1' to enable the RX path LNA1 between RxSw4 and RxSw6.
5 | Ch1RxAmpEn Write a '1' to enable the RX path Amp directly before the Mykonos inputs.
4 | Ch1RxMixerEn Write a '1' to enable the lowband mixer. Note that Ch1RxLowbandMixerPathSelect must be properly configured to select the mixer path.
3 | Ch1RxLowbandMixerPathSelect Controls Switches 7 and 8. Write a '1' to select the Lowband Mixer path. Writing '0' will select the bypass path around the mixer. Default is '0'. Note: Individual control over these switches was removed as an optimization to allow all TX controls to fit in one 16 bit register... so the same was done for the RX path for continuity.
2..0 | Ch1RxSw6 Controls Switch 6. Selects between the upper and lower filter banks and bypass path. The values for this bitfield are in the Rx1Switch6 table. (show here)
Value | Name
1 | LowerFilterBankFromSwitch5
2 | UpperFilterBankFromSwitch4
4 | BypassPathFromSwitch2
This enumerated type is defined in HDL source file TopCpld.vhd.

### Offset 0x0053: TxCh1_TxOn Register (R|W)

(show extended info)

TxCh1_TxOn
offset=0x0053

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel TX 1 when the ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same as for the Tx1_Off register.

### Offset 0x0054: RxCh1_0_RxOn Register (R|W)

(show extended info)

RxCh1_0_RxOn
offset=0x0054

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 1 when the ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same as for the RxCh1_0_Idle register.

### Offset 0x0055: RxCh1_1_RxOn Register (R|W)

(show extended info)

RxCh1_1_RxOn
offset=0x0055

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 1 when the ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same as for the RxCh1_1_Idle register.

### Offset 0x0060: TxCh2_Idle Register (R|W)

(show extended info)

TxCh2_Idle
offset=0x0060

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel TX 2 when the ATR bits are configured: TX = 0, RX = don't-care. The bitfields are the same as for the Tx1_Off register.

### Offset 0x0061: RxCh2_0_Idle Register (R|W)

(show extended info)

RxCh2_0_Idle
offset=0x0061

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 2 when the ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same as for the RxCh1_0_Idle register.

### Offset 0x0062: RxCh2_1_Idle Register (R|W)

(show extended info)

RxCh2_1_Idle
offset=0x0062

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 2 when the ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same as for the RxCh1_1_Idle register.

### Offset 0x0063: TxCh2_TxOn Register (R|W)

(show extended info)

TxCh2_TxOn
offset=0x0063

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel TX 2 when the ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same as for the Tx1_Off register.

### Offset 0x0064: RxCh2_0_RxOn Register (R|W)

(show extended info)

RxCh2_0_RxOn
offset=0x0064

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 2 when the ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same as for the RxCh1_0_Idle register.

### Offset 0x0065: RxCh2_1_RxOn Register (R|W)

(show extended info)

RxCh2_1_RxOn
offset=0x0065

Initial Value not specified

This register is defined in HDL source file TopCpld.vhd.

Load this register with the front-end configuration for channel RX 2 when the ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same as for the RxCh1_1_Idle register.