/*
 * Copyright (c) 2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 */
/*                                                                           */
/* File:       /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg_map_macro.h*/
/* Creator:    irshad                                                        */
/* Time:       Wednesday Feb 15, 2012 [5:06:37 pm]                           */
/*                                                                           */
/* Path:       /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
/* Arguments:  /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -dump      */
/*             -codegen                                                      */
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.codegen*/
/*             -ath_ansic -Wdesc -I                                          */
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
/*             -I /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint */
/*             -I                                                            */
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint*/
/*             -I                                                            */
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig*/
/*             -odir                                                         */
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
/*             -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval                      */
/*             $WAR_EV58615_for_ansic_codegen=1 scorpion_reg.rdl             */
/*                                                                           */
/* Sources:    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/
/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm*/
/*             /cad/local/lib/perl/Pinfo.pm                                  */
/*                                                                           */
/* Blueprint:   3.7.3 (Fri Aug 29 12:39:16 PDT 2008)                         */
/* Machine:    rupavathi.users.atheros.com                                   */
/* OS:         Linux 2.6.9-89.ELsmp                                          */
/* Description:                                                              */
/*                                                                           */
/*This Register Map contains the complete register set for scorpion.         */
/*                                                                           */
/* Copyright (C) 2012 Denali Software Inc.  All rights reserved              */
/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
/*                                                                           */


#ifndef __REG_SCORPION_REG_MAP_MACRO_H__
#define __REG_SCORPION_REG_MAP_MACRO_H__


/* macros for BlueprintGlobalNameSpace::MAC_DMA_CR */
#ifndef __MAC_DMA_CR_MACRO__
#define __MAC_DMA_CR_MACRO__

/* macros for field RXE_LP */
#define MAC_DMA_CR__RXE_LP__SHIFT                                             2
#define MAC_DMA_CR__RXE_LP__WIDTH                                             1
#define MAC_DMA_CR__RXE_LP__MASK                                    0x00000004U
#define MAC_DMA_CR__RXE_LP__READ(src)   (((u_int32_t)(src) & 0x00000004U) >> 2)
#define MAC_DMA_CR__RXE_LP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_DMA_CR__RXE_LP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field RXE_HP */
#define MAC_DMA_CR__RXE_HP__SHIFT                                             3
#define MAC_DMA_CR__RXE_HP__WIDTH                                             1
#define MAC_DMA_CR__RXE_HP__MASK                                    0x00000008U
#define MAC_DMA_CR__RXE_HP__READ(src)   (((u_int32_t)(src) & 0x00000008U) >> 3)
#define MAC_DMA_CR__RXE_HP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_DMA_CR__RXE_HP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field RXD */
#define MAC_DMA_CR__RXD__SHIFT                                                5
#define MAC_DMA_CR__RXD__WIDTH                                                1
#define MAC_DMA_CR__RXD__MASK                                       0x00000020U
#define MAC_DMA_CR__RXD__READ(src)      (((u_int32_t)(src) & 0x00000020U) >> 5)
#define MAC_DMA_CR__RXD__WRITE(src)     (((u_int32_t)(src) << 5) & 0x00000020U)
#define MAC_DMA_CR__RXD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_DMA_CR__RXD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_DMA_CR__RXD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_DMA_CR__RXD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field SWI */
#define MAC_DMA_CR__SWI__SHIFT                                                6
#define MAC_DMA_CR__SWI__WIDTH                                                1
#define MAC_DMA_CR__SWI__MASK                                       0x00000040U
#define MAC_DMA_CR__SWI__READ(src)      (((u_int32_t)(src) & 0x00000040U) >> 6)
#define MAC_DMA_CR__SWI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_DMA_CR__SWI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field SPARE */
#define MAC_DMA_CR__SPARE__SHIFT                                              7
#define MAC_DMA_CR__SPARE__WIDTH                                              4
#define MAC_DMA_CR__SPARE__MASK                                     0x00000780U
#define MAC_DMA_CR__SPARE__READ(src)    (((u_int32_t)(src) & 0x00000780U) >> 7)
#define MAC_DMA_CR__SPARE__WRITE(src)   (((u_int32_t)(src) << 7) & 0x00000780U)
#define MAC_DMA_CR__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000780U) | (((u_int32_t)(src) <<\
                    7) & 0x00000780U)
#define MAC_DMA_CR__SPARE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000780U)))
#define MAC_DMA_CR__TYPE                                              u_int32_t
#define MAC_DMA_CR__READ                                            0x000007ecU
#define MAC_DMA_CR__WRITE                                           0x000007ecU

#endif /* __MAC_DMA_CR_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_CR */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_CR__NUM                                 1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_CFG */
#ifndef __MAC_DMA_CFG_MACRO__
#define __MAC_DMA_CFG_MACRO__

/* macros for field BE_MODE_XMIT_DESC */
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SHIFT                                 0
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WIDTH                                 1
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MASK                        0x00000001U
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field BE_MODE_XMIT_DATA */
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SHIFT                                 1
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WIDTH                                 1
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MASK                        0x00000002U
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field BE_MODE_RCV_DESC */
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SHIFT                                  2
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WIDTH                                  1
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MASK                         0x00000004U
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_DMA_CFG__BE_MODE_RCV_DESC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field BE_MODE_RCV_DATA */
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SHIFT                                  3
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WIDTH                                  1
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MASK                         0x00000008U
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_DMA_CFG__BE_MODE_RCV_DATA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field BE_MODE_MMR */
#define MAC_DMA_CFG__BE_MODE_MMR__SHIFT                                       4
#define MAC_DMA_CFG__BE_MODE_MMR__WIDTH                                       1
#define MAC_DMA_CFG__BE_MODE_MMR__MASK                              0x00000010U
#define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_DMA_CFG__BE_MODE_MMR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_DMA_CFG__BE_MODE_MMR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field ADHOC */
#define MAC_DMA_CFG__ADHOC__SHIFT                                             5
#define MAC_DMA_CFG__ADHOC__WIDTH                                             1
#define MAC_DMA_CFG__ADHOC__MASK                                    0x00000020U
#define MAC_DMA_CFG__ADHOC__READ(src)   (((u_int32_t)(src) & 0x00000020U) >> 5)
#define MAC_DMA_CFG__ADHOC__WRITE(src)  (((u_int32_t)(src) << 5) & 0x00000020U)
#define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_DMA_CFG__ADHOC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_DMA_CFG__ADHOC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_DMA_CFG__ADHOC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field PHY_OK */
#define MAC_DMA_CFG__PHY_OK__SHIFT                                            8
#define MAC_DMA_CFG__PHY_OK__WIDTH                                            1
#define MAC_DMA_CFG__PHY_OK__MASK                                   0x00000100U
#define MAC_DMA_CFG__PHY_OK__READ(src)  (((u_int32_t)(src) & 0x00000100U) >> 8)
#define MAC_DMA_CFG__PHY_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_DMA_CFG__PHY_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field EEPROM_BUSY */
#define MAC_DMA_CFG__EEPROM_BUSY__SHIFT                                       9
#define MAC_DMA_CFG__EEPROM_BUSY__WIDTH                                       1
#define MAC_DMA_CFG__EEPROM_BUSY__MASK                              0x00000200U
#define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_DMA_CFG__EEPROM_BUSY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_DMA_CFG__EEPROM_BUSY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field CLKGATE_DIS */
#define MAC_DMA_CFG__CLKGATE_DIS__SHIFT                                      10
#define MAC_DMA_CFG__CLKGATE_DIS__WIDTH                                       1
#define MAC_DMA_CFG__CLKGATE_DIS__MASK                              0x00000400U
#define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_DMA_CFG__CLKGATE_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_DMA_CFG__CLKGATE_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field HALT_REQ */
#define MAC_DMA_CFG__HALT_REQ__SHIFT                                         11
#define MAC_DMA_CFG__HALT_REQ__WIDTH                                          1
#define MAC_DMA_CFG__HALT_REQ__MASK                                 0x00000800U
#define MAC_DMA_CFG__HALT_REQ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_DMA_CFG__HALT_REQ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_DMA_CFG__HALT_REQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_DMA_CFG__HALT_REQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field HALT_ACK */
#define MAC_DMA_CFG__HALT_ACK__SHIFT                                         12
#define MAC_DMA_CFG__HALT_ACK__WIDTH                                          1
#define MAC_DMA_CFG__HALT_ACK__MASK                                 0x00001000U
#define MAC_DMA_CFG__HALT_ACK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_DMA_CFG__HALT_ACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_DMA_CFG__HALT_ACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field REQ_Q_FULL_THRESHOLD */
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__SHIFT                             17
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WIDTH                              2
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MASK                     0x00060000U
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00060000U) >> 17)
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00060000U)
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00060000U) | (((u_int32_t)(src) <<\
                    17) & 0x00060000U)
#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00060000U)))

/* macros for field MISSING_TX_INTR_FIX_ENABLE */
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SHIFT                       19
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WIDTH                        1
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MASK               0x00080000U
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field LEGACY_INT_MIT_MODE_ENABLE */
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SHIFT                       20
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WIDTH                        1
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MASK               0x00100000U
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field RESET_INT_MIT_CNTRS */
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SHIFT                              21
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WIDTH                               1
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MASK                      0x00200000U
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)
#define MAC_DMA_CFG__TYPE                                             u_int32_t
#define MAC_DMA_CFG__READ                                           0x003e1f3fU
#define MAC_DMA_CFG__WRITE                                          0x003e1f3fU

#endif /* __MAC_DMA_CFG_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_CFG */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_CFG__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXBUFPTR_THRESH */
#ifndef __MAC_DMA_RXBUFPTR_THRESH_MACRO__
#define __MAC_DMA_RXBUFPTR_THRESH_MACRO__

/* macros for field HP_DATA */
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__SHIFT                               0
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WIDTH                               4
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MASK                      0x0000000fU
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field LP_DATA */
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__SHIFT                               8
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WIDTH                               7
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MASK                      0x00007f00U
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007f00U) >> 8)
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00007f00U)
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00007f00U)
#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00007f00U)))
#define MAC_DMA_RXBUFPTR_THRESH__TYPE                                 u_int32_t
#define MAC_DMA_RXBUFPTR_THRESH__READ                               0x00007f0fU
#define MAC_DMA_RXBUFPTR_THRESH__WRITE                              0x00007f0fU

#endif /* __MAC_DMA_RXBUFPTR_THRESH_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RXBUFPTR_THRESH */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXBUFPTR_THRESH__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXDPPTR_THRESH */
#ifndef __MAC_DMA_TXDPPTR_THRESH_MACRO__
#define __MAC_DMA_TXDPPTR_THRESH_MACRO__

/* macros for field DATA */
#define MAC_DMA_TXDPPTR_THRESH__DATA__SHIFT                                   0
#define MAC_DMA_TXDPPTR_THRESH__DATA__WIDTH                                   4
#define MAC_DMA_TXDPPTR_THRESH__DATA__MASK                          0x0000000fU
#define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src)  (u_int32_t)(src) & 0x0000000fU
#define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))
#define MAC_DMA_TXDPPTR_THRESH__TYPE                                  u_int32_t
#define MAC_DMA_TXDPPTR_THRESH__READ                                0x0000000fU
#define MAC_DMA_TXDPPTR_THRESH__WRITE                               0x0000000fU

#endif /* __MAC_DMA_TXDPPTR_THRESH_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TXDPPTR_THRESH */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXDPPTR_THRESH__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIRT */
#ifndef __MAC_DMA_MIRT_MACRO__
#define __MAC_DMA_MIRT_MACRO__

/* macros for field RATE_THRESH */
#define MAC_DMA_MIRT__RATE_THRESH__SHIFT                                      0
#define MAC_DMA_MIRT__RATE_THRESH__WIDTH                                     16
#define MAC_DMA_MIRT__RATE_THRESH__MASK                             0x0000ffffU
#define MAC_DMA_MIRT__RATE_THRESH__READ(src)     (u_int32_t)(src) & 0x0000ffffU
#define MAC_DMA_MIRT__RATE_THRESH__WRITE(src)  ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_DMA_MIRT__TYPE                                            u_int32_t
#define MAC_DMA_MIRT__READ                                          0x0000ffffU
#define MAC_DMA_MIRT__WRITE                                         0x0000ffffU

#endif /* __MAC_DMA_MIRT_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_MIRT */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_MIRT__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_GLOBAL_IER */
#ifndef __MAC_DMA_GLOBAL_IER_MACRO__
#define __MAC_DMA_GLOBAL_IER_MACRO__

/* macros for field ENABLE */
#define MAC_DMA_GLOBAL_IER__ENABLE__SHIFT                                     0
#define MAC_DMA_GLOBAL_IER__ENABLE__WIDTH                                     1
#define MAC_DMA_GLOBAL_IER__ENABLE__MASK                            0x00000001U
#define MAC_DMA_GLOBAL_IER__ENABLE__READ(src)    (u_int32_t)(src) & 0x00000001U
#define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
#define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_DMA_GLOBAL_IER__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_DMA_GLOBAL_IER__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define MAC_DMA_GLOBAL_IER__TYPE                                      u_int32_t
#define MAC_DMA_GLOBAL_IER__READ                                    0x00000001U
#define MAC_DMA_GLOBAL_IER__WRITE                                   0x00000001U

#endif /* __MAC_DMA_GLOBAL_IER_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_GLOBAL_IER */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_GLOBAL_IER__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_alias */
#ifndef __MAC_DMA_TIMT_ALIAS_MACRO__
#define __MAC_DMA_TIMT_ALIAS_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__SHIFT                         0
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WIDTH                        16
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MASK                0x0000ffffU
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__SHIFT                       16
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WIDTH                       16
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MASK               0xffff0000U
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_ALIAS__TYPE                                      u_int32_t
#define MAC_DMA_TIMT_ALIAS__READ                                    0xffffffffU
#define MAC_DMA_TIMT_ALIAS__WRITE                                   0xffffffffU

#endif /* __MAC_DMA_TIMT_ALIAS_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RIMT */
#ifndef __MAC_DMA_RIMT_MACRO__
#define __MAC_DMA_RIMT_MACRO__

/* macros for field RX_LAST_PKT_THRESH */
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__SHIFT                               0
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WIDTH                              16
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MASK                      0x0000ffffU
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field RX_FIRST_PKT_THRESH */
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__SHIFT                             16
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WIDTH                             16
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MASK                     0xffff0000U
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_RIMT__TYPE                                            u_int32_t
#define MAC_DMA_RIMT__READ                                          0xffffffffU
#define MAC_DMA_RIMT__WRITE                                         0xffffffffU

#endif /* __MAC_DMA_RIMT_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RIMT */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RIMT__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXCFG */
#ifndef __MAC_DMA_TXCFG_MACRO__
#define __MAC_DMA_TXCFG_MACRO__

/* macros for field DMA_SIZE */
#define MAC_DMA_TXCFG__DMA_SIZE__SHIFT                                        0
#define MAC_DMA_TXCFG__DMA_SIZE__WIDTH                                        3
#define MAC_DMA_TXCFG__DMA_SIZE__MASK                               0x00000007U
#define MAC_DMA_TXCFG__DMA_SIZE__READ(src)       (u_int32_t)(src) & 0x00000007U
#define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src)    ((u_int32_t)(src) & 0x00000007U)
#define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field TRIGLVL */
#define MAC_DMA_TXCFG__TRIGLVL__SHIFT                                         4
#define MAC_DMA_TXCFG__TRIGLVL__WIDTH                                         6
#define MAC_DMA_TXCFG__TRIGLVL__MASK                                0x000003f0U
#define MAC_DMA_TXCFG__TRIGLVL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field JUMBO_EN */
#define MAC_DMA_TXCFG__JUMBO_EN__SHIFT                                       10
#define MAC_DMA_TXCFG__JUMBO_EN__WIDTH                                        1
#define MAC_DMA_TXCFG__JUMBO_EN__MASK                               0x00000400U
#define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_DMA_TXCFG__JUMBO_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_DMA_TXCFG__JUMBO_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field BCN_PAST_ATIM_DIS */
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SHIFT                              11
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WIDTH                               1
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MASK                      0x00000800U
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field ATIM_DEFER_DIS */
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SHIFT                                 12
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WIDTH                                  1
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MASK                         0x00001000U
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field RTCI_DIS */
#define MAC_DMA_TXCFG__RTCI_DIS__SHIFT                                       14
#define MAC_DMA_TXCFG__RTCI_DIS__WIDTH                                        1
#define MAC_DMA_TXCFG__RTCI_DIS__MASK                               0x00004000U
#define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define MAC_DMA_TXCFG__RTCI_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define MAC_DMA_TXCFG__RTCI_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field DIS_RETRY_UNDERRUN */
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SHIFT                             17
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WIDTH                              1
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MASK                     0x00020000U
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field DIS_CW_INC_QUIET_COLL */
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SHIFT                          18
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WIDTH                           1
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MASK                  0x00040000U
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field RTS_FAIL_EXCESSIVE_RETRIES */
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SHIFT                     19
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WIDTH                      1
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MASK             0x00080000U
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)
#define MAC_DMA_TXCFG__TYPE                                           u_int32_t
#define MAC_DMA_TXCFG__READ                                         0x000e5ff7U
#define MAC_DMA_TXCFG__WRITE                                        0x000e5ff7U

#endif /* __MAC_DMA_TXCFG_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TXCFG */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXCFG__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXCFG */
#ifndef __MAC_DMA_RXCFG_MACRO__
#define __MAC_DMA_RXCFG_MACRO__

/* macros for field DMA_SIZE */
#define MAC_DMA_RXCFG__DMA_SIZE__SHIFT                                        0
#define MAC_DMA_RXCFG__DMA_SIZE__WIDTH                                        3
#define MAC_DMA_RXCFG__DMA_SIZE__MASK                               0x00000007U
#define MAC_DMA_RXCFG__DMA_SIZE__READ(src)       (u_int32_t)(src) & 0x00000007U
#define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src)    ((u_int32_t)(src) & 0x00000007U)
#define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field ZERO_LEN_DMA_EN */
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__SHIFT                                 3
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WIDTH                                 2
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MASK                        0x00000018U
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000018U) >> 3)
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000018U)
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000018U) | (((u_int32_t)(src) <<\
                    3) & 0x00000018U)
#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000018U)))

/* macros for field JUMBO_EN */
#define MAC_DMA_RXCFG__JUMBO_EN__SHIFT                                        5
#define MAC_DMA_RXCFG__JUMBO_EN__WIDTH                                        1
#define MAC_DMA_RXCFG__JUMBO_EN__MASK                               0x00000020U
#define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_DMA_RXCFG__JUMBO_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_DMA_RXCFG__JUMBO_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field JUMBO_WRAP_EN */
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SHIFT                                   6
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WIDTH                                   1
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MASK                          0x00000040U
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field SLEEP_RX_PEND_EN */
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SHIFT                                7
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WIDTH                                1
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MASK                       0x00000080U
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)
#define MAC_DMA_RXCFG__TYPE                                           u_int32_t
#define MAC_DMA_RXCFG__READ                                         0x000000ffU
#define MAC_DMA_RXCFG__WRITE                                        0x000000ffU

#endif /* __MAC_DMA_RXCFG_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RXCFG */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXCFG__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXJLA */
#ifndef __MAC_DMA_RXJLA_MACRO__
#define __MAC_DMA_RXJLA_MACRO__

/* macros for field DATA */
#define MAC_DMA_RXJLA__DATA__SHIFT                                            2
#define MAC_DMA_RXJLA__DATA__WIDTH                                           30
#define MAC_DMA_RXJLA__DATA__MASK                                   0xfffffffcU
#define MAC_DMA_RXJLA__DATA__READ(src)  (((u_int32_t)(src) & 0xfffffffcU) >> 2)
#define MAC_DMA_RXJLA__TYPE                                           u_int32_t
#define MAC_DMA_RXJLA__READ                                         0xfffffffcU

#endif /* __MAC_DMA_RXJLA_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RXJLA */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXJLA__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIBC */
#ifndef __MAC_DMA_MIBC_MACRO__
#define __MAC_DMA_MIBC_MACRO__

/* macros for field WARNING */
#define MAC_DMA_MIBC__WARNING__SHIFT                                          0
#define MAC_DMA_MIBC__WARNING__WIDTH                                          1
#define MAC_DMA_MIBC__WARNING__MASK                                 0x00000001U
#define MAC_DMA_MIBC__WARNING__READ(src)         (u_int32_t)(src) & 0x00000001U
#define MAC_DMA_MIBC__WARNING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_DMA_MIBC__WARNING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field FREEZE */
#define MAC_DMA_MIBC__FREEZE__SHIFT                                           1
#define MAC_DMA_MIBC__FREEZE__WIDTH                                           1
#define MAC_DMA_MIBC__FREEZE__MASK                                  0x00000002U
#define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
#define MAC_DMA_MIBC__FREEZE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_DMA_MIBC__FREEZE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_DMA_MIBC__FREEZE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_DMA_MIBC__FREEZE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field CLEAR */
#define MAC_DMA_MIBC__CLEAR__SHIFT                                            2
#define MAC_DMA_MIBC__CLEAR__WIDTH                                            1
#define MAC_DMA_MIBC__CLEAR__MASK                                   0x00000004U
#define MAC_DMA_MIBC__CLEAR__READ(src)  (((u_int32_t)(src) & 0x00000004U) >> 2)
#define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
#define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_DMA_MIBC__CLEAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_DMA_MIBC__CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_DMA_MIBC__CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field STROBE */
#define MAC_DMA_MIBC__STROBE__SHIFT                                           3
#define MAC_DMA_MIBC__STROBE__WIDTH                                           1
#define MAC_DMA_MIBC__STROBE__MASK                                  0x00000008U
#define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
#define MAC_DMA_MIBC__STROBE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_DMA_MIBC__STROBE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)
#define MAC_DMA_MIBC__TYPE                                            u_int32_t
#define MAC_DMA_MIBC__READ                                          0x0000000fU
#define MAC_DMA_MIBC__WRITE                                         0x0000000fU

#endif /* __MAC_DMA_MIBC_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_MIBC */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_MIBC__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TOPS */
#ifndef __MAC_DMA_TOPS_MACRO__
#define __MAC_DMA_TOPS_MACRO__

/* macros for field TIMEOUT */
#define MAC_DMA_TOPS__TIMEOUT__SHIFT                                          0
#define MAC_DMA_TOPS__TIMEOUT__WIDTH                                         16
#define MAC_DMA_TOPS__TIMEOUT__MASK                                 0x0000ffffU
#define MAC_DMA_TOPS__TIMEOUT__READ(src)         (u_int32_t)(src) & 0x0000ffffU
#define MAC_DMA_TOPS__TIMEOUT__WRITE(src)      ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_DMA_TOPS__TYPE                                            u_int32_t
#define MAC_DMA_TOPS__READ                                          0x0000ffffU
#define MAC_DMA_TOPS__WRITE                                         0x0000ffffU

#endif /* __MAC_DMA_TOPS_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TOPS */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TOPS__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXNPTO */
#ifndef __MAC_DMA_RXNPTO_MACRO__
#define __MAC_DMA_RXNPTO_MACRO__

/* macros for field TIMEOUT */
#define MAC_DMA_RXNPTO__TIMEOUT__SHIFT                                        0
#define MAC_DMA_RXNPTO__TIMEOUT__WIDTH                                       10
#define MAC_DMA_RXNPTO__TIMEOUT__MASK                               0x000003ffU
#define MAC_DMA_RXNPTO__TIMEOUT__READ(src)       (u_int32_t)(src) & 0x000003ffU
#define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src)    ((u_int32_t)(src) & 0x000003ffU)
#define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define MAC_DMA_RXNPTO__TYPE                                          u_int32_t
#define MAC_DMA_RXNPTO__READ                                        0x000003ffU
#define MAC_DMA_RXNPTO__WRITE                                       0x000003ffU

#endif /* __MAC_DMA_RXNPTO_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RXNPTO */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXNPTO__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXNPTO */
#ifndef __MAC_DMA_TXNPTO_MACRO__
#define __MAC_DMA_TXNPTO_MACRO__

/* macros for field TIMEOUT */
#define MAC_DMA_TXNPTO__TIMEOUT__SHIFT                                        0
#define MAC_DMA_TXNPTO__TIMEOUT__WIDTH                                       10
#define MAC_DMA_TXNPTO__TIMEOUT__MASK                               0x000003ffU
#define MAC_DMA_TXNPTO__TIMEOUT__READ(src)       (u_int32_t)(src) & 0x000003ffU
#define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src)    ((u_int32_t)(src) & 0x000003ffU)
#define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field MASK */
#define MAC_DMA_TXNPTO__MASK__SHIFT                                          10
#define MAC_DMA_TXNPTO__MASK__WIDTH                                          10
#define MAC_DMA_TXNPTO__MASK__MASK                                  0x000ffc00U
#define MAC_DMA_TXNPTO__MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define MAC_DMA_TXNPTO__MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define MAC_DMA_TXNPTO__MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))
#define MAC_DMA_TXNPTO__TYPE                                          u_int32_t
#define MAC_DMA_TXNPTO__READ                                        0x000fffffU
#define MAC_DMA_TXNPTO__WRITE                                       0x000fffffU

#endif /* __MAC_DMA_TXNPTO_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TXNPTO */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXNPTO__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RPGTO */
#ifndef __MAC_DMA_RPGTO_MACRO__
#define __MAC_DMA_RPGTO_MACRO__

/* macros for field TIMEOUT */
#define MAC_DMA_RPGTO__TIMEOUT__SHIFT                                         0
#define MAC_DMA_RPGTO__TIMEOUT__WIDTH                                        10
#define MAC_DMA_RPGTO__TIMEOUT__MASK                                0x000003ffU
#define MAC_DMA_RPGTO__TIMEOUT__READ(src)        (u_int32_t)(src) & 0x000003ffU
#define MAC_DMA_RPGTO__TIMEOUT__WRITE(src)     ((u_int32_t)(src) & 0x000003ffU)
#define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define MAC_DMA_RPGTO__TYPE                                           u_int32_t
#define MAC_DMA_RPGTO__READ                                         0x000003ffU
#define MAC_DMA_RPGTO__WRITE                                        0x000003ffU

#endif /* __MAC_DMA_RPGTO_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RPGTO */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RPGTO__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_MACMISC */
#ifndef __MAC_DMA_MACMISC_MACRO__
#define __MAC_DMA_MACMISC_MACRO__

/* macros for field FORCE_PCI_EXT */
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SHIFT                                 4
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WIDTH                                 1
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MASK                        0x00000010U
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_DMA_MACMISC__FORCE_PCI_EXT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field DMA_OBS_MUXSEL */
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__SHIFT                                5
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WIDTH                                4
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MASK                       0x000001e0U
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001e0U) >> 5)
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000001e0U)
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000001e0U)
#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000001e0U)))

/* macros for field MISC_OBS_MUXSEL */
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__SHIFT                               9
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WIDTH                               3
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MASK                      0x00000e00U
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000e00U) >> 9)
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000e00U)
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field MISC_F2_OBS_LOW_MUXSEL */
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__SHIFT                       12
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WIDTH                        3
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MASK               0x00007000U
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007000U) >> 12)
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00007000U)
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field MISC_F2_OBS_HIGH_MUXSEL */
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__SHIFT                      15
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WIDTH                       3
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MASK              0x00038000U
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00038000U) >> 15)
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00038000U)
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00038000U)))
#define MAC_DMA_MACMISC__TYPE                                         u_int32_t
#define MAC_DMA_MACMISC__READ                                       0x0003fff0U
#define MAC_DMA_MACMISC__WRITE                                      0x0003fff0U

#endif /* __MAC_DMA_MACMISC_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_MACMISC */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_MACMISC__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_INTER */
#ifndef __MAC_DMA_INTER_MACRO__
#define __MAC_DMA_INTER_MACRO__

/* macros for field REQ */
#define MAC_DMA_INTER__REQ__SHIFT                                             0
#define MAC_DMA_INTER__REQ__WIDTH                                             1
#define MAC_DMA_INTER__REQ__MASK                                    0x00000001U
#define MAC_DMA_INTER__REQ__READ(src)            (u_int32_t)(src) & 0x00000001U
#define MAC_DMA_INTER__REQ__WRITE(src)         ((u_int32_t)(src) & 0x00000001U)
#define MAC_DMA_INTER__REQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_DMA_INTER__REQ__VERIFY(src)  (!(((u_int32_t)(src) & ~0x00000001U)))
#define MAC_DMA_INTER__REQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_DMA_INTER__REQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field MSI_RX_SRC */
#define MAC_DMA_INTER__MSI_RX_SRC__SHIFT                                      1
#define MAC_DMA_INTER__MSI_RX_SRC__WIDTH                                      2
#define MAC_DMA_INTER__MSI_RX_SRC__MASK                             0x00000006U
#define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000006U) >> 1)
#define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000006U)
#define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000006U) | (((u_int32_t)(src) <<\
                    1) & 0x00000006U)
#define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000006U)))

/* macros for field MSI_TX_SRC */
#define MAC_DMA_INTER__MSI_TX_SRC__SHIFT                                      3
#define MAC_DMA_INTER__MSI_TX_SRC__WIDTH                                      2
#define MAC_DMA_INTER__MSI_TX_SRC__MASK                             0x00000018U
#define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000018U) >> 3)
#define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000018U)
#define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000018U) | (((u_int32_t)(src) <<\
                    3) & 0x00000018U)
#define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000018U)))
#define MAC_DMA_INTER__TYPE                                           u_int32_t
#define MAC_DMA_INTER__READ                                         0x0000001fU
#define MAC_DMA_INTER__WRITE                                        0x0000001fU

#endif /* __MAC_DMA_INTER_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_INTER */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_INTER__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DATABUF */
#ifndef __MAC_DMA_DATABUF_MACRO__
#define __MAC_DMA_DATABUF_MACRO__

/* macros for field LEN */
#define MAC_DMA_DATABUF__LEN__SHIFT                                           0
#define MAC_DMA_DATABUF__LEN__WIDTH                                          12
#define MAC_DMA_DATABUF__LEN__MASK                                  0x00000fffU
#define MAC_DMA_DATABUF__LEN__READ(src)          (u_int32_t)(src) & 0x00000fffU
#define MAC_DMA_DATABUF__LEN__WRITE(src)       ((u_int32_t)(src) & 0x00000fffU)
#define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define MAC_DMA_DATABUF__LEN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))
#define MAC_DMA_DATABUF__TYPE                                         u_int32_t
#define MAC_DMA_DATABUF__READ                                       0x00000fffU
#define MAC_DMA_DATABUF__WRITE                                      0x00000fffU

#endif /* __MAC_DMA_DATABUF_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DATABUF */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DATABUF__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTT */
#ifndef __MAC_DMA_GTT_MACRO__
#define __MAC_DMA_GTT_MACRO__

/* macros for field COUNT */
#define MAC_DMA_GTT__COUNT__SHIFT                                             0
#define MAC_DMA_GTT__COUNT__WIDTH                                            16
#define MAC_DMA_GTT__COUNT__MASK                                    0x0000ffffU
#define MAC_DMA_GTT__COUNT__READ(src)            (u_int32_t)(src) & 0x0000ffffU
#define MAC_DMA_GTT__COUNT__WRITE(src)         ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_GTT__COUNT__VERIFY(src)  (!(((u_int32_t)(src) & ~0x0000ffffU)))

/* macros for field LIMIT */
#define MAC_DMA_GTT__LIMIT__SHIFT                                            16
#define MAC_DMA_GTT__LIMIT__WIDTH                                            16
#define MAC_DMA_GTT__LIMIT__MASK                                    0xffff0000U
#define MAC_DMA_GTT__LIMIT__READ(src)  (((u_int32_t)(src) & 0xffff0000U) >> 16)
#define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
#define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_GTT__LIMIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_GTT__TYPE                                             u_int32_t
#define MAC_DMA_GTT__READ                                           0xffffffffU
#define MAC_DMA_GTT__WRITE                                          0xffffffffU

#endif /* __MAC_DMA_GTT_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_GTT */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_GTT__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTTM */
#ifndef __MAC_DMA_GTTM_MACRO__
#define __MAC_DMA_GTTM_MACRO__

/* macros for field USEC_STROBE */
#define MAC_DMA_GTTM__USEC_STROBE__SHIFT                                      0
#define MAC_DMA_GTTM__USEC_STROBE__WIDTH                                      1
#define MAC_DMA_GTTM__USEC_STROBE__MASK                             0x00000001U
#define MAC_DMA_GTTM__USEC_STROBE__READ(src)     (u_int32_t)(src) & 0x00000001U
#define MAC_DMA_GTTM__USEC_STROBE__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
#define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_DMA_GTTM__USEC_STROBE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_DMA_GTTM__USEC_STROBE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field IGNORE_CHAN_IDLE */
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SHIFT                                 1
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WIDTH                                 1
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MASK                        0x00000002U
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field RESET_ON_CHAN_IDLE */
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SHIFT                               2
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WIDTH                               1
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MASK                      0x00000004U
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field CST_USEC_STROBE */
#define MAC_DMA_GTTM__CST_USEC_STROBE__SHIFT                                  3
#define MAC_DMA_GTTM__CST_USEC_STROBE__WIDTH                                  1
#define MAC_DMA_GTTM__CST_USEC_STROBE__MASK                         0x00000008U
#define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_DMA_GTTM__CST_USEC_STROBE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_DMA_GTTM__CST_USEC_STROBE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field DISABLE_QCU_FR_ACTIVE_GTT */
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SHIFT                        4
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WIDTH                        1
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MASK               0x00000010U
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field DISABLE_QCU_FR_ACTIVE_BT */
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SHIFT                         5
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WIDTH                         1
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MASK                0x00000020U
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define MAC_DMA_GTTM__TYPE                                            u_int32_t
#define MAC_DMA_GTTM__READ                                          0x0000003fU
#define MAC_DMA_GTTM__WRITE                                         0x0000003fU

#endif /* __MAC_DMA_GTTM_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_GTTM */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_GTTM__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_CST */
#ifndef __MAC_DMA_CST_MACRO__
#define __MAC_DMA_CST_MACRO__

/* macros for field COUNT */
#define MAC_DMA_CST__COUNT__SHIFT                                             0
#define MAC_DMA_CST__COUNT__WIDTH                                            16
#define MAC_DMA_CST__COUNT__MASK                                    0x0000ffffU
#define MAC_DMA_CST__COUNT__READ(src)            (u_int32_t)(src) & 0x0000ffffU
#define MAC_DMA_CST__COUNT__WRITE(src)         ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_DMA_CST__COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_CST__COUNT__VERIFY(src)  (!(((u_int32_t)(src) & ~0x0000ffffU)))

/* macros for field LIMIT */
#define MAC_DMA_CST__LIMIT__SHIFT                                            16
#define MAC_DMA_CST__LIMIT__WIDTH                                            16
#define MAC_DMA_CST__LIMIT__MASK                                    0xffff0000U
#define MAC_DMA_CST__LIMIT__READ(src)  (((u_int32_t)(src) & 0xffff0000U) >> 16)
#define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
#define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_CST__LIMIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_CST__TYPE                                             u_int32_t
#define MAC_DMA_CST__READ                                           0xffffffffU
#define MAC_DMA_CST__WRITE                                          0xffffffffU

#endif /* __MAC_DMA_CST_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_CST */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_CST__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXDP_SIZE */
#ifndef __MAC_DMA_RXDP_SIZE_MACRO__
#define __MAC_DMA_RXDP_SIZE_MACRO__

/* macros for field LP */
#define MAC_DMA_RXDP_SIZE__LP__SHIFT                                          0
#define MAC_DMA_RXDP_SIZE__LP__WIDTH                                          8
#define MAC_DMA_RXDP_SIZE__LP__MASK                                 0x000000ffU
#define MAC_DMA_RXDP_SIZE__LP__READ(src)         (u_int32_t)(src) & 0x000000ffU

/* macros for field HP */
#define MAC_DMA_RXDP_SIZE__HP__SHIFT                                          8
#define MAC_DMA_RXDP_SIZE__HP__WIDTH                                          5
#define MAC_DMA_RXDP_SIZE__HP__MASK                                 0x00001f00U
#define MAC_DMA_RXDP_SIZE__HP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define MAC_DMA_RXDP_SIZE__TYPE                                       u_int32_t
#define MAC_DMA_RXDP_SIZE__READ                                     0x00001fffU

#endif /* __MAC_DMA_RXDP_SIZE_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RXDP_SIZE */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXDP_SIZE__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_HP_RXDP */
#ifndef __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__
#define __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__

/* macros for field ADDR */
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__SHIFT                                 0
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WIDTH                                32
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MASK                        0xffffffffU
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_RX_QUEUE_HP_RXDP__TYPE                                u_int32_t
#define MAC_DMA_RX_QUEUE_HP_RXDP__READ                              0xffffffffU
#define MAC_DMA_RX_QUEUE_HP_RXDP__WRITE                             0xffffffffU

#endif /* __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_HP_RXDP */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_HP_RXDP__NUM                   1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_LP_RXDP */
#ifndef __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__
#define __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__

/* macros for field ADDR */
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__SHIFT                                 0
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WIDTH                                32
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MASK                        0xffffffffU
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_RX_QUEUE_LP_RXDP__TYPE                                u_int32_t
#define MAC_DMA_RX_QUEUE_LP_RXDP__READ                              0xffffffffU
#define MAC_DMA_RX_QUEUE_LP_RXDP__WRITE                             0xffffffffU

#endif /* __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_LP_RXDP */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_LP_RXDP__NUM                   1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P */
#ifndef __MAC_DMA_ISR_P_MACRO__
#define __MAC_DMA_ISR_P_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_P__DATA__SHIFT                                            0
#define MAC_DMA_ISR_P__DATA__WIDTH                                           32
#define MAC_DMA_ISR_P__DATA__MASK                                   0xffffffffU
#define MAC_DMA_ISR_P__DATA__READ(src)           (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_P__DATA__WRITE(src)        ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
#define MAC_DMA_ISR_P__TYPE                                           u_int32_t
#define MAC_DMA_ISR_P__READ                                         0xffffffffU
#define MAC_DMA_ISR_P__WRITE                                        0xffffffffU

#endif /* __MAC_DMA_ISR_P_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_P */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0 */
#ifndef __MAC_DMA_ISR_S0_MACRO__
#define __MAC_DMA_ISR_S0_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_S0__DATA__SHIFT                                           0
#define MAC_DMA_ISR_S0__DATA__WIDTH                                          32
#define MAC_DMA_ISR_S0__DATA__MASK                                  0xffffffffU
#define MAC_DMA_ISR_S0__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S0__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_S0__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_ISR_S0__TYPE                                          u_int32_t
#define MAC_DMA_ISR_S0__READ                                        0xffffffffU
#define MAC_DMA_ISR_S0__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_ISR_S0_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S0 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1 */
#ifndef __MAC_DMA_ISR_S1_MACRO__
#define __MAC_DMA_ISR_S1_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_S1__DATA__SHIFT                                           0
#define MAC_DMA_ISR_S1__DATA__WIDTH                                          32
#define MAC_DMA_ISR_S1__DATA__MASK                                  0xffffffffU
#define MAC_DMA_ISR_S1__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S1__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_S1__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_ISR_S1__TYPE                                          u_int32_t
#define MAC_DMA_ISR_S1__READ                                        0xffffffffU
#define MAC_DMA_ISR_S1__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_ISR_S1_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S1 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2 */
#ifndef __MAC_DMA_ISR_S2_MACRO__
#define __MAC_DMA_ISR_S2_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_S2__DATA__SHIFT                                           0
#define MAC_DMA_ISR_S2__DATA__WIDTH                                          32
#define MAC_DMA_ISR_S2__DATA__MASK                                  0xffffffffU
#define MAC_DMA_ISR_S2__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S2__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_S2__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_ISR_S2__TYPE                                          u_int32_t
#define MAC_DMA_ISR_S2__READ                                        0xffffffffU
#define MAC_DMA_ISR_S2__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_ISR_S2_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S2 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3 */
#ifndef __MAC_DMA_ISR_S3_MACRO__
#define __MAC_DMA_ISR_S3_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_S3__DATA__SHIFT                                           0
#define MAC_DMA_ISR_S3__DATA__WIDTH                                          32
#define MAC_DMA_ISR_S3__DATA__MASK                                  0xffffffffU
#define MAC_DMA_ISR_S3__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S3__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_S3__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_ISR_S3__TYPE                                          u_int32_t
#define MAC_DMA_ISR_S3__READ                                        0xffffffffU
#define MAC_DMA_ISR_S3__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_ISR_S3_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S3 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4 */
#ifndef __MAC_DMA_ISR_S4_MACRO__
#define __MAC_DMA_ISR_S4_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_S4__DATA__SHIFT                                           0
#define MAC_DMA_ISR_S4__DATA__WIDTH                                          32
#define MAC_DMA_ISR_S4__DATA__MASK                                  0xffffffffU
#define MAC_DMA_ISR_S4__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S4__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_S4__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_ISR_S4__TYPE                                          u_int32_t
#define MAC_DMA_ISR_S4__READ                                        0xffffffffU
#define MAC_DMA_ISR_S4__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_ISR_S4_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S4 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5 */
#ifndef __MAC_DMA_ISR_S5_MACRO__
#define __MAC_DMA_ISR_S5_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_S5__DATA__SHIFT                                           0
#define MAC_DMA_ISR_S5__DATA__WIDTH                                          32
#define MAC_DMA_ISR_S5__DATA__MASK                                  0xffffffffU
#define MAC_DMA_ISR_S5__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S5__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_ISR_S5__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_ISR_S5__TYPE                                          u_int32_t
#define MAC_DMA_ISR_S5__READ                                        0xffffffffU
#define MAC_DMA_ISR_S5__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_ISR_S5_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S5 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_P */
#ifndef __MAC_DMA_IMR_P_MACRO__
#define __MAC_DMA_IMR_P_MACRO__

/* macros for field MASK */
#define MAC_DMA_IMR_P__MASK__SHIFT                                            0
#define MAC_DMA_IMR_P__MASK__WIDTH                                           32
#define MAC_DMA_IMR_P__MASK__MASK                                   0xffffffffU
#define MAC_DMA_IMR_P__MASK__READ(src)           (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_P__MASK__WRITE(src)        ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
#define MAC_DMA_IMR_P__TYPE                                           u_int32_t
#define MAC_DMA_IMR_P__READ                                         0xffffffffU
#define MAC_DMA_IMR_P__WRITE                                        0xffffffffU

#endif /* __MAC_DMA_IMR_P_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_P */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_P__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S0 */
#ifndef __MAC_DMA_IMR_S0_MACRO__
#define __MAC_DMA_IMR_S0_MACRO__

/* macros for field MASK */
#define MAC_DMA_IMR_S0__MASK__SHIFT                                           0
#define MAC_DMA_IMR_S0__MASK__WIDTH                                          32
#define MAC_DMA_IMR_S0__MASK__MASK                                  0xffffffffU
#define MAC_DMA_IMR_S0__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_S0__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_S0__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_IMR_S0__TYPE                                          u_int32_t
#define MAC_DMA_IMR_S0__READ                                        0xffffffffU
#define MAC_DMA_IMR_S0__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_IMR_S0_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_S0 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S0__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S1 */
#ifndef __MAC_DMA_IMR_S1_MACRO__
#define __MAC_DMA_IMR_S1_MACRO__

/* macros for field DATA */
#define MAC_DMA_IMR_S1__DATA__SHIFT                                           0
#define MAC_DMA_IMR_S1__DATA__WIDTH                                          32
#define MAC_DMA_IMR_S1__DATA__MASK                                  0xffffffffU
#define MAC_DMA_IMR_S1__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_S1__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_S1__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_IMR_S1__TYPE                                          u_int32_t
#define MAC_DMA_IMR_S1__READ                                        0xffffffffU
#define MAC_DMA_IMR_S1__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_IMR_S1_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_S1 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S1__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S2 */
#ifndef __MAC_DMA_IMR_S2_MACRO__
#define __MAC_DMA_IMR_S2_MACRO__

/* macros for field MASK */
#define MAC_DMA_IMR_S2__MASK__SHIFT                                           0
#define MAC_DMA_IMR_S2__MASK__WIDTH                                          32
#define MAC_DMA_IMR_S2__MASK__MASK                                  0xffffffffU
#define MAC_DMA_IMR_S2__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_S2__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_S2__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_IMR_S2__TYPE                                          u_int32_t
#define MAC_DMA_IMR_S2__READ                                        0xffffffffU
#define MAC_DMA_IMR_S2__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_IMR_S2_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_S2 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S2__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S3 */
#ifndef __MAC_DMA_IMR_S3_MACRO__
#define __MAC_DMA_IMR_S3_MACRO__

/* macros for field MASK */
#define MAC_DMA_IMR_S3__MASK__SHIFT                                           0
#define MAC_DMA_IMR_S3__MASK__WIDTH                                          32
#define MAC_DMA_IMR_S3__MASK__MASK                                  0xffffffffU
#define MAC_DMA_IMR_S3__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_S3__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_S3__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_IMR_S3__TYPE                                          u_int32_t
#define MAC_DMA_IMR_S3__READ                                        0xffffffffU
#define MAC_DMA_IMR_S3__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_IMR_S3_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_S3 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S3__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S4 */
#ifndef __MAC_DMA_IMR_S4_MACRO__
#define __MAC_DMA_IMR_S4_MACRO__

/* macros for field MASK */
#define MAC_DMA_IMR_S4__MASK__SHIFT                                           0
#define MAC_DMA_IMR_S4__MASK__WIDTH                                          32
#define MAC_DMA_IMR_S4__MASK__MASK                                  0xffffffffU
#define MAC_DMA_IMR_S4__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_S4__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_S4__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_IMR_S4__TYPE                                          u_int32_t
#define MAC_DMA_IMR_S4__READ                                        0xffffffffU
#define MAC_DMA_IMR_S4__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_IMR_S4_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_S4 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S4__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S5 */
#ifndef __MAC_DMA_IMR_S5_MACRO__
#define __MAC_DMA_IMR_S5_MACRO__

/* macros for field MASK */
#define MAC_DMA_IMR_S5__MASK__SHIFT                                           0
#define MAC_DMA_IMR_S5__MASK__WIDTH                                          32
#define MAC_DMA_IMR_S5__MASK__MASK                                  0xffffffffU
#define MAC_DMA_IMR_S5__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_IMR_S5__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DMA_IMR_S5__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DMA_IMR_S5__TYPE                                          u_int32_t
#define MAC_DMA_IMR_S5__READ                                        0xffffffffU
#define MAC_DMA_IMR_S5__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_IMR_S5_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_IMR_S5 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S5__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P_RAC */
#ifndef __MAC_DMA_ISR_P_RAC_MACRO__
#define __MAC_DMA_ISR_P_RAC_MACRO__

/* macros for field DATA */
#define MAC_DMA_ISR_P_RAC__DATA__SHIFT                                        0
#define MAC_DMA_ISR_P_RAC__DATA__WIDTH                                       32
#define MAC_DMA_ISR_P_RAC__DATA__MASK                               0xffffffffU
#define MAC_DMA_ISR_P_RAC__DATA__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_P_RAC__TYPE                                       u_int32_t
#define MAC_DMA_ISR_P_RAC__READ                                     0xffffffffU

#endif /* __MAC_DMA_ISR_P_RAC_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_P_RAC */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P_RAC__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0_S */
#ifndef __MAC_DMA_ISR_S0_S_MACRO__
#define __MAC_DMA_ISR_S0_S_MACRO__

/* macros for field SHADOW */
#define MAC_DMA_ISR_S0_S__SHADOW__SHIFT                                       0
#define MAC_DMA_ISR_S0_S__SHADOW__WIDTH                                      32
#define MAC_DMA_ISR_S0_S__SHADOW__MASK                              0xffffffffU
#define MAC_DMA_ISR_S0_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S0_S__TYPE                                        u_int32_t
#define MAC_DMA_ISR_S0_S__READ                                      0xffffffffU

#endif /* __MAC_DMA_ISR_S0_S_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S0_S */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0_S__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1_S */
#ifndef __MAC_DMA_ISR_S1_S_MACRO__
#define __MAC_DMA_ISR_S1_S_MACRO__

/* macros for field SHADOW */
#define MAC_DMA_ISR_S1_S__SHADOW__SHIFT                                       0
#define MAC_DMA_ISR_S1_S__SHADOW__WIDTH                                      32
#define MAC_DMA_ISR_S1_S__SHADOW__MASK                              0xffffffffU
#define MAC_DMA_ISR_S1_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S1_S__TYPE                                        u_int32_t
#define MAC_DMA_ISR_S1_S__READ                                      0xffffffffU

#endif /* __MAC_DMA_ISR_S1_S_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S1_S */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1_S__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2_S */
#ifndef __MAC_DMA_ISR_S2_S_MACRO__
#define __MAC_DMA_ISR_S2_S_MACRO__

/* macros for field SHADOW */
#define MAC_DMA_ISR_S2_S__SHADOW__SHIFT                                       0
#define MAC_DMA_ISR_S2_S__SHADOW__WIDTH                                      32
#define MAC_DMA_ISR_S2_S__SHADOW__MASK                              0xffffffffU
#define MAC_DMA_ISR_S2_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S2_S__TYPE                                        u_int32_t
#define MAC_DMA_ISR_S2_S__READ                                      0xffffffffU

#endif /* __MAC_DMA_ISR_S2_S_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S2_S */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2_S__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3_S */
#ifndef __MAC_DMA_ISR_S3_S_MACRO__
#define __MAC_DMA_ISR_S3_S_MACRO__

/* macros for field SHADOW */
#define MAC_DMA_ISR_S3_S__SHADOW__SHIFT                                       0
#define MAC_DMA_ISR_S3_S__SHADOW__WIDTH                                      32
#define MAC_DMA_ISR_S3_S__SHADOW__MASK                              0xffffffffU
#define MAC_DMA_ISR_S3_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S3_S__TYPE                                        u_int32_t
#define MAC_DMA_ISR_S3_S__READ                                      0xffffffffU

#endif /* __MAC_DMA_ISR_S3_S_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S3_S */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3_S__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4_S */
#ifndef __MAC_DMA_ISR_S4_S_MACRO__
#define __MAC_DMA_ISR_S4_S_MACRO__

/* macros for field SHADOW */
#define MAC_DMA_ISR_S4_S__SHADOW__SHIFT                                       0
#define MAC_DMA_ISR_S4_S__SHADOW__WIDTH                                      32
#define MAC_DMA_ISR_S4_S__SHADOW__MASK                              0xffffffffU
#define MAC_DMA_ISR_S4_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S4_S__TYPE                                        u_int32_t
#define MAC_DMA_ISR_S4_S__READ                                      0xffffffffU

#endif /* __MAC_DMA_ISR_S4_S_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S4_S */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4_S__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5_S */
#ifndef __MAC_DMA_ISR_S5_S_MACRO__
#define __MAC_DMA_ISR_S5_S_MACRO__

/* macros for field SHADOW */
#define MAC_DMA_ISR_S5_S__SHADOW__SHIFT                                       0
#define MAC_DMA_ISR_S5_S__SHADOW__WIDTH                                      32
#define MAC_DMA_ISR_S5_S__SHADOW__MASK                              0xffffffffU
#define MAC_DMA_ISR_S5_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_ISR_S5_S__TYPE                                        u_int32_t
#define MAC_DMA_ISR_S5_S__READ                                      0xffffffffU

#endif /* __MAC_DMA_ISR_S5_S_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_ISR_S5_S */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5_S__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_0 */
#ifndef __MAC_DMA_DMADBG_0_MACRO__
#define __MAC_DMA_DMADBG_0_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_0__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_0__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_0__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_0__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_0__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_0__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_0_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_0 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_0__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_1 */
#ifndef __MAC_DMA_DMADBG_1_MACRO__
#define __MAC_DMA_DMADBG_1_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_1__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_1__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_1__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_1__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_1__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_1__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_1_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_1 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_1__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_2 */
#ifndef __MAC_DMA_DMADBG_2_MACRO__
#define __MAC_DMA_DMADBG_2_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_2__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_2__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_2__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_2__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_2__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_2__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_2_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_2 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_2__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_3 */
#ifndef __MAC_DMA_DMADBG_3_MACRO__
#define __MAC_DMA_DMADBG_3_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_3__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_3__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_3__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_3__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_3__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_3__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_3_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_3 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_3__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_4 */
#ifndef __MAC_DMA_DMADBG_4_MACRO__
#define __MAC_DMA_DMADBG_4_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_4__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_4__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_4__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_4__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_4__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_4__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_4_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_4 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_4__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_5 */
#ifndef __MAC_DMA_DMADBG_5_MACRO__
#define __MAC_DMA_DMADBG_5_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_5__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_5__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_5__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_5__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_5__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_5__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_5_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_5 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_5__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_6 */
#ifndef __MAC_DMA_DMADBG_6_MACRO__
#define __MAC_DMA_DMADBG_6_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_6__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_6__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_6__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_6__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_6__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_6__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_6_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_6 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_6__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_7 */
#ifndef __MAC_DMA_DMADBG_7_MACRO__
#define __MAC_DMA_DMADBG_7_MACRO__

/* macros for field DATA */
#define MAC_DMA_DMADBG_7__DATA__SHIFT                                         0
#define MAC_DMA_DMADBG_7__DATA__WIDTH                                        32
#define MAC_DMA_DMADBG_7__DATA__MASK                                0xffffffffU
#define MAC_DMA_DMADBG_7__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_DMA_DMADBG_7__TYPE                                        u_int32_t
#define MAC_DMA_DMADBG_7__READ                                      0xffffffffU

#endif /* __MAC_DMA_DMADBG_7_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_7 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_7__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */
#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__
#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__

/* macros for field DATA */
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__SHIFT                       0
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__WIDTH                      32
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__MASK              0xffffffffU
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__TYPE                      u_int32_t
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__READ                    0xffffffffU

#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__NUM         1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */
#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__
#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__

/* macros for field DATA */
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__SHIFT                       0
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__WIDTH                       8
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__MASK              0x000000ffU
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__TYPE                      u_int32_t
#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__READ                    0x000000ffU

#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__NUM         1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_0 */
#ifndef __MAC_DMA_TIMT_0_MACRO__
#define __MAC_DMA_TIMT_0_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_0__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_0__READ                                        0xffffffffU
#define MAC_DMA_TIMT_0__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_0_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_0 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_0__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_1 */
#ifndef __MAC_DMA_TIMT_1_MACRO__
#define __MAC_DMA_TIMT_1_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_1__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_1__READ                                        0xffffffffU
#define MAC_DMA_TIMT_1__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_1_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_1 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_1__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_2 */
#ifndef __MAC_DMA_TIMT_2_MACRO__
#define __MAC_DMA_TIMT_2_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_2__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_2__READ                                        0xffffffffU
#define MAC_DMA_TIMT_2__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_2_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_2 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_2__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_3 */
#ifndef __MAC_DMA_TIMT_3_MACRO__
#define __MAC_DMA_TIMT_3_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_3__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_3__READ                                        0xffffffffU
#define MAC_DMA_TIMT_3__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_3_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_3 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_3__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_4 */
#ifndef __MAC_DMA_TIMT_4_MACRO__
#define __MAC_DMA_TIMT_4_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_4__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_4__READ                                        0xffffffffU
#define MAC_DMA_TIMT_4__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_4_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_4 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_4__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_5 */
#ifndef __MAC_DMA_TIMT_5_MACRO__
#define __MAC_DMA_TIMT_5_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_5__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_5__READ                                        0xffffffffU
#define MAC_DMA_TIMT_5__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_5_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_5 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_5__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_6 */
#ifndef __MAC_DMA_TIMT_6_MACRO__
#define __MAC_DMA_TIMT_6_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_6__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_6__READ                                        0xffffffffU
#define MAC_DMA_TIMT_6__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_6_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_6 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_6__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_7 */
#ifndef __MAC_DMA_TIMT_7_MACRO__
#define __MAC_DMA_TIMT_7_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_7__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_7__READ                                        0xffffffffU
#define MAC_DMA_TIMT_7__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_7_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_7 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_7__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_8 */
#ifndef __MAC_DMA_TIMT_8_MACRO__
#define __MAC_DMA_TIMT_8_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_8__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_8__READ                                        0xffffffffU
#define MAC_DMA_TIMT_8__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_8_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_8 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_8__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_9 */
#ifndef __MAC_DMA_TIMT_9_MACRO__
#define __MAC_DMA_TIMT_9_MACRO__

/* macros for field TX_LAST_PKT_THRESH */
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__SHIFT                             0
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WIDTH                            16
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field TX_FIRST_PKT_THRESH */
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__SHIFT                           16
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WIDTH                           16
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_DMA_TIMT_9__TYPE                                          u_int32_t
#define MAC_DMA_TIMT_9__READ                                        0xffffffffU
#define MAC_DMA_TIMT_9__WRITE                                       0xffffffffU

#endif /* __MAC_DMA_TIMT_9_MACRO__ */


/* macros for mac_dma_reg_map.MAC_DMA_TIMT_9 */
#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_9__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXDP */
#ifndef __MAC_QCU_TXDP_MACRO__
#define __MAC_QCU_TXDP_MACRO__

/* macros for field DATA */
#define MAC_QCU_TXDP__DATA__SHIFT                                             0
#define MAC_QCU_TXDP__DATA__WIDTH                                            32
#define MAC_QCU_TXDP__DATA__MASK                                    0xffffffffU
#define MAC_QCU_TXDP__DATA__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define MAC_QCU_TXDP__DATA__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_QCU_TXDP__DATA__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define MAC_QCU_TXDP__TYPE                                            u_int32_t
#define MAC_QCU_TXDP__READ                                          0xffffffffU
#define MAC_QCU_TXDP__WRITE                                         0xffffffffU

#endif /* __MAC_QCU_TXDP_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_TXDP */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXDP__NUM                              10

/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_START */
#ifndef __MAC_QCU_STATUS_RING_START_MACRO__
#define __MAC_QCU_STATUS_RING_START_MACRO__

/* macros for field ADDR */
#define MAC_QCU_STATUS_RING_START__ADDR__SHIFT                                0
#define MAC_QCU_STATUS_RING_START__ADDR__WIDTH                               32
#define MAC_QCU_STATUS_RING_START__ADDR__MASK                       0xffffffffU
#define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_QCU_STATUS_RING_START__TYPE                               u_int32_t
#define MAC_QCU_STATUS_RING_START__READ                             0xffffffffU
#define MAC_QCU_STATUS_RING_START__WRITE                            0xffffffffU

#endif /* __MAC_QCU_STATUS_RING_START_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_START */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_START__NUM                  1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_END */
#ifndef __MAC_QCU_STATUS_RING_END_MACRO__
#define __MAC_QCU_STATUS_RING_END_MACRO__

/* macros for field ADDR */
#define MAC_QCU_STATUS_RING_END__ADDR__SHIFT                                  0
#define MAC_QCU_STATUS_RING_END__ADDR__WIDTH                                 32
#define MAC_QCU_STATUS_RING_END__ADDR__MASK                         0xffffffffU
#define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU
#define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_QCU_STATUS_RING_END__TYPE                                 u_int32_t
#define MAC_QCU_STATUS_RING_END__READ                               0xffffffffU
#define MAC_QCU_STATUS_RING_END__WRITE                              0xffffffffU

#endif /* __MAC_QCU_STATUS_RING_END_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_END */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_END__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_CURRENT */
#ifndef __MAC_QCU_STATUS_RING_CURRENT_MACRO__
#define __MAC_QCU_STATUS_RING_CURRENT_MACRO__

/* macros for field ADDRESS */
#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__SHIFT                           0
#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__WIDTH                          32
#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__MASK                  0xffffffffU
#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_QCU_STATUS_RING_CURRENT__TYPE                             u_int32_t
#define MAC_QCU_STATUS_RING_CURRENT__READ                           0xffffffffU

#endif /* __MAC_QCU_STATUS_RING_CURRENT_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_CURRENT */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_CURRENT__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXE */
#ifndef __MAC_QCU_TXE_MACRO__
#define __MAC_QCU_TXE_MACRO__

/* macros for field DATA */
#define MAC_QCU_TXE__DATA__SHIFT                                              0
#define MAC_QCU_TXE__DATA__WIDTH                                             10
#define MAC_QCU_TXE__DATA__MASK                                     0x000003ffU
#define MAC_QCU_TXE__DATA__READ(src)             (u_int32_t)(src) & 0x000003ffU
#define MAC_QCU_TXE__TYPE                                             u_int32_t
#define MAC_QCU_TXE__READ                                           0x000003ffU

#endif /* __MAC_QCU_TXE_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_TXE */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXE__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXD */
#ifndef __MAC_QCU_TXD_MACRO__
#define __MAC_QCU_TXD_MACRO__

/* macros for field DATA */
#define MAC_QCU_TXD__DATA__SHIFT                                              0
#define MAC_QCU_TXD__DATA__WIDTH                                             10
#define MAC_QCU_TXD__DATA__MASK                                     0x000003ffU
#define MAC_QCU_TXD__DATA__READ(src)             (u_int32_t)(src) & 0x000003ffU
#define MAC_QCU_TXD__DATA__WRITE(src)          ((u_int32_t)(src) & 0x000003ffU)
#define MAC_QCU_TXD__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_QCU_TXD__DATA__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000003ffU)))

/* macros for field SPARE */
#define MAC_QCU_TXD__SPARE__SHIFT                                            10
#define MAC_QCU_TXD__SPARE__WIDTH                                             4
#define MAC_QCU_TXD__SPARE__MASK                                    0x00003c00U
#define MAC_QCU_TXD__SPARE__READ(src)  (((u_int32_t)(src) & 0x00003c00U) >> 10)
#define MAC_QCU_TXD__SPARE__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U)
#define MAC_QCU_TXD__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00003c00U)
#define MAC_QCU_TXD__SPARE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00003c00U)))
#define MAC_QCU_TXD__TYPE                                             u_int32_t
#define MAC_QCU_TXD__READ                                           0x00003fffU
#define MAC_QCU_TXD__WRITE                                          0x00003fffU

#endif /* __MAC_QCU_TXD_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_TXD */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXD__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_CBR */
#ifndef __MAC_QCU_CBR_MACRO__
#define __MAC_QCU_CBR_MACRO__

/* macros for field INTERVAL */
#define MAC_QCU_CBR__INTERVAL__SHIFT                                          0
#define MAC_QCU_CBR__INTERVAL__WIDTH                                         24
#define MAC_QCU_CBR__INTERVAL__MASK                                 0x00ffffffU
#define MAC_QCU_CBR__INTERVAL__READ(src)         (u_int32_t)(src) & 0x00ffffffU
#define MAC_QCU_CBR__INTERVAL__WRITE(src)      ((u_int32_t)(src) & 0x00ffffffU)
#define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_QCU_CBR__INTERVAL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))

/* macros for field OVF_THRESH */
#define MAC_QCU_CBR__OVF_THRESH__SHIFT                                       24
#define MAC_QCU_CBR__OVF_THRESH__WIDTH                                        8
#define MAC_QCU_CBR__OVF_THRESH__MASK                               0xff000000U
#define MAC_QCU_CBR__OVF_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_QCU_CBR__TYPE                                             u_int32_t
#define MAC_QCU_CBR__READ                                           0xffffffffU
#define MAC_QCU_CBR__WRITE                                          0xffffffffU

#endif /* __MAC_QCU_CBR_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_CBR */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_CBR__NUM                               10

/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME */
#ifndef __MAC_QCU_RDYTIME_MACRO__
#define __MAC_QCU_RDYTIME_MACRO__

/* macros for field DURATION */
#define MAC_QCU_RDYTIME__DURATION__SHIFT                                      0
#define MAC_QCU_RDYTIME__DURATION__WIDTH                                     24
#define MAC_QCU_RDYTIME__DURATION__MASK                             0x00ffffffU
#define MAC_QCU_RDYTIME__DURATION__READ(src)     (u_int32_t)(src) & 0x00ffffffU
#define MAC_QCU_RDYTIME__DURATION__WRITE(src)  ((u_int32_t)(src) & 0x00ffffffU)
#define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))

/* macros for field EN */
#define MAC_QCU_RDYTIME__EN__SHIFT                                           24
#define MAC_QCU_RDYTIME__EN__WIDTH                                            1
#define MAC_QCU_RDYTIME__EN__MASK                                   0x01000000U
#define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
#define MAC_QCU_RDYTIME__EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_QCU_RDYTIME__EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_QCU_RDYTIME__EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_QCU_RDYTIME__EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define MAC_QCU_RDYTIME__TYPE                                         u_int32_t
#define MAC_QCU_RDYTIME__READ                                       0x01ffffffU
#define MAC_QCU_RDYTIME__WRITE                                      0x01ffffffU

#endif /* __MAC_QCU_RDYTIME_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME__NUM                           10

/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_SC */
#ifndef __MAC_QCU_ONESHOT_ARM_SC_MACRO__
#define __MAC_QCU_ONESHOT_ARM_SC_MACRO__

/* macros for field SET */
#define MAC_QCU_ONESHOT_ARM_SC__SET__SHIFT                                    0
#define MAC_QCU_ONESHOT_ARM_SC__SET__WIDTH                                   10
#define MAC_QCU_ONESHOT_ARM_SC__SET__MASK                           0x000003ffU
#define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src)   (u_int32_t)(src) & 0x000003ffU
#define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define MAC_QCU_ONESHOT_ARM_SC__TYPE                                  u_int32_t
#define MAC_QCU_ONESHOT_ARM_SC__READ                                0x000003ffU
#define MAC_QCU_ONESHOT_ARM_SC__WRITE                               0x000003ffU

#endif /* __MAC_QCU_ONESHOT_ARM_SC_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_SC */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_SC__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_CC */
#ifndef __MAC_QCU_ONESHOT_ARM_CC_MACRO__
#define __MAC_QCU_ONESHOT_ARM_CC_MACRO__

/* macros for field CLEAR */
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__SHIFT                                  0
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WIDTH                                 10
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MASK                         0x000003ffU
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define MAC_QCU_ONESHOT_ARM_CC__TYPE                                  u_int32_t
#define MAC_QCU_ONESHOT_ARM_CC__READ                                0x000003ffU
#define MAC_QCU_ONESHOT_ARM_CC__WRITE                               0x000003ffU

#endif /* __MAC_QCU_ONESHOT_ARM_CC_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_CC */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_CC__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_MISC */
#ifndef __MAC_QCU_MISC_MACRO__
#define __MAC_QCU_MISC_MACRO__

/* macros for field FSP */
#define MAC_QCU_MISC__FSP__SHIFT                                              0
#define MAC_QCU_MISC__FSP__WIDTH                                              4
#define MAC_QCU_MISC__FSP__MASK                                     0x0000000fU
#define MAC_QCU_MISC__FSP__READ(src)             (u_int32_t)(src) & 0x0000000fU
#define MAC_QCU_MISC__FSP__WRITE(src)          ((u_int32_t)(src) & 0x0000000fU)
#define MAC_QCU_MISC__FSP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_QCU_MISC__FSP__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000000fU)))

/* macros for field ONESHOT_EN */
#define MAC_QCU_MISC__ONESHOT_EN__SHIFT                                       4
#define MAC_QCU_MISC__ONESHOT_EN__WIDTH                                       1
#define MAC_QCU_MISC__ONESHOT_EN__MASK                              0x00000010U
#define MAC_QCU_MISC__ONESHOT_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_QCU_MISC__ONESHOT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_QCU_MISC__ONESHOT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field CBR_EXP_INC_DIS_NOFR */
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SHIFT                             5
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WIDTH                             1
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MASK                    0x00000020U
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field CBR_EXP_INC_DIS_NOBCNFR */
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SHIFT                          6
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WIDTH                          1
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MASK                 0x00000040U
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field IS_BCN */
#define MAC_QCU_MISC__IS_BCN__SHIFT                                           7
#define MAC_QCU_MISC__IS_BCN__WIDTH                                           1
#define MAC_QCU_MISC__IS_BCN__MASK                                  0x00000080U
#define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
#define MAC_QCU_MISC__IS_BCN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_QCU_MISC__IS_BCN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_QCU_MISC__IS_BCN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_QCU_MISC__IS_BCN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field CBR_EXP_INC_LIMIT */
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SHIFT                                8
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WIDTH                                1
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MASK                       0x00000100U
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field TXE_CLR_ON_CBR_END */
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SHIFT                               9
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WIDTH                               1
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MASK                      0x00000200U
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field MMR_CBR_EXP_CNT_CLR_EN */
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SHIFT                          10
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WIDTH                           1
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MASK                  0x00000400U
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field FR_ABORT_REQ_EN */
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SHIFT                                 11
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WIDTH                                  1
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MASK                         0x00000800U
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_QCU_MISC__FR_ABORT_REQ_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)
#define MAC_QCU_MISC__TYPE                                            u_int32_t
#define MAC_QCU_MISC__READ                                          0x00000fffU
#define MAC_QCU_MISC__WRITE                                         0x00000fffU

#endif /* __MAC_QCU_MISC_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_MISC */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_MISC__NUM                              10

/* macros for BlueprintGlobalNameSpace::MAC_QCU_CNT */
#ifndef __MAC_QCU_CNT_MACRO__
#define __MAC_QCU_CNT_MACRO__

/* macros for field FR_PEND */
#define MAC_QCU_CNT__FR_PEND__SHIFT                                           0
#define MAC_QCU_CNT__FR_PEND__WIDTH                                           2
#define MAC_QCU_CNT__FR_PEND__MASK                                  0x00000003U
#define MAC_QCU_CNT__FR_PEND__READ(src)          (u_int32_t)(src) & 0x00000003U

/* macros for field CBR_EXP */
#define MAC_QCU_CNT__CBR_EXP__SHIFT                                           8
#define MAC_QCU_CNT__CBR_EXP__WIDTH                                           8
#define MAC_QCU_CNT__CBR_EXP__MASK                                  0x0000ff00U
#define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define MAC_QCU_CNT__TYPE                                             u_int32_t
#define MAC_QCU_CNT__READ                                           0x0000ff03U

#endif /* __MAC_QCU_CNT_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_CNT */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_CNT__NUM                               10

/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME_SHDN */
#ifndef __MAC_QCU_RDYTIME_SHDN_MACRO__
#define __MAC_QCU_RDYTIME_SHDN_MACRO__

/* macros for field SHUTDOWN */
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__SHIFT                                 0
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WIDTH                                10
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MASK                        0x000003ffU
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define MAC_QCU_RDYTIME_SHDN__TYPE                                    u_int32_t
#define MAC_QCU_RDYTIME_SHDN__READ                                  0x000003ffU
#define MAC_QCU_RDYTIME_SHDN__WRITE                                 0x000003ffU
#define MAC_QCU_RDYTIME_SHDN__WOCLR                                 0x000003ffU

#endif /* __MAC_QCU_RDYTIME_SHDN_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME_SHDN */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME_SHDN__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_QCU_DESC_CRC_CHK */
#ifndef __MAC_QCU_DESC_CRC_CHK_MACRO__
#define __MAC_QCU_DESC_CRC_CHK_MACRO__

/* macros for field EN */
#define MAC_QCU_DESC_CRC_CHK__EN__SHIFT                                       0
#define MAC_QCU_DESC_CRC_CHK__EN__WIDTH                                       1
#define MAC_QCU_DESC_CRC_CHK__EN__MASK                              0x00000001U
#define MAC_QCU_DESC_CRC_CHK__EN__READ(src)      (u_int32_t)(src) & 0x00000001U
#define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
#define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_QCU_DESC_CRC_CHK__EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_QCU_DESC_CRC_CHK__EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define MAC_QCU_DESC_CRC_CHK__TYPE                                    u_int32_t
#define MAC_QCU_DESC_CRC_CHK__READ                                  0x00000001U
#define MAC_QCU_DESC_CRC_CHK__WRITE                                 0x00000001U

#endif /* __MAC_QCU_DESC_CRC_CHK_MACRO__ */


/* macros for mac_qcu_reg_map.MAC_QCU_DESC_CRC_CHK */
#define INST_MAC_QCU_REG_MAP__MAC_QCU_DESC_CRC_CHK__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_QCUMASK */
#ifndef __MAC_DCU_QCUMASK_MACRO__
#define __MAC_DCU_QCUMASK_MACRO__

/* macros for field DATA */
#define MAC_DCU_QCUMASK__DATA__SHIFT                                          0
#define MAC_DCU_QCUMASK__DATA__WIDTH                                         10
#define MAC_DCU_QCUMASK__DATA__MASK                                 0x000003ffU
#define MAC_DCU_QCUMASK__DATA__READ(src)         (u_int32_t)(src) & 0x000003ffU
#define MAC_DCU_QCUMASK__DATA__WRITE(src)      ((u_int32_t)(src) & 0x000003ffU)
#define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_DCU_QCUMASK__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define MAC_DCU_QCUMASK__TYPE                                         u_int32_t
#define MAC_DCU_QCUMASK__READ                                       0x000003ffU
#define MAC_DCU_QCUMASK__WRITE                                      0x000003ffU

#endif /* __MAC_DCU_QCUMASK_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_QCUMASK */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_QCUMASK__NUM                           10

/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SIFS */
#ifndef __MAC_DCU_GBL_IFS_SIFS_MACRO__
#define __MAC_DCU_GBL_IFS_SIFS_MACRO__

/* macros for field DURATION */
#define MAC_DCU_GBL_IFS_SIFS__DURATION__SHIFT                                 0
#define MAC_DCU_GBL_IFS_SIFS__DURATION__WIDTH                                16
#define MAC_DCU_GBL_IFS_SIFS__DURATION__MASK                        0x0000ffffU
#define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_DCU_GBL_IFS_SIFS__TYPE                                    u_int32_t
#define MAC_DCU_GBL_IFS_SIFS__READ                                  0x0000ffffU
#define MAC_DCU_GBL_IFS_SIFS__WRITE                                 0x0000ffffU

#endif /* __MAC_DCU_GBL_IFS_SIFS_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SIFS */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SIFS__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DCU_TXFILTER_DCU0_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU0_31_0__READ                            0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_31_0__WRITE                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU8_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_LCL_IFS */
#ifndef __MAC_DCU_LCL_IFS_MACRO__
#define __MAC_DCU_LCL_IFS_MACRO__

/* macros for field CW_MIN */
#define MAC_DCU_LCL_IFS__CW_MIN__SHIFT                                        0
#define MAC_DCU_LCL_IFS__CW_MIN__WIDTH                                       10
#define MAC_DCU_LCL_IFS__CW_MIN__MASK                               0x000003ffU
#define MAC_DCU_LCL_IFS__CW_MIN__READ(src)       (u_int32_t)(src) & 0x000003ffU
#define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src)    ((u_int32_t)(src) & 0x000003ffU)
#define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field CW_MAX */
#define MAC_DCU_LCL_IFS__CW_MAX__SHIFT                                       10
#define MAC_DCU_LCL_IFS__CW_MAX__WIDTH                                       10
#define MAC_DCU_LCL_IFS__CW_MAX__MASK                               0x000ffc00U
#define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field AIFS */
#define MAC_DCU_LCL_IFS__AIFS__SHIFT                                         20
#define MAC_DCU_LCL_IFS__AIFS__WIDTH                                          8
#define MAC_DCU_LCL_IFS__AIFS__MASK                                 0x0ff00000U
#define MAC_DCU_LCL_IFS__AIFS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0ff00000U) >> 20)
#define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x0ff00000U)
#define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0ff00000U) | (((u_int32_t)(src) <<\
                    20) & 0x0ff00000U)
#define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x0ff00000U)))

/* macros for field LONG_AIFS */
#define MAC_DCU_LCL_IFS__LONG_AIFS__SHIFT                                    28
#define MAC_DCU_LCL_IFS__LONG_AIFS__WIDTH                                     1
#define MAC_DCU_LCL_IFS__LONG_AIFS__MASK                            0x10000000U
#define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_DCU_LCL_IFS__LONG_AIFS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_DCU_LCL_IFS__LONG_AIFS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)
#define MAC_DCU_LCL_IFS__TYPE                                         u_int32_t
#define MAC_DCU_LCL_IFS__READ                                       0x1fffffffU
#define MAC_DCU_LCL_IFS__WRITE                                      0x1fffffffU

#endif /* __MAC_DCU_LCL_IFS_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_LCL_IFS */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_LCL_IFS__NUM                           10

/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SLOT */
#ifndef __MAC_DCU_GBL_IFS_SLOT_MACRO__
#define __MAC_DCU_GBL_IFS_SLOT_MACRO__

/* macros for field DURATION */
#define MAC_DCU_GBL_IFS_SLOT__DURATION__SHIFT                                 0
#define MAC_DCU_GBL_IFS_SLOT__DURATION__WIDTH                                16
#define MAC_DCU_GBL_IFS_SLOT__DURATION__MASK                        0x0000ffffU
#define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_DCU_GBL_IFS_SLOT__TYPE                                    u_int32_t
#define MAC_DCU_GBL_IFS_SLOT__READ                                  0x0000ffffU
#define MAC_DCU_GBL_IFS_SLOT__WRITE                                 0x0000ffffU

#endif /* __MAC_DCU_GBL_IFS_SLOT_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SLOT */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SLOT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DCU_TXFILTER_DCU0_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU0_63_32__READ                           0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_63_32__WRITE                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU8_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_RETRY_LIMIT */
#ifndef __MAC_DCU_RETRY_LIMIT_MACRO__
#define __MAC_DCU_RETRY_LIMIT_MACRO__

/* macros for field FRFL */
#define MAC_DCU_RETRY_LIMIT__FRFL__SHIFT                                      0
#define MAC_DCU_RETRY_LIMIT__FRFL__WIDTH                                      4
#define MAC_DCU_RETRY_LIMIT__FRFL__MASK                             0x0000000fU
#define MAC_DCU_RETRY_LIMIT__FRFL__READ(src)     (u_int32_t)(src) & 0x0000000fU
#define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src)  ((u_int32_t)(src) & 0x0000000fU)
#define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field SRFL */
#define MAC_DCU_RETRY_LIMIT__SRFL__SHIFT                                      8
#define MAC_DCU_RETRY_LIMIT__SRFL__WIDTH                                      6
#define MAC_DCU_RETRY_LIMIT__SRFL__MASK                             0x00003f00U
#define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field SDFL */
#define MAC_DCU_RETRY_LIMIT__SDFL__SHIFT                                     14
#define MAC_DCU_RETRY_LIMIT__SDFL__WIDTH                                      6
#define MAC_DCU_RETRY_LIMIT__SDFL__MASK                             0x000fc000U
#define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fc000U) >> 14)
#define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x000fc000U)
#define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x000fc000U)
#define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x000fc000U)))
#define MAC_DCU_RETRY_LIMIT__TYPE                                     u_int32_t
#define MAC_DCU_RETRY_LIMIT__READ                                   0x000fff0fU
#define MAC_DCU_RETRY_LIMIT__WRITE                                  0x000fff0fU

#endif /* __MAC_DCU_RETRY_LIMIT_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_RETRY_LIMIT */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_RETRY_LIMIT__NUM                       10

/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_EIFS */
#ifndef __MAC_DCU_GBL_IFS_EIFS_MACRO__
#define __MAC_DCU_GBL_IFS_EIFS_MACRO__

/* macros for field DURATION */
#define MAC_DCU_GBL_IFS_EIFS__DURATION__SHIFT                                 0
#define MAC_DCU_GBL_IFS_EIFS__DURATION__WIDTH                                16
#define MAC_DCU_GBL_IFS_EIFS__DURATION__MASK                        0x0000ffffU
#define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_DCU_GBL_IFS_EIFS__TYPE                                    u_int32_t
#define MAC_DCU_GBL_IFS_EIFS__READ                                  0x0000ffffU
#define MAC_DCU_GBL_IFS_EIFS__WRITE                                 0x0000ffffU

#endif /* __MAC_DCU_GBL_IFS_EIFS_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_EIFS */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_EIFS__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DCU_TXFILTER_DCU0_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU0_95_64__READ                           0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_95_64__WRITE                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU8_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_CHANNEL_TIME */
#ifndef __MAC_DCU_CHANNEL_TIME_MACRO__
#define __MAC_DCU_CHANNEL_TIME_MACRO__

/* macros for field DURATION */
#define MAC_DCU_CHANNEL_TIME__DURATION__SHIFT                                 0
#define MAC_DCU_CHANNEL_TIME__DURATION__WIDTH                                20
#define MAC_DCU_CHANNEL_TIME__DURATION__MASK                        0x000fffffU
#define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000fffffU
#define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000fffffU)
#define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fffffU) | ((u_int32_t)(src) &\
                    0x000fffffU)
#define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000fffffU)))

/* macros for field ENABLE */
#define MAC_DCU_CHANNEL_TIME__ENABLE__SHIFT                                  20
#define MAC_DCU_CHANNEL_TIME__ENABLE__WIDTH                                   1
#define MAC_DCU_CHANNEL_TIME__ENABLE__MASK                          0x00100000U
#define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_DCU_CHANNEL_TIME__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_DCU_CHANNEL_TIME__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)
#define MAC_DCU_CHANNEL_TIME__TYPE                                    u_int32_t
#define MAC_DCU_CHANNEL_TIME__READ                                  0x001fffffU
#define MAC_DCU_CHANNEL_TIME__WRITE                                 0x001fffffU

#endif /* __MAC_DCU_CHANNEL_TIME_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_CHANNEL_TIME */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_CHANNEL_TIME__NUM                      10

/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_MISC */
#ifndef __MAC_DCU_GBL_IFS_MISC_MACRO__
#define __MAC_DCU_GBL_IFS_MISC_MACRO__

/* macros for field LFSR_SLICE_SEL */
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__SHIFT                           0
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WIDTH                           3
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MASK                  0x00000007U
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field TURBO_MODE */
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SHIFT                               3
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WIDTH                               1
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MASK                      0x00000008U
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field SIFS_DUR_USEC */
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__SHIFT                            4
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WIDTH                            6
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MASK                   0x000003f0U
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field ARB_DLY */
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__SHIFT                                 20
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WIDTH                                  2
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MASK                         0x00300000U
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00300000U) >> 20)
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00300000U)
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00300000U) | (((u_int32_t)(src) <<\
                    20) & 0x00300000U)
#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00300000U)))

/* macros for field SIFS_RST_UNCOND */
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SHIFT                         22
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WIDTH                          1
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MASK                 0x00400000U
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field AIFS_RST_UNCOND */
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SHIFT                         23
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WIDTH                          1
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MASK                 0x00800000U
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field LFSR_SLICE_RANDOM_DIS */
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SHIFT                   24
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WIDTH                    1
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MASK           0x01000000U
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field CHAN_SLOT_WIN_DUR */
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__SHIFT                       25
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WIDTH                        2
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MASK               0x06000000U
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x06000000U) >> 25)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x06000000U)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x06000000U) | (((u_int32_t)(src) <<\
                    25) & 0x06000000U)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x06000000U)))

/* macros for field CHAN_SLOT_ALWAYS */
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SHIFT                        27
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WIDTH                         1
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MASK                0x08000000U
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field IGNORE_BACKOFF */
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SHIFT                          28
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WIDTH                           1
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MASK                  0x10000000U
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field SLOT_COUNT_RST_UNCOND */
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SHIFT                   29
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WIDTH                    1
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MASK           0x20000000U
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define MAC_DCU_GBL_IFS_MISC__TYPE                                    u_int32_t
#define MAC_DCU_GBL_IFS_MISC__READ                                  0x3ff003ffU
#define MAC_DCU_GBL_IFS_MISC__WRITE                                 0x3ff003ffU

#endif /* __MAC_DCU_GBL_IFS_MISC_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_MISC */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_MISC__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DCU_TXFILTER_DCU0_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU0_127_96__READ                          0xffffffffU
#define MAC_DCU_TXFILTER_DCU0_127_96__WRITE                         0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU8_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU8_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_MISC */
#ifndef __MAC_DCU_MISC_MACRO__
#define __MAC_DCU_MISC_MACRO__

/* macros for field BKOFF_THRESH */
#define MAC_DCU_MISC__BKOFF_THRESH__SHIFT                                     0
#define MAC_DCU_MISC__BKOFF_THRESH__WIDTH                                     6
#define MAC_DCU_MISC__BKOFF_THRESH__MASK                            0x0000003fU
#define MAC_DCU_MISC__BKOFF_THRESH__READ(src)    (u_int32_t)(src) & 0x0000003fU
#define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
#define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field SFC_RST_AT_TS_END_EN */
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SHIFT                             6
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WIDTH                             1
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MASK                    0x00000040U
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field CW_RST_AT_TS_END_DIS */
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SHIFT                             7
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WIDTH                             1
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MASK                    0x00000080U
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field FRAG_BURST_WAIT_QCU_EN */
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SHIFT                           8
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WIDTH                           1
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MASK                  0x00000100U
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field FRAG_BURST_BKOFF_EN */
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SHIFT                              9
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WIDTH                              1
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MASK                     0x00000200U
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field HCF_POLL_EN */
#define MAC_DCU_MISC__HCF_POLL_EN__SHIFT                                     11
#define MAC_DCU_MISC__HCF_POLL_EN__WIDTH                                      1
#define MAC_DCU_MISC__HCF_POLL_EN__MASK                             0x00000800U
#define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_DCU_MISC__HCF_POLL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_DCU_MISC__HCF_POLL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field BKOFF_PF */
#define MAC_DCU_MISC__BKOFF_PF__SHIFT                                        12
#define MAC_DCU_MISC__BKOFF_PF__WIDTH                                         1
#define MAC_DCU_MISC__BKOFF_PF__MASK                                0x00001000U
#define MAC_DCU_MISC__BKOFF_PF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_DCU_MISC__BKOFF_PF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_DCU_MISC__BKOFF_PF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field VIRT_COLL_POLICY */
#define MAC_DCU_MISC__VIRT_COLL_POLICY__SHIFT                                14
#define MAC_DCU_MISC__VIRT_COLL_POLICY__WIDTH                                 2
#define MAC_DCU_MISC__VIRT_COLL_POLICY__MASK                        0x0000c000U
#define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000c000U) >> 14)
#define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0000c000U)
#define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0000c000U)
#define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field IS_BCN */
#define MAC_DCU_MISC__IS_BCN__SHIFT                                          16
#define MAC_DCU_MISC__IS_BCN__WIDTH                                           1
#define MAC_DCU_MISC__IS_BCN__MASK                                  0x00010000U
#define MAC_DCU_MISC__IS_BCN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_DCU_MISC__IS_BCN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_DCU_MISC__IS_BCN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_DCU_MISC__IS_BCN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_DCU_MISC__IS_BCN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field ARB_LOCKOUT_IF_EN */
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SHIFT                               17
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WIDTH                                1
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MASK                       0x00020000U
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field LOCKOUT_GBL_EN */
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SHIFT                                  18
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WIDTH                                   1
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MASK                          0x00040000U
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_DCU_MISC__LOCKOUT_GBL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field LOCKOUT_IGNORE */
#define MAC_DCU_MISC__LOCKOUT_IGNORE__SHIFT                                  19
#define MAC_DCU_MISC__LOCKOUT_IGNORE__WIDTH                                   1
#define MAC_DCU_MISC__LOCKOUT_IGNORE__MASK                          0x00080000U
#define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_DCU_MISC__LOCKOUT_IGNORE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_DCU_MISC__LOCKOUT_IGNORE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field SEQNUM_FREEZE */
#define MAC_DCU_MISC__SEQNUM_FREEZE__SHIFT                                   20
#define MAC_DCU_MISC__SEQNUM_FREEZE__WIDTH                                    1
#define MAC_DCU_MISC__SEQNUM_FREEZE__MASK                           0x00100000U
#define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_DCU_MISC__SEQNUM_FREEZE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_DCU_MISC__SEQNUM_FREEZE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field POST_BKOFF_SKIP */
#define MAC_DCU_MISC__POST_BKOFF_SKIP__SHIFT                                 21
#define MAC_DCU_MISC__POST_BKOFF_SKIP__WIDTH                                  1
#define MAC_DCU_MISC__POST_BKOFF_SKIP__MASK                         0x00200000U
#define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_DCU_MISC__POST_BKOFF_SKIP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_DCU_MISC__POST_BKOFF_SKIP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field VIRT_COLL_CW_INC_EN */
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SHIFT                             22
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WIDTH                              1
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MASK                     0x00400000U
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field RETRY_ON_BLOWN_IFS_EN */
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SHIFT                           23
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WIDTH                            1
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MASK                   0x00800000U
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field SIFS_BURST_CHAN_BUSY_IGNORE */
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SHIFT                     24
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WIDTH                      1
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MASK             0x01000000U
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define MAC_DCU_MISC__TYPE                                            u_int32_t
#define MAC_DCU_MISC__READ                                          0x01ffdbffU
#define MAC_DCU_MISC__WRITE                                         0x01ffdbffU

#endif /* __MAC_DCU_MISC_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_MISC */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_MISC__NUM                              10

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU1_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU9_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_SEQ */
#ifndef __MAC_DCU_SEQ_MACRO__
#define __MAC_DCU_SEQ_MACRO__

/* macros for field NUM */
#define MAC_DCU_SEQ__NUM__SHIFT                                               0
#define MAC_DCU_SEQ__NUM__WIDTH                                              32
#define MAC_DCU_SEQ__NUM__MASK                                      0xffffffffU
#define MAC_DCU_SEQ__NUM__READ(src)              (u_int32_t)(src) & 0xffffffffU
#define MAC_DCU_SEQ__NUM__WRITE(src)           ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_SEQ__NUM__VERIFY(src)    (!(((u_int32_t)(src) & ~0xffffffffU)))
#define MAC_DCU_SEQ__TYPE                                             u_int32_t
#define MAC_DCU_SEQ__READ                                           0xffffffffU
#define MAC_DCU_SEQ__WRITE                                          0xffffffffU

#endif /* __MAC_DCU_SEQ_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_SEQ */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_SEQ__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU1_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU9_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU1_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU9_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU1_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU1_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU9_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU9_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU2_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_PAUSE */
#ifndef __MAC_DCU_PAUSE_MACRO__
#define __MAC_DCU_PAUSE_MACRO__

/* macros for field REQUEST */
#define MAC_DCU_PAUSE__REQUEST__SHIFT                                         0
#define MAC_DCU_PAUSE__REQUEST__WIDTH                                        10
#define MAC_DCU_PAUSE__REQUEST__MASK                                0x000003ffU
#define MAC_DCU_PAUSE__REQUEST__READ(src)        (u_int32_t)(src) & 0x000003ffU
#define MAC_DCU_PAUSE__REQUEST__WRITE(src)     ((u_int32_t)(src) & 0x000003ffU)
#define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field STATUS */
#define MAC_DCU_PAUSE__STATUS__SHIFT                                         16
#define MAC_DCU_PAUSE__STATUS__WIDTH                                          1
#define MAC_DCU_PAUSE__STATUS__MASK                                 0x00010000U
#define MAC_DCU_PAUSE__STATUS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_DCU_PAUSE__STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_DCU_PAUSE__STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field SPARE */
#define MAC_DCU_PAUSE__SPARE__SHIFT                                          17
#define MAC_DCU_PAUSE__SPARE__WIDTH                                           4
#define MAC_DCU_PAUSE__SPARE__MASK                                  0x001e0000U
#define MAC_DCU_PAUSE__SPARE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001e0000U) >> 17)
#define MAC_DCU_PAUSE__SPARE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x001e0000U)
#define MAC_DCU_PAUSE__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x001e0000U)
#define MAC_DCU_PAUSE__SPARE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x001e0000U)))
#define MAC_DCU_PAUSE__TYPE                                           u_int32_t
#define MAC_DCU_PAUSE__READ                                         0x001f03ffU
#define MAC_DCU_PAUSE__WRITE                                        0x001f03ffU

#endif /* __MAC_DCU_PAUSE_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_PAUSE */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_PAUSE__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU2_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_WOW_KACFG */
#ifndef __MAC_DCU_WOW_KACFG_MACRO__
#define __MAC_DCU_WOW_KACFG_MACRO__

/* macros for field TX_EN */
#define MAC_DCU_WOW_KACFG__TX_EN__SHIFT                                       0
#define MAC_DCU_WOW_KACFG__TX_EN__WIDTH                                       1
#define MAC_DCU_WOW_KACFG__TX_EN__MASK                              0x00000001U
#define MAC_DCU_WOW_KACFG__TX_EN__READ(src)      (u_int32_t)(src) & 0x00000001U
#define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
#define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_DCU_WOW_KACFG__TX_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_DCU_WOW_KACFG__TX_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field TIM_EN */
#define MAC_DCU_WOW_KACFG__TIM_EN__SHIFT                                      1
#define MAC_DCU_WOW_KACFG__TIM_EN__WIDTH                                      1
#define MAC_DCU_WOW_KACFG__TIM_EN__MASK                             0x00000002U
#define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_DCU_WOW_KACFG__TIM_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_DCU_WOW_KACFG__TIM_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field BCN_CNT */
#define MAC_DCU_WOW_KACFG__BCN_CNT__SHIFT                                     4
#define MAC_DCU_WOW_KACFG__BCN_CNT__WIDTH                                     8
#define MAC_DCU_WOW_KACFG__BCN_CNT__MASK                            0x00000ff0U
#define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000ff0U) >> 4)
#define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000ff0U)
#define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000ff0U) | (((u_int32_t)(src) <<\
                    4) & 0x00000ff0U)
#define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000ff0U)))

/* macros for field RX_TIMEOUT_CNT */
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__SHIFT                             12
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WIDTH                             12
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MASK                     0x00fff000U
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fff000U) >> 12)
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00fff000U)
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fff000U) | (((u_int32_t)(src) <<\
                    12) & 0x00fff000U)
#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00fff000U)))
#define MAC_DCU_WOW_KACFG__TYPE                                       u_int32_t
#define MAC_DCU_WOW_KACFG__READ                                     0x00fffff3U
#define MAC_DCU_WOW_KACFG__WRITE                                    0x00fffff3U

#endif /* __MAC_DCU_WOW_KACFG_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_WOW_KACFG */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_WOW_KACFG__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU2_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXSLOT */
#ifndef __MAC_DCU_TXSLOT_MACRO__
#define __MAC_DCU_TXSLOT_MACRO__

/* macros for field MASK */
#define MAC_DCU_TXSLOT__MASK__SHIFT                                           0
#define MAC_DCU_TXSLOT__MASK__WIDTH                                          16
#define MAC_DCU_TXSLOT__MASK__MASK                                  0x0000ffffU
#define MAC_DCU_TXSLOT__MASK__READ(src)          (u_int32_t)(src) & 0x0000ffffU
#define MAC_DCU_TXSLOT__MASK__WRITE(src)       ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_DCU_TXSLOT__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_DCU_TXSLOT__TYPE                                          u_int32_t
#define MAC_DCU_TXSLOT__READ                                        0x0000ffffU
#define MAC_DCU_TXSLOT__WRITE                                       0x0000ffffU

#endif /* __MAC_DCU_TXSLOT_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXSLOT */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXSLOT__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU2_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU2_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU3_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU3_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU3_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU3_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU3_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU4_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_CLEAR */
#ifndef __MAC_DCU_TXFILTER_CLEAR_MACRO__
#define __MAC_DCU_TXFILTER_CLEAR_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_CLEAR__DATA__SHIFT                                   0
#define MAC_DCU_TXFILTER_CLEAR__DATA__WIDTH                                  32
#define MAC_DCU_TXFILTER_CLEAR__DATA__MASK                          0xffffffffU
#define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src)  (u_int32_t)(src) & 0xffffffffU
#define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DCU_TXFILTER_CLEAR__TYPE                                  u_int32_t
#define MAC_DCU_TXFILTER_CLEAR__READ                                0xffffffffU
#define MAC_DCU_TXFILTER_CLEAR__WRITE                               0xffffffffU

#endif /* __MAC_DCU_TXFILTER_CLEAR_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_CLEAR */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_CLEAR__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU4_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_SET */
#ifndef __MAC_DCU_TXFILTER_SET_MACRO__
#define __MAC_DCU_TXFILTER_SET_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_SET__DATA__SHIFT                                     0
#define MAC_DCU_TXFILTER_SET__DATA__WIDTH                                    32
#define MAC_DCU_TXFILTER_SET__DATA__MASK                            0xffffffffU
#define MAC_DCU_TXFILTER_SET__DATA__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_DCU_TXFILTER_SET__TYPE                                    u_int32_t
#define MAC_DCU_TXFILTER_SET__READ                                  0xffffffffU
#define MAC_DCU_TXFILTER_SET__WRITE                                 0xffffffffU

#endif /* __MAC_DCU_TXFILTER_SET_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_SET */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_SET__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU4_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU4_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU4_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU5_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU5_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU5_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU5_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU5_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU6_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU6_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU6_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU6_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU6_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_31_0 */
#ifndef __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__
#define __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__SHIFT                               0
#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__WIDTH                              32
#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__MASK                      0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_31_0__TYPE                              u_int32_t
#define MAC_DCU_TXFILTER_DCU7_31_0__READ                            0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_31_0 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_31_0__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_63_32 */
#ifndef __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__
#define __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_63_32__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU7_63_32__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_63_32 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_63_32__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_95_64 */
#ifndef __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__
#define __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__SHIFT                              0
#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__WIDTH                             32
#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__MASK                     0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_95_64__TYPE                             u_int32_t
#define MAC_DCU_TXFILTER_DCU7_95_64__READ                           0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_95_64 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_95_64__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_127_96 */
#ifndef __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__
#define __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__

/* macros for field DATA */
#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__SHIFT                             0
#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__WIDTH                            32
#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__MASK                    0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_DCU_TXFILTER_DCU7_127_96__TYPE                            u_int32_t
#define MAC_DCU_TXFILTER_DCU7_127_96__READ                          0xffffffffU

#endif /* __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_127_96 */
#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_127_96__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_STATUS */
#ifndef __MAC_SLEEP_STATUS_MACRO__
#define __MAC_SLEEP_STATUS_MACRO__

/* macros for field DATA */
#define MAC_SLEEP_STATUS__DATA__SHIFT                                         0
#define MAC_SLEEP_STATUS__DATA__WIDTH                                        32
#define MAC_SLEEP_STATUS__DATA__MASK                                0xffffffffU
#define MAC_SLEEP_STATUS__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_SLEEP_STATUS__DATA__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define MAC_SLEEP_STATUS__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_SLEEP_STATUS__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_SLEEP_STATUS__TYPE                                        u_int32_t
#define MAC_SLEEP_STATUS__READ                                      0xffffffffU
#define MAC_SLEEP_STATUS__WRITE                                     0xffffffffU

#endif /* __MAC_SLEEP_STATUS_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_SLEEP_STATUS */
#define INST_MAC_DCU_REG_MAP__MAC_SLEEP_STATUS__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_LED_CONFIG */
#ifndef __MAC_LED_CONFIG_MACRO__
#define __MAC_LED_CONFIG_MACRO__

/* macros for field DATA */
#define MAC_LED_CONFIG__DATA__SHIFT                                           0
#define MAC_LED_CONFIG__DATA__WIDTH                                          32
#define MAC_LED_CONFIG__DATA__MASK                                  0xffffffffU
#define MAC_LED_CONFIG__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
#define MAC_LED_CONFIG__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define MAC_LED_CONFIG__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_LED_CONFIG__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_LED_CONFIG__TYPE                                          u_int32_t
#define MAC_LED_CONFIG__READ                                        0xffffffffU
#define MAC_LED_CONFIG__WRITE                                       0xffffffffU

#endif /* __MAC_LED_CONFIG_MACRO__ */


/* macros for mac_dcu_reg_map.MAC_LED_CONFIG */
#define INST_MAC_DCU_REG_MAP__MAC_LED_CONFIG__NUM                             1

/* macros for BlueprintGlobalNameSpace::RESET_CONTROL */
#ifndef __RESET_CONTROL_MACRO__
#define __RESET_CONTROL_MACRO__

/* macros for field MAC_WARM_RST */
#define RESET_CONTROL__MAC_WARM_RST__SHIFT                                    0
#define RESET_CONTROL__MAC_WARM_RST__WIDTH                                    1
#define RESET_CONTROL__MAC_WARM_RST__MASK                           0x00000001U
#define RESET_CONTROL__MAC_WARM_RST__READ(src)   (u_int32_t)(src) & 0x00000001U
#define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RESET_CONTROL__MAC_WARM_RST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RESET_CONTROL__MAC_WARM_RST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field MAC_COLD_RST */
#define RESET_CONTROL__MAC_COLD_RST__SHIFT                                    1
#define RESET_CONTROL__MAC_COLD_RST__WIDTH                                    1
#define RESET_CONTROL__MAC_COLD_RST__MASK                           0x00000002U
#define RESET_CONTROL__MAC_COLD_RST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RESET_CONTROL__MAC_COLD_RST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RESET_CONTROL__MAC_COLD_RST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field WARM_RST */
#define RESET_CONTROL__WARM_RST__SHIFT                                        2
#define RESET_CONTROL__WARM_RST__WIDTH                                        1
#define RESET_CONTROL__WARM_RST__MASK                               0x00000004U
#define RESET_CONTROL__WARM_RST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define RESET_CONTROL__WARM_RST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RESET_CONTROL__WARM_RST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RESET_CONTROL__WARM_RST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RESET_CONTROL__WARM_RST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field COLD_RST */
#define RESET_CONTROL__COLD_RST__SHIFT                                        3
#define RESET_CONTROL__COLD_RST__WIDTH                                        1
#define RESET_CONTROL__COLD_RST__MASK                               0x00000008U
#define RESET_CONTROL__COLD_RST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RESET_CONTROL__COLD_RST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RESET_CONTROL__COLD_RST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RESET_CONTROL__COLD_RST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RESET_CONTROL__COLD_RST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)
#define RESET_CONTROL__TYPE                                           u_int32_t
#define RESET_CONTROL__READ                                         0x0000000fU
#define RESET_CONTROL__WRITE                                        0x0000000fU

#endif /* __RESET_CONTROL_MACRO__ */


/* macros for rtc_reg_map.RESET_CONTROL */
#define INST_RTC_REG_MAP__RESET_CONTROL__NUM                                  1

/* macros for BlueprintGlobalNameSpace::XTAL_CONTROL */
#ifndef __XTAL_CONTROL_MACRO__
#define __XTAL_CONTROL_MACRO__

/* macros for field TCXO */
#define XTAL_CONTROL__TCXO__SHIFT                                             0
#define XTAL_CONTROL__TCXO__WIDTH                                             1
#define XTAL_CONTROL__TCXO__MASK                                    0x00000001U
#define XTAL_CONTROL__TCXO__READ(src)            (u_int32_t)(src) & 0x00000001U
#define XTAL_CONTROL__TCXO__WRITE(src)         ((u_int32_t)(src) & 0x00000001U)
#define XTAL_CONTROL__TCXO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define XTAL_CONTROL__TCXO__VERIFY(src)  (!(((u_int32_t)(src) & ~0x00000001U)))
#define XTAL_CONTROL__TCXO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define XTAL_CONTROL__TCXO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define XTAL_CONTROL__TYPE                                            u_int32_t
#define XTAL_CONTROL__READ                                          0x00000001U
#define XTAL_CONTROL__WRITE                                         0x00000001U

#endif /* __XTAL_CONTROL_MACRO__ */


/* macros for rtc_reg_map.XTAL_CONTROL */
#define INST_RTC_REG_MAP__XTAL_CONTROL__NUM                                   1

/* macros for BlueprintGlobalNameSpace::REG_CONTROL0 */
#ifndef __REG_CONTROL0_MACRO__
#define __REG_CONTROL0_MACRO__

/* macros for field SWREG_BITS */
#define REG_CONTROL0__SWREG_BITS__SHIFT                                       0
#define REG_CONTROL0__SWREG_BITS__WIDTH                                      32
#define REG_CONTROL0__SWREG_BITS__MASK                              0xffffffffU
#define REG_CONTROL0__SWREG_BITS__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define REG_CONTROL0__SWREG_BITS__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define REG_CONTROL0__SWREG_BITS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define REG_CONTROL0__TYPE                                            u_int32_t
#define REG_CONTROL0__READ                                          0xffffffffU
#define REG_CONTROL0__WRITE                                         0xffffffffU

#endif /* __REG_CONTROL0_MACRO__ */


/* macros for rtc_reg_map.REG_CONTROL0 */
#define INST_RTC_REG_MAP__REG_CONTROL0__NUM                                   1

/* macros for BlueprintGlobalNameSpace::REG_CONTROL1 */
#ifndef __REG_CONTROL1_MACRO__
#define __REG_CONTROL1_MACRO__

/* macros for field SWREG_PROGRAM */
#define REG_CONTROL1__SWREG_PROGRAM__SHIFT                                    0
#define REG_CONTROL1__SWREG_PROGRAM__WIDTH                                    1
#define REG_CONTROL1__SWREG_PROGRAM__MASK                           0x00000001U
#define REG_CONTROL1__SWREG_PROGRAM__READ(src)   (u_int32_t)(src) & 0x00000001U
#define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define REG_CONTROL1__SWREG_PROGRAM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define REG_CONTROL1__SWREG_PROGRAM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field OTPREG_LVL */
#define REG_CONTROL1__OTPREG_LVL__SHIFT                                       1
#define REG_CONTROL1__OTPREG_LVL__WIDTH                                       2
#define REG_CONTROL1__OTPREG_LVL__MASK                              0x00000006U
#define REG_CONTROL1__OTPREG_LVL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000006U) >> 1)
#define REG_CONTROL1__OTPREG_LVL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000006U)
#define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000006U) | (((u_int32_t)(src) <<\
                    1) & 0x00000006U)
#define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000006U)))
#define REG_CONTROL1__TYPE                                            u_int32_t
#define REG_CONTROL1__READ                                          0x00000007U
#define REG_CONTROL1__WRITE                                         0x00000007U

#endif /* __REG_CONTROL1_MACRO__ */


/* macros for rtc_reg_map.REG_CONTROL1 */
#define INST_RTC_REG_MAP__REG_CONTROL1__NUM                                   1

/* macros for BlueprintGlobalNameSpace::QUADRATURE */
#ifndef __QUADRATURE_MACRO__
#define __QUADRATURE_MACRO__

/* macros for field DAC */
#define QUADRATURE__DAC__SHIFT                                                0
#define QUADRATURE__DAC__WIDTH                                                3
#define QUADRATURE__DAC__MASK                                       0x00000007U
#define QUADRATURE__DAC__READ(src)               (u_int32_t)(src) & 0x00000007U
#define QUADRATURE__DAC__WRITE(src)            ((u_int32_t)(src) & 0x00000007U)
#define QUADRATURE__DAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define QUADRATURE__DAC__VERIFY(src)     (!(((u_int32_t)(src) & ~0x00000007U)))

/* macros for field ADC */
#define QUADRATURE__ADC__SHIFT                                                4
#define QUADRATURE__ADC__WIDTH                                                4
#define QUADRATURE__ADC__MASK                                       0x000000f0U
#define QUADRATURE__ADC__READ(src)      (((u_int32_t)(src) & 0x000000f0U) >> 4)
#define QUADRATURE__ADC__WRITE(src)     (((u_int32_t)(src) << 4) & 0x000000f0U)
#define QUADRATURE__ADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define QUADRATURE__ADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))
#define QUADRATURE__TYPE                                              u_int32_t
#define QUADRATURE__READ                                            0x000000f7U
#define QUADRATURE__WRITE                                           0x000000f7U

#endif /* __QUADRATURE_MACRO__ */


/* macros for rtc_reg_map.QUADRATURE */
#define INST_RTC_REG_MAP__QUADRATURE__NUM                                     1

/* macros for BlueprintGlobalNameSpace::PLL_CONTROL */
#ifndef __PLL_CONTROL_MACRO__
#define __PLL_CONTROL_MACRO__

/* macros for field DIV_INT */
#define PLL_CONTROL__DIV_INT__SHIFT                                           0
#define PLL_CONTROL__DIV_INT__WIDTH                                           6
#define PLL_CONTROL__DIV_INT__MASK                                  0x0000003fU
#define PLL_CONTROL__DIV_INT__READ(src)          (u_int32_t)(src) & 0x0000003fU
#define PLL_CONTROL__DIV_INT__WRITE(src)       ((u_int32_t)(src) & 0x0000003fU)
#define PLL_CONTROL__DIV_INT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define PLL_CONTROL__DIV_INT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field DIV_FRAC */
#define PLL_CONTROL__DIV_FRAC__SHIFT                                          6
#define PLL_CONTROL__DIV_FRAC__WIDTH                                         14
#define PLL_CONTROL__DIV_FRAC__MASK                                 0x000fffc0U
#define PLL_CONTROL__DIV_FRAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fffc0U) >> 6)
#define PLL_CONTROL__DIV_FRAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000fffc0U)
#define PLL_CONTROL__DIV_FRAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fffc0U) | (((u_int32_t)(src) <<\
                    6) & 0x000fffc0U)
#define PLL_CONTROL__DIV_FRAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000fffc0U)))

/* macros for field REFDIV */
#define PLL_CONTROL__REFDIV__SHIFT                                           20
#define PLL_CONTROL__REFDIV__WIDTH                                            5
#define PLL_CONTROL__REFDIV__MASK                                   0x01f00000U
#define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x01f00000U) >> 20)
#define PLL_CONTROL__REFDIV__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define PLL_CONTROL__REFDIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define PLL_CONTROL__REFDIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field CLK_SEL */
#define PLL_CONTROL__CLK_SEL__SHIFT                                          25
#define PLL_CONTROL__CLK_SEL__WIDTH                                           2
#define PLL_CONTROL__CLK_SEL__MASK                                  0x06000000U
#define PLL_CONTROL__CLK_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x06000000U) >> 25)
#define PLL_CONTROL__CLK_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x06000000U)
#define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x06000000U) | (((u_int32_t)(src) <<\
                    25) & 0x06000000U)
#define PLL_CONTROL__CLK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x06000000U)))

/* macros for field BYPASS */
#define PLL_CONTROL__BYPASS__SHIFT                                           27
#define PLL_CONTROL__BYPASS__WIDTH                                            1
#define PLL_CONTROL__BYPASS__MASK                                   0x08000000U
#define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
#define PLL_CONTROL__BYPASS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define PLL_CONTROL__BYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define PLL_CONTROL__BYPASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define PLL_CONTROL__BYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define PLL_CONTROL__BYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field UPDATING */
#define PLL_CONTROL__UPDATING__SHIFT                                         28
#define PLL_CONTROL__UPDATING__WIDTH                                          1
#define PLL_CONTROL__UPDATING__MASK                                 0x10000000U
#define PLL_CONTROL__UPDATING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define PLL_CONTROL__UPDATING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define PLL_CONTROL__UPDATING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field NOPWD */
#define PLL_CONTROL__NOPWD__SHIFT                                            29
#define PLL_CONTROL__NOPWD__WIDTH                                             1
#define PLL_CONTROL__NOPWD__MASK                                    0x20000000U
#define PLL_CONTROL__NOPWD__READ(src)  (((u_int32_t)(src) & 0x20000000U) >> 29)
#define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
#define PLL_CONTROL__NOPWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define PLL_CONTROL__NOPWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define PLL_CONTROL__NOPWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define PLL_CONTROL__NOPWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field MAC_OVERRIDE */
#define PLL_CONTROL__MAC_OVERRIDE__SHIFT                                     30
#define PLL_CONTROL__MAC_OVERRIDE__WIDTH                                      1
#define PLL_CONTROL__MAC_OVERRIDE__MASK                             0x40000000U
#define PLL_CONTROL__MAC_OVERRIDE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define PLL_CONTROL__MAC_OVERRIDE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define PLL_CONTROL__MAC_OVERRIDE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)
#define PLL_CONTROL__TYPE                                             u_int32_t
#define PLL_CONTROL__READ                                           0x7fffffffU
#define PLL_CONTROL__WRITE                                          0x7fffffffU

#endif /* __PLL_CONTROL_MACRO__ */


/* macros for rtc_reg_map.PLL_CONTROL */
#define INST_RTC_REG_MAP__PLL_CONTROL__NUM                                    1

/* macros for BlueprintGlobalNameSpace::PLL_SETTLE */
#ifndef __PLL_SETTLE_MACRO__
#define __PLL_SETTLE_MACRO__

/* macros for field TIME */
#define PLL_SETTLE__TIME__SHIFT                                               0
#define PLL_SETTLE__TIME__WIDTH                                              11
#define PLL_SETTLE__TIME__MASK                                      0x000007ffU
#define PLL_SETTLE__TIME__READ(src)              (u_int32_t)(src) & 0x000007ffU
#define PLL_SETTLE__TIME__WRITE(src)           ((u_int32_t)(src) & 0x000007ffU)
#define PLL_SETTLE__TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((u_int32_t)(src) &\
                    0x000007ffU)
#define PLL_SETTLE__TIME__VERIFY(src)    (!(((u_int32_t)(src) & ~0x000007ffU)))
#define PLL_SETTLE__TYPE                                              u_int32_t
#define PLL_SETTLE__READ                                            0x000007ffU
#define PLL_SETTLE__WRITE                                           0x000007ffU

#endif /* __PLL_SETTLE_MACRO__ */


/* macros for rtc_reg_map.PLL_SETTLE */
#define INST_RTC_REG_MAP__PLL_SETTLE__NUM                                     1

/* macros for BlueprintGlobalNameSpace::XTAL_SETTLE */
#ifndef __XTAL_SETTLE_MACRO__
#define __XTAL_SETTLE_MACRO__

/* macros for field TIME */
#define XTAL_SETTLE__TIME__SHIFT                                              0
#define XTAL_SETTLE__TIME__WIDTH                                              7
#define XTAL_SETTLE__TIME__MASK                                     0x0000007fU
#define XTAL_SETTLE__TIME__READ(src)             (u_int32_t)(src) & 0x0000007fU
#define XTAL_SETTLE__TIME__WRITE(src)          ((u_int32_t)(src) & 0x0000007fU)
#define XTAL_SETTLE__TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define XTAL_SETTLE__TIME__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000007fU)))
#define XTAL_SETTLE__TYPE                                             u_int32_t
#define XTAL_SETTLE__READ                                           0x0000007fU
#define XTAL_SETTLE__WRITE                                          0x0000007fU

#endif /* __XTAL_SETTLE_MACRO__ */


/* macros for rtc_reg_map.XTAL_SETTLE */
#define INST_RTC_REG_MAP__XTAL_SETTLE__NUM                                    1

/* macros for BlueprintGlobalNameSpace::CLOCK_OUT */
#ifndef __CLOCK_OUT_MACRO__
#define __CLOCK_OUT_MACRO__

/* macros for field SELECT */
#define CLOCK_OUT__SELECT__SHIFT                                              0
#define CLOCK_OUT__SELECT__WIDTH                                              4
#define CLOCK_OUT__SELECT__MASK                                     0x0000000fU
#define CLOCK_OUT__SELECT__READ(src)             (u_int32_t)(src) & 0x0000000fU
#define CLOCK_OUT__SELECT__WRITE(src)          ((u_int32_t)(src) & 0x0000000fU)
#define CLOCK_OUT__SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define CLOCK_OUT__SELECT__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000000fU)))

/* macros for field DELAY */
#define CLOCK_OUT__DELAY__SHIFT                                               4
#define CLOCK_OUT__DELAY__WIDTH                                               3
#define CLOCK_OUT__DELAY__MASK                                      0x00000070U
#define CLOCK_OUT__DELAY__READ(src)     (((u_int32_t)(src) & 0x00000070U) >> 4)
#define CLOCK_OUT__DELAY__WRITE(src)    (((u_int32_t)(src) << 4) & 0x00000070U)
#define CLOCK_OUT__DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((u_int32_t)(src) <<\
                    4) & 0x00000070U)
#define CLOCK_OUT__DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000070U)))
#define CLOCK_OUT__TYPE                                               u_int32_t
#define CLOCK_OUT__READ                                             0x0000007fU
#define CLOCK_OUT__WRITE                                            0x0000007fU

#endif /* __CLOCK_OUT_MACRO__ */


/* macros for rtc_reg_map.CLOCK_OUT */
#define INST_RTC_REG_MAP__CLOCK_OUT__NUM                                      1

/* macros for BlueprintGlobalNameSpace::BIAS_OVERRIDE */
#ifndef __BIAS_OVERRIDE_MACRO__
#define __BIAS_OVERRIDE_MACRO__

/* macros for field ON */
#define BIAS_OVERRIDE__ON__SHIFT                                              0
#define BIAS_OVERRIDE__ON__WIDTH                                              1
#define BIAS_OVERRIDE__ON__MASK                                     0x00000001U
#define BIAS_OVERRIDE__ON__READ(src)             (u_int32_t)(src) & 0x00000001U
#define BIAS_OVERRIDE__ON__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
#define BIAS_OVERRIDE__ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define BIAS_OVERRIDE__ON__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
#define BIAS_OVERRIDE__ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define BIAS_OVERRIDE__ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define BIAS_OVERRIDE__TYPE                                           u_int32_t
#define BIAS_OVERRIDE__READ                                         0x00000001U
#define BIAS_OVERRIDE__WRITE                                        0x00000001U

#endif /* __BIAS_OVERRIDE_MACRO__ */


/* macros for rtc_reg_map.BIAS_OVERRIDE */
#define INST_RTC_REG_MAP__BIAS_OVERRIDE__NUM                                  1

/* macros for BlueprintGlobalNameSpace::RESET_CAUSE */
#ifndef __RESET_CAUSE_MACRO__
#define __RESET_CAUSE_MACRO__

/* macros for field LAST */
#define RESET_CAUSE__LAST__SHIFT                                              0
#define RESET_CAUSE__LAST__WIDTH                                              2
#define RESET_CAUSE__LAST__MASK                                     0x00000003U
#define RESET_CAUSE__LAST__READ(src)             (u_int32_t)(src) & 0x00000003U
#define RESET_CAUSE__TYPE                                             u_int32_t
#define RESET_CAUSE__READ                                           0x00000003U

#endif /* __RESET_CAUSE_MACRO__ */


/* macros for rtc_reg_map.RESET_CAUSE */
#define INST_RTC_REG_MAP__RESET_CAUSE__NUM                                    1

/* macros for BlueprintGlobalNameSpace::SYSTEM_SLEEP */
#ifndef __SYSTEM_SLEEP_MACRO__
#define __SYSTEM_SLEEP_MACRO__

/* macros for field DISABLE */
#define SYSTEM_SLEEP__DISABLE__SHIFT                                          0
#define SYSTEM_SLEEP__DISABLE__WIDTH                                          1
#define SYSTEM_SLEEP__DISABLE__MASK                                 0x00000001U
#define SYSTEM_SLEEP__DISABLE__READ(src)         (u_int32_t)(src) & 0x00000001U
#define SYSTEM_SLEEP__DISABLE__WRITE(src)      ((u_int32_t)(src) & 0x00000001U)
#define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SYSTEM_SLEEP__DISABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SYSTEM_SLEEP__DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SYSTEM_SLEEP__DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field LIGHT */
#define SYSTEM_SLEEP__LIGHT__SHIFT                                            1
#define SYSTEM_SLEEP__LIGHT__WIDTH                                            1
#define SYSTEM_SLEEP__LIGHT__MASK                                   0x00000002U
#define SYSTEM_SLEEP__LIGHT__READ(src)  (((u_int32_t)(src) & 0x00000002U) >> 1)
#define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
#define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define SYSTEM_SLEEP__LIGHT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define SYSTEM_SLEEP__LIGHT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define SYSTEM_SLEEP__LIGHT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field MAC_IF */
#define SYSTEM_SLEEP__MAC_IF__SHIFT                                           2
#define SYSTEM_SLEEP__MAC_IF__WIDTH                                           1
#define SYSTEM_SLEEP__MAC_IF__MASK                                  0x00000004U
#define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
#define SYSTEM_SLEEP__MAC_IF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define SYSTEM_SLEEP__MAC_IF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)
#define SYSTEM_SLEEP__TYPE                                            u_int32_t
#define SYSTEM_SLEEP__READ                                          0x00000007U
#define SYSTEM_SLEEP__WRITE                                         0x00000007U

#endif /* __SYSTEM_SLEEP_MACRO__ */


/* macros for rtc_reg_map.SYSTEM_SLEEP */
#define INST_RTC_REG_MAP__SYSTEM_SLEEP__NUM                                   1

/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_CONTROL */
#ifndef __MAC_SLEEP_CONTROL_MACRO__
#define __MAC_SLEEP_CONTROL_MACRO__

/* macros for field ENABLE */
#define MAC_SLEEP_CONTROL__ENABLE__SHIFT                                      0
#define MAC_SLEEP_CONTROL__ENABLE__WIDTH                                      2
#define MAC_SLEEP_CONTROL__ENABLE__MASK                             0x00000003U
#define MAC_SLEEP_CONTROL__ENABLE__READ(src)     (u_int32_t)(src) & 0x00000003U
#define MAC_SLEEP_CONTROL__ENABLE__WRITE(src)  ((u_int32_t)(src) & 0x00000003U)
#define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))
#define MAC_SLEEP_CONTROL__TYPE                                       u_int32_t
#define MAC_SLEEP_CONTROL__READ                                     0x00000003U
#define MAC_SLEEP_CONTROL__WRITE                                    0x00000003U

#endif /* __MAC_SLEEP_CONTROL_MACRO__ */


/* macros for rtc_reg_map.MAC_SLEEP_CONTROL */
#define INST_RTC_REG_MAP__MAC_SLEEP_CONTROL__NUM                              1

/* macros for BlueprintGlobalNameSpace::KEEP_AWAKE */
#ifndef __KEEP_AWAKE_MACRO__
#define __KEEP_AWAKE_MACRO__

/* macros for field COUNT */
#define KEEP_AWAKE__COUNT__SHIFT                                              0
#define KEEP_AWAKE__COUNT__WIDTH                                              8
#define KEEP_AWAKE__COUNT__MASK                                     0x000000ffU
#define KEEP_AWAKE__COUNT__READ(src)             (u_int32_t)(src) & 0x000000ffU
#define KEEP_AWAKE__COUNT__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
#define KEEP_AWAKE__COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define KEEP_AWAKE__COUNT__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))
#define KEEP_AWAKE__TYPE                                              u_int32_t
#define KEEP_AWAKE__READ                                            0x000000ffU
#define KEEP_AWAKE__WRITE                                           0x000000ffU

#endif /* __KEEP_AWAKE_MACRO__ */


/* macros for rtc_reg_map.KEEP_AWAKE */
#define INST_RTC_REG_MAP__KEEP_AWAKE__NUM                                     1

/* macros for BlueprintGlobalNameSpace::DERIVED_RTC_CLK */
#ifndef __DERIVED_RTC_CLK_MACRO__
#define __DERIVED_RTC_CLK_MACRO__

/* macros for field PERIOD */
#define DERIVED_RTC_CLK__PERIOD__SHIFT                                        1
#define DERIVED_RTC_CLK__PERIOD__WIDTH                                       15
#define DERIVED_RTC_CLK__PERIOD__MASK                               0x0000fffeU
#define DERIVED_RTC_CLK__PERIOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fffeU) >> 1)
#define DERIVED_RTC_CLK__PERIOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000fffeU)
#define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fffeU) | (((u_int32_t)(src) <<\
                    1) & 0x0000fffeU)
#define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000fffeU)))

/* macros for field EXTERNAL_DETECT */
#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SHIFT                              18
#define DERIVED_RTC_CLK__EXTERNAL_DETECT__WIDTH                               1
#define DERIVED_RTC_CLK__EXTERNAL_DETECT__MASK                      0x00040000U
#define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define DERIVED_RTC_CLK__EXTERNAL_DETECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)
#define DERIVED_RTC_CLK__TYPE                                         u_int32_t
#define DERIVED_RTC_CLK__READ                                       0x0004fffeU
#define DERIVED_RTC_CLK__WRITE                                      0x0004fffeU

#endif /* __DERIVED_RTC_CLK_MACRO__ */


/* macros for rtc_reg_map.DERIVED_RTC_CLK */
#define INST_RTC_REG_MAP__DERIVED_RTC_CLK__NUM                                1

/* macros for BlueprintGlobalNameSpace::PLL_CONTROL2 */
#ifndef __PLL_CONTROL2_MACRO__
#define __PLL_CONTROL2_MACRO__

/* macros for field DIV_INT */
#define PLL_CONTROL2__DIV_INT__SHIFT                                          0
#define PLL_CONTROL2__DIV_INT__WIDTH                                          3
#define PLL_CONTROL2__DIV_INT__MASK                                 0x00000007U
#define PLL_CONTROL2__DIV_INT__READ(src)         (u_int32_t)(src) & 0x00000007U
#define PLL_CONTROL2__DIV_INT__WRITE(src)      ((u_int32_t)(src) & 0x00000007U)
#define PLL_CONTROL2__DIV_INT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define PLL_CONTROL2__DIV_INT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field DIV_FRAC */
#define PLL_CONTROL2__DIV_FRAC__SHIFT                                         3
#define PLL_CONTROL2__DIV_FRAC__WIDTH                                         4
#define PLL_CONTROL2__DIV_FRAC__MASK                                0x00000078U
#define PLL_CONTROL2__DIV_FRAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000078U) >> 3)
#define PLL_CONTROL2__DIV_FRAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000078U)
#define PLL_CONTROL2__DIV_FRAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000078U) | (((u_int32_t)(src) <<\
                    3) & 0x00000078U)
#define PLL_CONTROL2__DIV_FRAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000078U)))
#define PLL_CONTROL2__TYPE                                            u_int32_t
#define PLL_CONTROL2__READ                                          0x0000007fU
#define PLL_CONTROL2__WRITE                                         0x0000007fU

#endif /* __PLL_CONTROL2_MACRO__ */


/* macros for rtc_reg_map.PLL_CONTROL2 */
#define INST_RTC_REG_MAP__PLL_CONTROL2__NUM                                   1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_RESET */
#ifndef __RTC_SYNC_RESET_MACRO__
#define __RTC_SYNC_RESET_MACRO__

/* macros for field RESET_L */
#define RTC_SYNC_RESET__RESET_L__SHIFT                                        0
#define RTC_SYNC_RESET__RESET_L__WIDTH                                        1
#define RTC_SYNC_RESET__RESET_L__MASK                               0x00000001U
#define RTC_SYNC_RESET__RESET_L__READ(src)       (u_int32_t)(src) & 0x00000001U
#define RTC_SYNC_RESET__RESET_L__WRITE(src)    ((u_int32_t)(src) & 0x00000001U)
#define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTC_SYNC_RESET__RESET_L__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTC_SYNC_RESET__RESET_L__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_RESET__RESET_L__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define RTC_SYNC_RESET__TYPE                                          u_int32_t
#define RTC_SYNC_RESET__READ                                        0x00000001U
#define RTC_SYNC_RESET__WRITE                                       0x00000001U

#endif /* __RTC_SYNC_RESET_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_RESET */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_RESET__NUM                            1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_STATUS */
#ifndef __RTC_SYNC_STATUS_MACRO__
#define __RTC_SYNC_STATUS_MACRO__

/* macros for field SHUTDOWN_STATE */
#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SHIFT                                0
#define RTC_SYNC_STATUS__SHUTDOWN_STATE__WIDTH                                1
#define RTC_SYNC_STATUS__SHUTDOWN_STATE__MASK                       0x00000001U
#define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_STATUS__SHUTDOWN_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field ON_STATE */
#define RTC_SYNC_STATUS__ON_STATE__SHIFT                                      1
#define RTC_SYNC_STATUS__ON_STATE__WIDTH                                      1
#define RTC_SYNC_STATUS__ON_STATE__MASK                             0x00000002U
#define RTC_SYNC_STATUS__ON_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTC_SYNC_STATUS__ON_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTC_SYNC_STATUS__ON_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field SLEEP_STATE */
#define RTC_SYNC_STATUS__SLEEP_STATE__SHIFT                                   2
#define RTC_SYNC_STATUS__SLEEP_STATE__WIDTH                                   1
#define RTC_SYNC_STATUS__SLEEP_STATE__MASK                          0x00000004U
#define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define RTC_SYNC_STATUS__SLEEP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RTC_SYNC_STATUS__SLEEP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field WAKEUP_STATE */
#define RTC_SYNC_STATUS__WAKEUP_STATE__SHIFT                                  3
#define RTC_SYNC_STATUS__WAKEUP_STATE__WIDTH                                  1
#define RTC_SYNC_STATUS__WAKEUP_STATE__MASK                         0x00000008U
#define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RTC_SYNC_STATUS__WAKEUP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RTC_SYNC_STATUS__WAKEUP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field WRESET */
#define RTC_SYNC_STATUS__WRESET__SHIFT                                        4
#define RTC_SYNC_STATUS__WRESET__WIDTH                                        1
#define RTC_SYNC_STATUS__WRESET__MASK                               0x00000010U
#define RTC_SYNC_STATUS__WRESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RTC_SYNC_STATUS__WRESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RTC_SYNC_STATUS__WRESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PLL_CHANGING */
#define RTC_SYNC_STATUS__PLL_CHANGING__SHIFT                                  5
#define RTC_SYNC_STATUS__PLL_CHANGING__WIDTH                                  1
#define RTC_SYNC_STATUS__PLL_CHANGING__MASK                         0x00000020U
#define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define RTC_SYNC_STATUS__PLL_CHANGING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RTC_SYNC_STATUS__PLL_CHANGING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define RTC_SYNC_STATUS__TYPE                                         u_int32_t
#define RTC_SYNC_STATUS__READ                                       0x0000003fU

#endif /* __RTC_SYNC_STATUS_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_STATUS */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_STATUS__NUM                           1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_DERIVED */
#ifndef __RTC_SYNC_DERIVED_MACRO__
#define __RTC_SYNC_DERIVED_MACRO__

/* macros for field BYPASS */
#define RTC_SYNC_DERIVED__BYPASS__SHIFT                                       0
#define RTC_SYNC_DERIVED__BYPASS__WIDTH                                       1
#define RTC_SYNC_DERIVED__BYPASS__MASK                              0x00000001U
#define RTC_SYNC_DERIVED__BYPASS__READ(src)      (u_int32_t)(src) & 0x00000001U
#define RTC_SYNC_DERIVED__BYPASS__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
#define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTC_SYNC_DERIVED__BYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_DERIVED__BYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field FORCE */
#define RTC_SYNC_DERIVED__FORCE__SHIFT                                        1
#define RTC_SYNC_DERIVED__FORCE__WIDTH                                        1
#define RTC_SYNC_DERIVED__FORCE__MASK                               0x00000002U
#define RTC_SYNC_DERIVED__FORCE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTC_SYNC_DERIVED__FORCE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTC_SYNC_DERIVED__FORCE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTC_SYNC_DERIVED__FORCE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define RTC_SYNC_DERIVED__TYPE                                        u_int32_t
#define RTC_SYNC_DERIVED__READ                                      0x00000003U
#define RTC_SYNC_DERIVED__WRITE                                     0x00000003U

#endif /* __RTC_SYNC_DERIVED_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_DERIVED */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_DERIVED__NUM                          1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_FORCE_WAKE */
#ifndef __RTC_SYNC_FORCE_WAKE_MACRO__
#define __RTC_SYNC_FORCE_WAKE_MACRO__

/* macros for field ENABLE */
#define RTC_SYNC_FORCE_WAKE__ENABLE__SHIFT                                    0
#define RTC_SYNC_FORCE_WAKE__ENABLE__WIDTH                                    1
#define RTC_SYNC_FORCE_WAKE__ENABLE__MASK                           0x00000001U
#define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src)   (u_int32_t)(src) & 0x00000001U
#define RTC_SYNC_FORCE_WAKE__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_FORCE_WAKE__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field INTR */
#define RTC_SYNC_FORCE_WAKE__INTR__SHIFT                                      1
#define RTC_SYNC_FORCE_WAKE__INTR__WIDTH                                      1
#define RTC_SYNC_FORCE_WAKE__INTR__MASK                             0x00000002U
#define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTC_SYNC_FORCE_WAKE__INTR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTC_SYNC_FORCE_WAKE__INTR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define RTC_SYNC_FORCE_WAKE__TYPE                                     u_int32_t
#define RTC_SYNC_FORCE_WAKE__READ                                   0x00000003U
#define RTC_SYNC_FORCE_WAKE__WRITE                                  0x00000003U

#endif /* __RTC_SYNC_FORCE_WAKE_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_FORCE_WAKE */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_FORCE_WAKE__NUM                       1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_CAUSE */
#ifndef __RTC_SYNC_INTR_CAUSE_MACRO__
#define __RTC_SYNC_INTR_CAUSE_MACRO__

/* macros for field SHUTDOWN_STATE */
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SHIFT                            0
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WIDTH                            1
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MASK                   0x00000001U
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field ON_STATE */
#define RTC_SYNC_INTR_CAUSE__ON_STATE__SHIFT                                  1
#define RTC_SYNC_INTR_CAUSE__ON_STATE__WIDTH                                  1
#define RTC_SYNC_INTR_CAUSE__ON_STATE__MASK                         0x00000002U
#define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTC_SYNC_INTR_CAUSE__ON_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTC_SYNC_INTR_CAUSE__ON_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field SLEEP_STATE */
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SHIFT                               2
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WIDTH                               1
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MASK                      0x00000004U
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field WAKEUP_STATE */
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SHIFT                              3
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WIDTH                              1
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MASK                     0x00000008U
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field SLEEP_ACCESS */
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SHIFT                              4
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WIDTH                              1
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MASK                     0x00000010U
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PLL_CHANGING */
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SHIFT                              5
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WIDTH                              1
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MASK                     0x00000020U
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define RTC_SYNC_INTR_CAUSE__TYPE                                     u_int32_t
#define RTC_SYNC_INTR_CAUSE__READ                                   0x0000003fU
#define RTC_SYNC_INTR_CAUSE__WRITE                                  0x0000003fU

#endif /* __RTC_SYNC_INTR_CAUSE_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_CAUSE */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_CAUSE__NUM                       1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_ENABLE */
#ifndef __RTC_SYNC_INTR_ENABLE_MACRO__
#define __RTC_SYNC_INTR_ENABLE_MACRO__

/* macros for field SHUTDOWN_STATE */
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SHIFT                           0
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WIDTH                           1
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MASK                  0x00000001U
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field ON_STATE */
#define RTC_SYNC_INTR_ENABLE__ON_STATE__SHIFT                                 1
#define RTC_SYNC_INTR_ENABLE__ON_STATE__WIDTH                                 1
#define RTC_SYNC_INTR_ENABLE__ON_STATE__MASK                        0x00000002U
#define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTC_SYNC_INTR_ENABLE__ON_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTC_SYNC_INTR_ENABLE__ON_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field SLEEP_STATE */
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SHIFT                              2
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WIDTH                              1
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MASK                     0x00000004U
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field WAKEUP_STATE */
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SHIFT                             3
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WIDTH                             1
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MASK                    0x00000008U
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field SLEEP_ACCESS */
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SHIFT                             4
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WIDTH                             1
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MASK                    0x00000010U
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PLL_CHANGING */
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SHIFT                             5
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WIDTH                             1
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MASK                    0x00000020U
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define RTC_SYNC_INTR_ENABLE__TYPE                                    u_int32_t
#define RTC_SYNC_INTR_ENABLE__READ                                  0x0000003fU
#define RTC_SYNC_INTR_ENABLE__WRITE                                 0x0000003fU

#endif /* __RTC_SYNC_INTR_ENABLE_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_ENABLE */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_ENABLE__NUM                      1

/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_MASK */
#ifndef __RTC_SYNC_INTR_MASK_MACRO__
#define __RTC_SYNC_INTR_MASK_MACRO__

/* macros for field SHUTDOWN_STATE */
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SHIFT                             0
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WIDTH                             1
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MASK                    0x00000001U
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field ON_STATE */
#define RTC_SYNC_INTR_MASK__ON_STATE__SHIFT                                   1
#define RTC_SYNC_INTR_MASK__ON_STATE__WIDTH                                   1
#define RTC_SYNC_INTR_MASK__ON_STATE__MASK                          0x00000002U
#define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTC_SYNC_INTR_MASK__ON_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTC_SYNC_INTR_MASK__ON_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field SLEEP_STATE */
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SHIFT                                2
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WIDTH                                1
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MASK                       0x00000004U
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RTC_SYNC_INTR_MASK__SLEEP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field WAKEUP_STATE */
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SHIFT                               3
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WIDTH                               1
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MASK                      0x00000008U
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field SLEEP_ACCESS */
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SHIFT                               4
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WIDTH                               1
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MASK                      0x00000010U
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PLL_CHANGING */
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SHIFT                               5
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WIDTH                               1
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MASK                      0x00000020U
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RTC_SYNC_INTR_MASK__PLL_CHANGING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define RTC_SYNC_INTR_MASK__TYPE                                      u_int32_t
#define RTC_SYNC_INTR_MASK__READ                                    0x0000003fU
#define RTC_SYNC_INTR_MASK__WRITE                                   0x0000003fU

#endif /* __RTC_SYNC_INTR_MASK_MACRO__ */


/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_MASK */
#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_MASK__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_L32 */
#ifndef __MAC_PCU_STA_ADDR_L32_MACRO__
#define __MAC_PCU_STA_ADDR_L32_MACRO__

/* macros for field ADDR_31_0 */
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__SHIFT                                0
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WIDTH                               32
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MASK                       0xffffffffU
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_STA_ADDR_L32__TYPE                                    u_int32_t
#define MAC_PCU_STA_ADDR_L32__READ                                  0xffffffffU
#define MAC_PCU_STA_ADDR_L32__WRITE                                 0xffffffffU

#endif /* __MAC_PCU_STA_ADDR_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_L32__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_U16 */
#ifndef __MAC_PCU_STA_ADDR_U16_MACRO__
#define __MAC_PCU_STA_ADDR_U16_MACRO__

/* macros for field ADDR_47_32 */
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__SHIFT                               0
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WIDTH                              16
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MASK                      0x0000ffffU
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field STA_AP */
#define MAC_PCU_STA_ADDR_U16__STA_AP__SHIFT                                  16
#define MAC_PCU_STA_ADDR_U16__STA_AP__WIDTH                                   1
#define MAC_PCU_STA_ADDR_U16__STA_AP__MASK                          0x00010000U
#define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_STA_ADDR_U16__STA_AP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_STA_ADDR_U16__STA_AP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field ADHOC */
#define MAC_PCU_STA_ADDR_U16__ADHOC__SHIFT                                   17
#define MAC_PCU_STA_ADDR_U16__ADHOC__WIDTH                                    1
#define MAC_PCU_STA_ADDR_U16__ADHOC__MASK                           0x00020000U
#define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_STA_ADDR_U16__ADHOC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_STA_ADDR_U16__ADHOC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field PW_SAVE */
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SHIFT                                 18
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WIDTH                                  1
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MASK                         0x00040000U
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_STA_ADDR_U16__PW_SAVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field KEYSRCH_DIS */
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SHIFT                             19
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WIDTH                              1
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MASK                     0x00080000U
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field PCF */
#define MAC_PCU_STA_ADDR_U16__PCF__SHIFT                                     20
#define MAC_PCU_STA_ADDR_U16__PCF__WIDTH                                      1
#define MAC_PCU_STA_ADDR_U16__PCF__MASK                             0x00100000U
#define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_STA_ADDR_U16__PCF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_STA_ADDR_U16__PCF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field USE_DEFANT */
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SHIFT                              21
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WIDTH                               1
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MASK                      0x00200000U
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field DEFANT_UPDATE */
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SHIFT                           22
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WIDTH                            1
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MASK                   0x00400000U
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field RTS_USE_DEF */
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SHIFT                             23
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WIDTH                              1
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MASK                     0x00800000U
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field ACKCTS_6MB */
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SHIFT                              24
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WIDTH                               1
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MASK                      0x01000000U
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field BASE_RATE_11B */
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SHIFT                           25
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WIDTH                            1
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MASK                   0x02000000U
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field SECTOR_SELF_GEN */
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SHIFT                         26
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WIDTH                          1
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MASK                 0x04000000U
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field CRPT_MIC_ENABLE */
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SHIFT                         27
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WIDTH                          1
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MASK                 0x08000000U
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field KSRCH_MODE */
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SHIFT                              28
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WIDTH                               1
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MASK                      0x10000000U
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field PRESERVE_SEQNUM */
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SHIFT                         29
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WIDTH                          1
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MASK                 0x20000000U
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field CBCIV_ENDIAN */
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SHIFT                            30
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WIDTH                             1
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MASK                    0x40000000U
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field ADHOC_MCAST_SEARCH */
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SHIFT                      31
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WIDTH                       1
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MASK              0x80000000U
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define MAC_PCU_STA_ADDR_U16__TYPE                                    u_int32_t
#define MAC_PCU_STA_ADDR_U16__READ                                  0xffffffffU
#define MAC_PCU_STA_ADDR_U16__WRITE                                 0xffffffffU

#endif /* __MAC_PCU_STA_ADDR_U16_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_U16 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_U16__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_L32 */
#ifndef __MAC_PCU_BSSID_L32_MACRO__
#define __MAC_PCU_BSSID_L32_MACRO__

/* macros for field ADDR */
#define MAC_PCU_BSSID_L32__ADDR__SHIFT                                        0
#define MAC_PCU_BSSID_L32__ADDR__WIDTH                                       32
#define MAC_PCU_BSSID_L32__ADDR__MASK                               0xffffffffU
#define MAC_PCU_BSSID_L32__ADDR__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_BSSID_L32__ADDR__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BSSID_L32__TYPE                                       u_int32_t
#define MAC_PCU_BSSID_L32__READ                                     0xffffffffU
#define MAC_PCU_BSSID_L32__WRITE                                    0xffffffffU

#endif /* __MAC_PCU_BSSID_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BSSID_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_L32__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_U16 */
#ifndef __MAC_PCU_BSSID_U16_MACRO__
#define __MAC_PCU_BSSID_U16_MACRO__

/* macros for field ADDR */
#define MAC_PCU_BSSID_U16__ADDR__SHIFT                                        0
#define MAC_PCU_BSSID_U16__ADDR__WIDTH                                       16
#define MAC_PCU_BSSID_U16__ADDR__MASK                               0x0000ffffU
#define MAC_PCU_BSSID_U16__ADDR__READ(src)       (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_BSSID_U16__ADDR__WRITE(src)    ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field AID */
#define MAC_PCU_BSSID_U16__AID__SHIFT                                        16
#define MAC_PCU_BSSID_U16__AID__WIDTH                                        11
#define MAC_PCU_BSSID_U16__AID__MASK                                0x07ff0000U
#define MAC_PCU_BSSID_U16__AID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define MAC_PCU_BSSID_U16__AID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x07ff0000U)
#define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x07ff0000U)
#define MAC_PCU_BSSID_U16__AID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x07ff0000U)))
#define MAC_PCU_BSSID_U16__TYPE                                       u_int32_t
#define MAC_PCU_BSSID_U16__READ                                     0x07ffffffU
#define MAC_PCU_BSSID_U16__WRITE                                    0x07ffffffU

#endif /* __MAC_PCU_BSSID_U16_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BSSID_U16 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_U16__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_AVE */
#ifndef __MAC_PCU_BCN_RSSI_AVE_MACRO__
#define __MAC_PCU_BCN_RSSI_AVE_MACRO__

/* macros for field AVE_VALUE */
#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__SHIFT                                0
#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__WIDTH                               12
#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__MASK                       0x00000fffU
#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU

/* macros for field SPARE */
#define MAC_PCU_BCN_RSSI_AVE__SPARE__SHIFT                                   12
#define MAC_PCU_BCN_RSSI_AVE__SPARE__WIDTH                                    8
#define MAC_PCU_BCN_RSSI_AVE__SPARE__MASK                           0x000ff000U
#define MAC_PCU_BCN_RSSI_AVE__SPARE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ff000U) >> 12)
#define MAC_PCU_BCN_RSSI_AVE__SPARE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x000ff000U)
#define MAC_PCU_BCN_RSSI_AVE__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x000ff000U)
#define MAC_PCU_BCN_RSSI_AVE__SPARE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x000ff000U)))
#define MAC_PCU_BCN_RSSI_AVE__TYPE                                    u_int32_t
#define MAC_PCU_BCN_RSSI_AVE__READ                                  0x000fffffU
#define MAC_PCU_BCN_RSSI_AVE__WRITE                                 0x000fffffU

#endif /* __MAC_PCU_BCN_RSSI_AVE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_AVE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_AVE__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_CTS_TIMEOUT */
#ifndef __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__
#define __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__

/* macros for field ACK_TIMEOUT */
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__SHIFT                           0
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WIDTH                          14
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MASK                  0x00003fffU
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field CTS_TIMEOUT */
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__SHIFT                          16
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WIDTH                          14
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MASK                  0x3fff0000U
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3fff0000U) >> 16)
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x3fff0000U)
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x3fff0000U)
#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x3fff0000U)))
#define MAC_PCU_ACK_CTS_TIMEOUT__TYPE                                 u_int32_t
#define MAC_PCU_ACK_CTS_TIMEOUT__READ                               0x3fff3fffU
#define MAC_PCU_ACK_CTS_TIMEOUT__WRITE                              0x3fff3fffU

#endif /* __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_ACK_CTS_TIMEOUT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_CTS_TIMEOUT__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_CTL */
#ifndef __MAC_PCU_BCN_RSSI_CTL_MACRO__
#define __MAC_PCU_BCN_RSSI_CTL_MACRO__

/* macros for field RSSI_THRESH */
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__SHIFT                              0
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WIDTH                              8
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MASK                     0x000000ffU
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field MISS_THRESH */
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__SHIFT                              8
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WIDTH                              8
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MASK                     0x0000ff00U
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field WEIGHT */
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__SHIFT                                  24
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WIDTH                                   5
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MASK                          0x1f000000U
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f000000U) >> 24)
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x1f000000U)
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x1f000000U)
#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x1f000000U)))

/* macros for field RESET */
#define MAC_PCU_BCN_RSSI_CTL__RESET__SHIFT                                   29
#define MAC_PCU_BCN_RSSI_CTL__RESET__WIDTH                                    1
#define MAC_PCU_BCN_RSSI_CTL__RESET__MASK                           0x20000000U
#define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_PCU_BCN_RSSI_CTL__RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_BCN_RSSI_CTL__RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define MAC_PCU_BCN_RSSI_CTL__TYPE                                    u_int32_t
#define MAC_PCU_BCN_RSSI_CTL__READ                                  0x3f00ffffU
#define MAC_PCU_BCN_RSSI_CTL__WRITE                                 0x3f00ffffU

#endif /* __MAC_PCU_BCN_RSSI_CTL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_CTL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_CTL__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_USEC_LATENCY */
#ifndef __MAC_PCU_USEC_LATENCY_MACRO__
#define __MAC_PCU_USEC_LATENCY_MACRO__

/* macros for field USEC */
#define MAC_PCU_USEC_LATENCY__USEC__SHIFT                                     0
#define MAC_PCU_USEC_LATENCY__USEC__WIDTH                                     8
#define MAC_PCU_USEC_LATENCY__USEC__MASK                            0x000000ffU
#define MAC_PCU_USEC_LATENCY__USEC__READ(src)    (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field TX_LATENCY */
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__SHIFT                              14
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WIDTH                               9
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MASK                      0x007fc000U
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007fc000U) >> 14)
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x007fc000U)
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x007fc000U)
#define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x007fc000U)))

/* macros for field RX_LATENCY */
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__SHIFT                              23
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WIDTH                               6
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MASK                      0x1f800000U
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f800000U) >> 23)
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x1f800000U)
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x1f800000U)
#define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x1f800000U)))
#define MAC_PCU_USEC_LATENCY__TYPE                                    u_int32_t
#define MAC_PCU_USEC_LATENCY__READ                                  0x1fffc0ffU
#define MAC_PCU_USEC_LATENCY__WRITE                                 0x1fffc0ffU

#endif /* __MAC_PCU_USEC_LATENCY_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_USEC_LATENCY */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_USEC_LATENCY__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RESET_TSF */
#ifndef __MAC_PCU_RESET_TSF_MACRO__
#define __MAC_PCU_RESET_TSF_MACRO__

/* macros for field ONE_SHOT */
#define MAC_PCU_RESET_TSF__ONE_SHOT__SHIFT                                   24
#define MAC_PCU_RESET_TSF__ONE_SHOT__WIDTH                                    1
#define MAC_PCU_RESET_TSF__ONE_SHOT__MASK                           0x01000000U
#define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_RESET_TSF__ONE_SHOT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_RESET_TSF__ONE_SHOT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field ONE_SHOT2 */
#define MAC_PCU_RESET_TSF__ONE_SHOT2__SHIFT                                  25
#define MAC_PCU_RESET_TSF__ONE_SHOT2__WIDTH                                   1
#define MAC_PCU_RESET_TSF__ONE_SHOT2__MASK                          0x02000000U
#define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_RESET_TSF__ONE_SHOT2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_RESET_TSF__ONE_SHOT2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)
#define MAC_PCU_RESET_TSF__TYPE                                       u_int32_t
#define MAC_PCU_RESET_TSF__READ                                     0x03000000U
#define MAC_PCU_RESET_TSF__WRITE                                    0x03000000U

#endif /* __MAC_PCU_RESET_TSF_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RESET_TSF */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RESET_TSF__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MAX_CFP_DUR */
#ifndef __MAC_PCU_MAX_CFP_DUR_MACRO__
#define __MAC_PCU_MAX_CFP_DUR_MACRO__

/* macros for field VALUE */
#define MAC_PCU_MAX_CFP_DUR__VALUE__SHIFT                                     0
#define MAC_PCU_MAX_CFP_DUR__VALUE__WIDTH                                    16
#define MAC_PCU_MAX_CFP_DUR__VALUE__MASK                            0x0000ffffU
#define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src)    (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field USEC_FRAC_NUMERATOR */
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__SHIFT                      16
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WIDTH                       4
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MASK              0x000f0000U
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field USEC_FRAC_DENOMINATOR */
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__SHIFT                    24
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WIDTH                     4
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MASK            0x0f000000U
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f000000U) >> 24)
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x0f000000U)
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x0f000000U)
#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x0f000000U)))
#define MAC_PCU_MAX_CFP_DUR__TYPE                                     u_int32_t
#define MAC_PCU_MAX_CFP_DUR__READ                                   0x0f0fffffU
#define MAC_PCU_MAX_CFP_DUR__WRITE                                  0x0f0fffffU

#endif /* __MAC_PCU_MAX_CFP_DUR_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MAX_CFP_DUR */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MAX_CFP_DUR__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FILTER */
#ifndef __MAC_PCU_RX_FILTER_MACRO__
#define __MAC_PCU_RX_FILTER_MACRO__

/* macros for field UNICAST */
#define MAC_PCU_RX_FILTER__UNICAST__SHIFT                                     0
#define MAC_PCU_RX_FILTER__UNICAST__WIDTH                                     1
#define MAC_PCU_RX_FILTER__UNICAST__MASK                            0x00000001U
#define MAC_PCU_RX_FILTER__UNICAST__READ(src)    (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
#define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_RX_FILTER__UNICAST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_RX_FILTER__UNICAST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field MULTICAST */
#define MAC_PCU_RX_FILTER__MULTICAST__SHIFT                                   1
#define MAC_PCU_RX_FILTER__MULTICAST__WIDTH                                   1
#define MAC_PCU_RX_FILTER__MULTICAST__MASK                          0x00000002U
#define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_RX_FILTER__MULTICAST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_RX_FILTER__MULTICAST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field BROADCAST */
#define MAC_PCU_RX_FILTER__BROADCAST__SHIFT                                   2
#define MAC_PCU_RX_FILTER__BROADCAST__WIDTH                                   1
#define MAC_PCU_RX_FILTER__BROADCAST__MASK                          0x00000004U
#define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_RX_FILTER__BROADCAST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_RX_FILTER__BROADCAST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field CONTROL */
#define MAC_PCU_RX_FILTER__CONTROL__SHIFT                                     3
#define MAC_PCU_RX_FILTER__CONTROL__WIDTH                                     1
#define MAC_PCU_RX_FILTER__CONTROL__MASK                            0x00000008U
#define MAC_PCU_RX_FILTER__CONTROL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_RX_FILTER__CONTROL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_RX_FILTER__CONTROL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field BEACON */
#define MAC_PCU_RX_FILTER__BEACON__SHIFT                                      4
#define MAC_PCU_RX_FILTER__BEACON__WIDTH                                      1
#define MAC_PCU_RX_FILTER__BEACON__MASK                             0x00000010U
#define MAC_PCU_RX_FILTER__BEACON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_RX_FILTER__BEACON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_RX_FILTER__BEACON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PROMISCUOUS */
#define MAC_PCU_RX_FILTER__PROMISCUOUS__SHIFT                                 5
#define MAC_PCU_RX_FILTER__PROMISCUOUS__WIDTH                                 1
#define MAC_PCU_RX_FILTER__PROMISCUOUS__MASK                        0x00000020U
#define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_RX_FILTER__PROMISCUOUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_RX_FILTER__PROMISCUOUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field XR_POLL */
#define MAC_PCU_RX_FILTER__XR_POLL__SHIFT                                     6
#define MAC_PCU_RX_FILTER__XR_POLL__WIDTH                                     1
#define MAC_PCU_RX_FILTER__XR_POLL__MASK                            0x00000040U
#define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_RX_FILTER__XR_POLL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_RX_FILTER__XR_POLL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field PROBE_REQ */
#define MAC_PCU_RX_FILTER__PROBE_REQ__SHIFT                                   7
#define MAC_PCU_RX_FILTER__PROBE_REQ__WIDTH                                   1
#define MAC_PCU_RX_FILTER__PROBE_REQ__MASK                          0x00000080U
#define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_RX_FILTER__PROBE_REQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_RX_FILTER__PROBE_REQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field SYNC_FRAME */
#define MAC_PCU_RX_FILTER__SYNC_FRAME__SHIFT                                  8
#define MAC_PCU_RX_FILTER__SYNC_FRAME__WIDTH                                  1
#define MAC_PCU_RX_FILTER__SYNC_FRAME__MASK                         0x00000100U
#define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_RX_FILTER__SYNC_FRAME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_RX_FILTER__SYNC_FRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field MY_BEACON */
#define MAC_PCU_RX_FILTER__MY_BEACON__SHIFT                                   9
#define MAC_PCU_RX_FILTER__MY_BEACON__WIDTH                                   1
#define MAC_PCU_RX_FILTER__MY_BEACON__MASK                          0x00000200U
#define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_PCU_RX_FILTER__MY_BEACON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_RX_FILTER__MY_BEACON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field COMPRESSED_BAR */
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SHIFT                             10
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WIDTH                              1
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MASK                     0x00000400U
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field COMPRESSED_BA */
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SHIFT                              11
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WIDTH                               1
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MASK                      0x00000800U
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_RX_FILTER__COMPRESSED_BA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field UNCOMPRESSED_BA_BAR */
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SHIFT                        12
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WIDTH                         1
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MASK                0x00001000U
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field ASSUME_RADAR */
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SHIFT                               13
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WIDTH                                1
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MASK                       0x00002000U
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define MAC_PCU_RX_FILTER__ASSUME_RADAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field PS_POLL */
#define MAC_PCU_RX_FILTER__PS_POLL__SHIFT                                    14
#define MAC_PCU_RX_FILTER__PS_POLL__WIDTH                                     1
#define MAC_PCU_RX_FILTER__PS_POLL__MASK                            0x00004000U
#define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define MAC_PCU_RX_FILTER__PS_POLL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define MAC_PCU_RX_FILTER__PS_POLL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field MCAST_BCAST_ALL */
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SHIFT                            15
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WIDTH                             1
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MASK                    0x00008000U
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field RST_DLMTR_CNT_DISABLE */
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SHIFT                      16
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WIDTH                       1
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MASK              0x00010000U
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field HW_BCN_PROC_ENABLE */
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SHIFT                         17
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WIDTH                          1
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MASK                 0x00020000U
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field MGMT_ACTION_MCAST */
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SHIFT                          18
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WIDTH                           1
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MASK                  0x00040000U
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field CONTROL_WRAPPER */
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SHIFT                            19
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WIDTH                             1
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MASK                    0x00080000U
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field FROM_TO_DS */
#define MAC_PCU_RX_FILTER__FROM_TO_DS__SHIFT                                 20
#define MAC_PCU_RX_FILTER__FROM_TO_DS__WIDTH                                  1
#define MAC_PCU_RX_FILTER__FROM_TO_DS__MASK                         0x00100000U
#define MAC_PCU_RX_FILTER__FROM_TO_DS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_RX_FILTER__FROM_TO_DS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_RX_FILTER__FROM_TO_DS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_RX_FILTER__FROM_TO_DS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_RX_FILTER__FROM_TO_DS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_RX_FILTER__FROM_TO_DS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)
#define MAC_PCU_RX_FILTER__TYPE                                       u_int32_t
#define MAC_PCU_RX_FILTER__READ                                     0x001fffffU
#define MAC_PCU_RX_FILTER__WRITE                                    0x001fffffU

#endif /* __MAC_PCU_RX_FILTER_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RX_FILTER */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FILTER__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_L32 */
#ifndef __MAC_PCU_MCAST_FILTER_L32_MACRO__
#define __MAC_PCU_MCAST_FILTER_L32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_MCAST_FILTER_L32__VALUE__SHIFT                                0
#define MAC_PCU_MCAST_FILTER_L32__VALUE__WIDTH                               32
#define MAC_PCU_MCAST_FILTER_L32__VALUE__MASK                       0xffffffffU
#define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_MCAST_FILTER_L32__TYPE                                u_int32_t
#define MAC_PCU_MCAST_FILTER_L32__READ                              0xffffffffU
#define MAC_PCU_MCAST_FILTER_L32__WRITE                             0xffffffffU

#endif /* __MAC_PCU_MCAST_FILTER_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_L32__NUM                   1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_U32 */
#ifndef __MAC_PCU_MCAST_FILTER_U32_MACRO__
#define __MAC_PCU_MCAST_FILTER_U32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_MCAST_FILTER_U32__VALUE__SHIFT                                0
#define MAC_PCU_MCAST_FILTER_U32__VALUE__WIDTH                               32
#define MAC_PCU_MCAST_FILTER_U32__VALUE__MASK                       0xffffffffU
#define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_MCAST_FILTER_U32__TYPE                                u_int32_t
#define MAC_PCU_MCAST_FILTER_U32__READ                              0xffffffffU
#define MAC_PCU_MCAST_FILTER_U32__WRITE                             0xffffffffU

#endif /* __MAC_PCU_MCAST_FILTER_U32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_U32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_U32__NUM                   1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIAG_SW */
#ifndef __MAC_PCU_DIAG_SW_MACRO__
#define __MAC_PCU_DIAG_SW_MACRO__

/* macros for field INVALID_KEY_NO_ACK */
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SHIFT                            0
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WIDTH                            1
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MASK                   0x00000001U
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field NO_ACK */
#define MAC_PCU_DIAG_SW__NO_ACK__SHIFT                                        1
#define MAC_PCU_DIAG_SW__NO_ACK__WIDTH                                        1
#define MAC_PCU_DIAG_SW__NO_ACK__MASK                               0x00000002U
#define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_DIAG_SW__NO_ACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_DIAG_SW__NO_ACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field NO_CTS */
#define MAC_PCU_DIAG_SW__NO_CTS__SHIFT                                        2
#define MAC_PCU_DIAG_SW__NO_CTS__WIDTH                                        1
#define MAC_PCU_DIAG_SW__NO_CTS__MASK                               0x00000004U
#define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_DIAG_SW__NO_CTS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_DIAG_SW__NO_CTS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field NO_ENCRYPT */
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SHIFT                                    3
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WIDTH                                    1
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MASK                           0x00000008U
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_DIAG_SW__NO_ENCRYPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field NO_DECRYPT */
#define MAC_PCU_DIAG_SW__NO_DECRYPT__SHIFT                                    4
#define MAC_PCU_DIAG_SW__NO_DECRYPT__WIDTH                                    1
#define MAC_PCU_DIAG_SW__NO_DECRYPT__MASK                           0x00000010U
#define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_DIAG_SW__NO_DECRYPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_DIAG_SW__NO_DECRYPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field HALT_RX */
#define MAC_PCU_DIAG_SW__HALT_RX__SHIFT                                       5
#define MAC_PCU_DIAG_SW__HALT_RX__WIDTH                                       1
#define MAC_PCU_DIAG_SW__HALT_RX__MASK                              0x00000020U
#define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_DIAG_SW__HALT_RX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_DIAG_SW__HALT_RX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field LOOP_BACK */
#define MAC_PCU_DIAG_SW__LOOP_BACK__SHIFT                                     6
#define MAC_PCU_DIAG_SW__LOOP_BACK__WIDTH                                     1
#define MAC_PCU_DIAG_SW__LOOP_BACK__MASK                            0x00000040U
#define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_DIAG_SW__LOOP_BACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_DIAG_SW__LOOP_BACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field CORRUPT_FCS */
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SHIFT                                   7
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WIDTH                                   1
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MASK                          0x00000080U
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_DIAG_SW__CORRUPT_FCS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field DUMP_CHAN_INFO */
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SHIFT                                8
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WIDTH                                1
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MASK                       0x00000100U
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field ACCEPT_NON_V0 */
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SHIFT                                17
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WIDTH                                 1
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MASK                        0x00020000U
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field OBS_SEL_1_0 */
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__SHIFT                                  18
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WIDTH                                   2
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MASK                          0x000c0000U
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000c0000U) >> 18)
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x000c0000U)
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x000c0000U)
#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x000c0000U)))

/* macros for field RX_CLEAR_HIGH */
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SHIFT                                20
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WIDTH                                 1
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MASK                        0x00100000U
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field IGNORE_NAV */
#define MAC_PCU_DIAG_SW__IGNORE_NAV__SHIFT                                   21
#define MAC_PCU_DIAG_SW__IGNORE_NAV__WIDTH                                    1
#define MAC_PCU_DIAG_SW__IGNORE_NAV__MASK                           0x00200000U
#define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_DIAG_SW__IGNORE_NAV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_DIAG_SW__IGNORE_NAV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field CHAN_IDLE_HIGH */
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SHIFT                               22
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WIDTH                                1
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MASK                       0x00400000U
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field PHYERR_ENABLE_EIFS_CTL */
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SHIFT                       23
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WIDTH                        1
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MASK               0x00800000U
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field DUAL_CHAIN_CHAN_INFO */
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SHIFT                         24
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WIDTH                          1
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MASK                 0x01000000U
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field FORCE_RX_ABORT */
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SHIFT                               25
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WIDTH                                1
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MASK                       0x02000000U
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field SATURATE_CYCLE_CNT */
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SHIFT                           26
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WIDTH                            1
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MASK                   0x04000000U
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field OBS_SEL_2 */
#define MAC_PCU_DIAG_SW__OBS_SEL_2__SHIFT                                    27
#define MAC_PCU_DIAG_SW__OBS_SEL_2__WIDTH                                     1
#define MAC_PCU_DIAG_SW__OBS_SEL_2__MASK                            0x08000000U
#define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define MAC_PCU_DIAG_SW__OBS_SEL_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define MAC_PCU_DIAG_SW__OBS_SEL_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field RX_CLEAR_CTL_LOW */
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SHIFT                             28
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WIDTH                              1
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MASK                     0x10000000U
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field RX_CLEAR_EXT_LOW */
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SHIFT                             29
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WIDTH                              1
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MASK                     0x20000000U
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field DEBUG_MODE */
#define MAC_PCU_DIAG_SW__DEBUG_MODE__SHIFT                                   30
#define MAC_PCU_DIAG_SW__DEBUG_MODE__WIDTH                                    2
#define MAC_PCU_DIAG_SW__DEBUG_MODE__MASK                           0xc0000000U
#define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define MAC_PCU_DIAG_SW__TYPE                                         u_int32_t
#define MAC_PCU_DIAG_SW__READ                                       0xfffe01ffU
#define MAC_PCU_DIAG_SW__WRITE                                      0xfffe01ffU

#endif /* __MAC_PCU_DIAG_SW_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_DIAG_SW */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_DIAG_SW__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_L32 */
#ifndef __MAC_PCU_TSF_L32_MACRO__
#define __MAC_PCU_TSF_L32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TSF_L32__VALUE__SHIFT                                         0
#define MAC_PCU_TSF_L32__VALUE__WIDTH                                        32
#define MAC_PCU_TSF_L32__VALUE__MASK                                0xffffffffU
#define MAC_PCU_TSF_L32__VALUE__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TSF_L32__VALUE__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TSF_L32__TYPE                                         u_int32_t
#define MAC_PCU_TSF_L32__READ                                       0xffffffffU
#define MAC_PCU_TSF_L32__WRITE                                      0xffffffffU

#endif /* __MAC_PCU_TSF_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TSF_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_L32__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_U32 */
#ifndef __MAC_PCU_TSF_U32_MACRO__
#define __MAC_PCU_TSF_U32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TSF_U32__VALUE__SHIFT                                         0
#define MAC_PCU_TSF_U32__VALUE__WIDTH                                        32
#define MAC_PCU_TSF_U32__VALUE__MASK                                0xffffffffU
#define MAC_PCU_TSF_U32__VALUE__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TSF_U32__VALUE__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TSF_U32__TYPE                                         u_int32_t
#define MAC_PCU_TSF_U32__READ                                       0xffffffffU
#define MAC_PCU_TSF_U32__WRITE                                      0xffffffffU

#endif /* __MAC_PCU_TSF_U32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TSF_U32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_U32__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TST_ADDAC */
#ifndef __MAC_PCU_TST_ADDAC_MACRO__
#define __MAC_PCU_TST_ADDAC_MACRO__

/* macros for field CONT_TX */
#define MAC_PCU_TST_ADDAC__CONT_TX__SHIFT                                     0
#define MAC_PCU_TST_ADDAC__CONT_TX__WIDTH                                     1
#define MAC_PCU_TST_ADDAC__CONT_TX__MASK                            0x00000001U
#define MAC_PCU_TST_ADDAC__CONT_TX__READ(src)    (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
#define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_TST_ADDAC__CONT_TX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_TST_ADDAC__CONT_TX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field TESTMODE */
#define MAC_PCU_TST_ADDAC__TESTMODE__SHIFT                                    1
#define MAC_PCU_TST_ADDAC__TESTMODE__WIDTH                                    1
#define MAC_PCU_TST_ADDAC__TESTMODE__MASK                           0x00000002U
#define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_TST_ADDAC__TESTMODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_TST_ADDAC__TESTMODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field LOOP */
#define MAC_PCU_TST_ADDAC__LOOP__SHIFT                                        2
#define MAC_PCU_TST_ADDAC__LOOP__WIDTH                                        1
#define MAC_PCU_TST_ADDAC__LOOP__MASK                               0x00000004U
#define MAC_PCU_TST_ADDAC__LOOP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_TST_ADDAC__LOOP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_TST_ADDAC__LOOP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field LOOP_LEN */
#define MAC_PCU_TST_ADDAC__LOOP_LEN__SHIFT                                    3
#define MAC_PCU_TST_ADDAC__LOOP_LEN__WIDTH                                   11
#define MAC_PCU_TST_ADDAC__LOOP_LEN__MASK                           0x00003ff8U
#define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003ff8U) >> 3)
#define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00003ff8U)
#define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003ff8U) | (((u_int32_t)(src) <<\
                    3) & 0x00003ff8U)
#define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00003ff8U)))

/* macros for field UPPER_8B */
#define MAC_PCU_TST_ADDAC__UPPER_8B__SHIFT                                   14
#define MAC_PCU_TST_ADDAC__UPPER_8B__WIDTH                                    1
#define MAC_PCU_TST_ADDAC__UPPER_8B__MASK                           0x00004000U
#define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define MAC_PCU_TST_ADDAC__UPPER_8B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define MAC_PCU_TST_ADDAC__UPPER_8B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field SAMPLE_SIZE_2K */
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SHIFT                             15
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WIDTH                              1
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MASK                     0x00008000U
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field TRIG_SEL */
#define MAC_PCU_TST_ADDAC__TRIG_SEL__SHIFT                                   16
#define MAC_PCU_TST_ADDAC__TRIG_SEL__WIDTH                                    1
#define MAC_PCU_TST_ADDAC__TRIG_SEL__MASK                           0x00010000U
#define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_TST_ADDAC__TRIG_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_TST_ADDAC__TRIG_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field TRIG_POLARITY */
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SHIFT                              17
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WIDTH                               1
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MASK                      0x00020000U
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field CONT_TEST */
#define MAC_PCU_TST_ADDAC__CONT_TEST__SHIFT                                  18
#define MAC_PCU_TST_ADDAC__CONT_TEST__WIDTH                                   1
#define MAC_PCU_TST_ADDAC__CONT_TEST__MASK                          0x00040000U
#define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_TST_ADDAC__CONT_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_TST_ADDAC__CONT_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field TEST_CAPTURE */
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SHIFT                               19
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WIDTH                                1
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MASK                       0x00080000U
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field TEST_ARM */
#define MAC_PCU_TST_ADDAC__TEST_ARM__SHIFT                                   20
#define MAC_PCU_TST_ADDAC__TEST_ARM__WIDTH                                    1
#define MAC_PCU_TST_ADDAC__TEST_ARM__MASK                           0x00100000U
#define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_TST_ADDAC__TEST_ARM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_TST_ADDAC__TEST_ARM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)
#define MAC_PCU_TST_ADDAC__TYPE                                       u_int32_t
#define MAC_PCU_TST_ADDAC__READ                                     0x001fffffU
#define MAC_PCU_TST_ADDAC__WRITE                                    0x001fffffU

#endif /* __MAC_PCU_TST_ADDAC_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TST_ADDAC */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TST_ADDAC__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_DEF_ANTENNA */
#ifndef __MAC_PCU_DEF_ANTENNA_MACRO__
#define __MAC_PCU_DEF_ANTENNA_MACRO__

/* macros for field VALUE */
#define MAC_PCU_DEF_ANTENNA__VALUE__SHIFT                                     0
#define MAC_PCU_DEF_ANTENNA__VALUE__WIDTH                                    24
#define MAC_PCU_DEF_ANTENNA__VALUE__MASK                            0x00ffffffU
#define MAC_PCU_DEF_ANTENNA__VALUE__READ(src)    (u_int32_t)(src) & 0x00ffffffU
#define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU)
#define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))

/* macros for field TX_DEF_ANT_SEL */
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SHIFT                           24
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WIDTH                            1
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MASK                   0x01000000U
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field SLOW_TX_ANT_EN */
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SHIFT                           25
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WIDTH                            1
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MASK                   0x02000000U
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field TX_CUR_ANT */
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SHIFT                               26
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WIDTH                                1
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MASK                       0x04000000U
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field FAST_DEF_ANT */
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SHIFT                             27
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WIDTH                              1
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MASK                     0x08000000U
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field RX_LNA_CONFIG_SEL */
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SHIFT                        28
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WIDTH                         1
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MASK                0x10000000U
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field FAST_TX_ANT_EN */
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SHIFT                           29
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WIDTH                            1
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MASK                   0x20000000U
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field RX_ANT_EN */
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SHIFT                                30
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WIDTH                                 1
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MASK                        0x40000000U
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field RX_ANT_DIV_ON */
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SHIFT                            31
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WIDTH                             1
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MASK                    0x80000000U
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define MAC_PCU_DEF_ANTENNA__TYPE                                     u_int32_t
#define MAC_PCU_DEF_ANTENNA__READ                                   0xffffffffU
#define MAC_PCU_DEF_ANTENNA__WRITE                                  0xffffffffU

#endif /* __MAC_PCU_DEF_ANTENNA_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_DEF_ANTENNA */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_DEF_ANTENNA__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_0 */
#ifndef __MAC_PCU_AES_MUTE_MASK_0_MACRO__
#define __MAC_PCU_AES_MUTE_MASK_0_MACRO__

/* macros for field FC */
#define MAC_PCU_AES_MUTE_MASK_0__FC__SHIFT                                    0
#define MAC_PCU_AES_MUTE_MASK_0__FC__WIDTH                                   16
#define MAC_PCU_AES_MUTE_MASK_0__FC__MASK                           0x0000ffffU
#define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src)   (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field QOS */
#define MAC_PCU_AES_MUTE_MASK_0__QOS__SHIFT                                  16
#define MAC_PCU_AES_MUTE_MASK_0__QOS__WIDTH                                  16
#define MAC_PCU_AES_MUTE_MASK_0__QOS__MASK                          0xffff0000U
#define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_AES_MUTE_MASK_0__TYPE                                 u_int32_t
#define MAC_PCU_AES_MUTE_MASK_0__READ                               0xffffffffU
#define MAC_PCU_AES_MUTE_MASK_0__WRITE                              0xffffffffU

#endif /* __MAC_PCU_AES_MUTE_MASK_0_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_0 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_0__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_1 */
#ifndef __MAC_PCU_AES_MUTE_MASK_1_MACRO__
#define __MAC_PCU_AES_MUTE_MASK_1_MACRO__

/* macros for field SEQ */
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__SHIFT                                   0
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WIDTH                                  16
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MASK                          0x0000ffffU
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src)  (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field FC_MGMT */
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__SHIFT                              16
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WIDTH                              16
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MASK                      0xffff0000U
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_AES_MUTE_MASK_1__TYPE                                 u_int32_t
#define MAC_PCU_AES_MUTE_MASK_1__READ                               0xffffffffU
#define MAC_PCU_AES_MUTE_MASK_1__WRITE                              0xffffffffU

#endif /* __MAC_PCU_AES_MUTE_MASK_1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_1__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_GATED_CLKS */
#ifndef __MAC_PCU_GATED_CLKS_MACRO__
#define __MAC_PCU_GATED_CLKS_MACRO__

/* macros for field GATED_TX */
#define MAC_PCU_GATED_CLKS__GATED_TX__SHIFT                                   1
#define MAC_PCU_GATED_CLKS__GATED_TX__WIDTH                                   1
#define MAC_PCU_GATED_CLKS__GATED_TX__MASK                          0x00000002U
#define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_GATED_CLKS__GATED_TX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_GATED_CLKS__GATED_TX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field GATED_RX */
#define MAC_PCU_GATED_CLKS__GATED_RX__SHIFT                                   2
#define MAC_PCU_GATED_CLKS__GATED_RX__WIDTH                                   1
#define MAC_PCU_GATED_CLKS__GATED_RX__MASK                          0x00000004U
#define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_GATED_CLKS__GATED_RX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_GATED_CLKS__GATED_RX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field GATED_REG */
#define MAC_PCU_GATED_CLKS__GATED_REG__SHIFT                                  3
#define MAC_PCU_GATED_CLKS__GATED_REG__WIDTH                                  1
#define MAC_PCU_GATED_CLKS__GATED_REG__MASK                         0x00000008U
#define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_GATED_CLKS__GATED_REG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_GATED_CLKS__GATED_REG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)
#define MAC_PCU_GATED_CLKS__TYPE                                      u_int32_t
#define MAC_PCU_GATED_CLKS__READ                                    0x0000000eU
#define MAC_PCU_GATED_CLKS__WRITE                                   0x0000000eU

#endif /* __MAC_PCU_GATED_CLKS_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_GATED_CLKS */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_GATED_CLKS__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_2 */
#ifndef __MAC_PCU_OBS_BUS_2_MACRO__
#define __MAC_PCU_OBS_BUS_2_MACRO__

/* macros for field VALUE */
#define MAC_PCU_OBS_BUS_2__VALUE__SHIFT                                       0
#define MAC_PCU_OBS_BUS_2__VALUE__WIDTH                                      18
#define MAC_PCU_OBS_BUS_2__VALUE__MASK                              0x0003ffffU
#define MAC_PCU_OBS_BUS_2__VALUE__READ(src)      (u_int32_t)(src) & 0x0003ffffU

/* macros for field WCF_STATE */
#define MAC_PCU_OBS_BUS_2__WCF_STATE__SHIFT                                  18
#define MAC_PCU_OBS_BUS_2__WCF_STATE__WIDTH                                   4
#define MAC_PCU_OBS_BUS_2__WCF_STATE__MASK                          0x003c0000U
#define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003c0000U) >> 18)

/* macros for field WCF0_FULL */
#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SHIFT                                  22
#define MAC_PCU_OBS_BUS_2__WCF0_FULL__WIDTH                                   1
#define MAC_PCU_OBS_BUS_2__WCF0_FULL__MASK                          0x00400000U
#define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_OBS_BUS_2__WCF0_FULL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field WCF1_FULL */
#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SHIFT                                  23
#define MAC_PCU_OBS_BUS_2__WCF1_FULL__WIDTH                                   1
#define MAC_PCU_OBS_BUS_2__WCF1_FULL__MASK                          0x00800000U
#define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_PCU_OBS_BUS_2__WCF1_FULL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field WCF_COUNT */
#define MAC_PCU_OBS_BUS_2__WCF_COUNT__SHIFT                                  24
#define MAC_PCU_OBS_BUS_2__WCF_COUNT__WIDTH                                   5
#define MAC_PCU_OBS_BUS_2__WCF_COUNT__MASK                          0x1f000000U
#define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f000000U) >> 24)

/* macros for field MACBB_ALL_AWAKE */
#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SHIFT                            29
#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__WIDTH                             1
#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__MASK                    0x20000000U
#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define MAC_PCU_OBS_BUS_2__TYPE                                       u_int32_t
#define MAC_PCU_OBS_BUS_2__READ                                     0x3fffffffU

#endif /* __MAC_PCU_OBS_BUS_2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_2__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_1 */
#ifndef __MAC_PCU_OBS_BUS_1_MACRO__
#define __MAC_PCU_OBS_BUS_1_MACRO__

/* macros for field PCU_DIRECTED */
#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SHIFT                                0
#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__WIDTH                                1
#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__MASK                       0x00000001U
#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field PCU_RX_END */
#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SHIFT                                  1
#define MAC_PCU_OBS_BUS_1__PCU_RX_END__WIDTH                                  1
#define MAC_PCU_OBS_BUS_1__PCU_RX_END__MASK                         0x00000002U
#define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_OBS_BUS_1__PCU_RX_END__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field RX_WEP */
#define MAC_PCU_OBS_BUS_1__RX_WEP__SHIFT                                      2
#define MAC_PCU_OBS_BUS_1__RX_WEP__WIDTH                                      1
#define MAC_PCU_OBS_BUS_1__RX_WEP__MASK                             0x00000004U
#define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_OBS_BUS_1__RX_WEP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_OBS_BUS_1__RX_WEP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field RX_MY_BEACON */
#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SHIFT                                3
#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__WIDTH                                1
#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__MASK                       0x00000008U
#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field FILTER_PASS */
#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SHIFT                                 4
#define MAC_PCU_OBS_BUS_1__FILTER_PASS__WIDTH                                 1
#define MAC_PCU_OBS_BUS_1__FILTER_PASS__MASK                        0x00000010U
#define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_OBS_BUS_1__FILTER_PASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field TX_HCF */
#define MAC_PCU_OBS_BUS_1__TX_HCF__SHIFT                                      5
#define MAC_PCU_OBS_BUS_1__TX_HCF__WIDTH                                      1
#define MAC_PCU_OBS_BUS_1__TX_HCF__MASK                             0x00000020U
#define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_OBS_BUS_1__TX_HCF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_OBS_BUS_1__TX_HCF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field TM_QUIET_TIME */
#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SHIFT                               6
#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__WIDTH                               1
#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__MASK                      0x00000040U
#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field PCU_CHANNEL_IDLE */
#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SHIFT                            7
#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__WIDTH                            1
#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__MASK                   0x00000080U
#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field TX_HOLD */
#define MAC_PCU_OBS_BUS_1__TX_HOLD__SHIFT                                     8
#define MAC_PCU_OBS_BUS_1__TX_HOLD__WIDTH                                     1
#define MAC_PCU_OBS_BUS_1__TX_HOLD__MASK                            0x00000100U
#define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_OBS_BUS_1__TX_HOLD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_OBS_BUS_1__TX_HOLD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field TX_FRAME */
#define MAC_PCU_OBS_BUS_1__TX_FRAME__SHIFT                                    9
#define MAC_PCU_OBS_BUS_1__TX_FRAME__WIDTH                                    1
#define MAC_PCU_OBS_BUS_1__TX_FRAME__MASK                           0x00000200U
#define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_OBS_BUS_1__TX_FRAME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_OBS_BUS_1__TX_FRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field RX_FRAME */
#define MAC_PCU_OBS_BUS_1__RX_FRAME__SHIFT                                   10
#define MAC_PCU_OBS_BUS_1__RX_FRAME__WIDTH                                    1
#define MAC_PCU_OBS_BUS_1__RX_FRAME__MASK                           0x00000400U
#define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_PCU_OBS_BUS_1__RX_FRAME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_PCU_OBS_BUS_1__RX_FRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field RX_CLEAR */
#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SHIFT                                   11
#define MAC_PCU_OBS_BUS_1__RX_CLEAR__WIDTH                                    1
#define MAC_PCU_OBS_BUS_1__RX_CLEAR__MASK                           0x00000800U
#define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_OBS_BUS_1__RX_CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field WEP_STATE */
#define MAC_PCU_OBS_BUS_1__WEP_STATE__SHIFT                                  12
#define MAC_PCU_OBS_BUS_1__WEP_STATE__WIDTH                                   6
#define MAC_PCU_OBS_BUS_1__WEP_STATE__MASK                          0x0003f000U
#define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)

/* macros for field RX_STATE */
#define MAC_PCU_OBS_BUS_1__RX_STATE__SHIFT                                   20
#define MAC_PCU_OBS_BUS_1__RX_STATE__WIDTH                                    5
#define MAC_PCU_OBS_BUS_1__RX_STATE__MASK                           0x01f00000U
#define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)

/* macros for field TX_STATE */
#define MAC_PCU_OBS_BUS_1__TX_STATE__SHIFT                                   25
#define MAC_PCU_OBS_BUS_1__TX_STATE__WIDTH                                    6
#define MAC_PCU_OBS_BUS_1__TX_STATE__MASK                           0x7e000000U
#define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7e000000U) >> 25)
#define MAC_PCU_OBS_BUS_1__TYPE                                       u_int32_t
#define MAC_PCU_OBS_BUS_1__READ                                     0x7ff3ffffU

#endif /* __MAC_PCU_OBS_BUS_1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_1__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_DYM_MIMO_PWR_SAVE */
#ifndef __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__
#define __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__

/* macros for field USE_MAC_CTRL */
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SHIFT                        0
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WIDTH                        1
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MASK               0x00000001U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field HW_CTRL_EN */
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SHIFT                          1
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WIDTH                          1
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MASK                 0x00000002U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field SW_CHAIN_MASK_SEL */
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SHIFT                   2
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WIDTH                   1
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MASK          0x00000004U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field LOW_PWR_CHAIN_MASK */
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__SHIFT                  4
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WIDTH                  3
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MASK         0x00000070U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000070U) >> 4)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000070U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((u_int32_t)(src) <<\
                    4) & 0x00000070U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field HI_PWR_CHAIN_MASK */
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__SHIFT                   8
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WIDTH                   3
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MASK          0x00000700U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000700U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))
#define MAC_PCU_DYM_MIMO_PWR_SAVE__TYPE                               u_int32_t
#define MAC_PCU_DYM_MIMO_PWR_SAVE__READ                             0x00000777U
#define MAC_PCU_DYM_MIMO_PWR_SAVE__WRITE                            0x00000777U

#endif /* __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_DYM_MIMO_PWR_SAVE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_DYM_MIMO_PWR_SAVE__NUM                  1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */
#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__
#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__SHIFT             0
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WIDTH            32
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MASK    0xffffffffU
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__TYPE             u_int32_t
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__READ           0xffffffffU
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__WRITE          0xffffffffU

#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__NUM \
                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */
#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__
#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__SHIFT             0
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WIDTH            32
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MASK    0xffffffffU
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__TYPE             u_int32_t
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__READ           0xffffffffU
#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__WRITE          0xffffffffU

#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__NUM \
                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LAST_BEACON_TSF */
#ifndef __MAC_PCU_LAST_BEACON_TSF_MACRO__
#define __MAC_PCU_LAST_BEACON_TSF_MACRO__

/* macros for field VALUE */
#define MAC_PCU_LAST_BEACON_TSF__VALUE__SHIFT                                 0
#define MAC_PCU_LAST_BEACON_TSF__VALUE__WIDTH                                32
#define MAC_PCU_LAST_BEACON_TSF__VALUE__MASK                        0xffffffffU
#define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_LAST_BEACON_TSF__TYPE                                 u_int32_t
#define MAC_PCU_LAST_BEACON_TSF__READ                               0xffffffffU

#endif /* __MAC_PCU_LAST_BEACON_TSF_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LAST_BEACON_TSF */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LAST_BEACON_TSF__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_NAV */
#ifndef __MAC_PCU_NAV_MACRO__
#define __MAC_PCU_NAV_MACRO__

/* macros for field VALUE */
#define MAC_PCU_NAV__VALUE__SHIFT                                             0
#define MAC_PCU_NAV__VALUE__WIDTH                                            26
#define MAC_PCU_NAV__VALUE__MASK                                    0x03ffffffU
#define MAC_PCU_NAV__VALUE__READ(src)            (u_int32_t)(src) & 0x03ffffffU
#define MAC_PCU_NAV__VALUE__WRITE(src)         ((u_int32_t)(src) & 0x03ffffffU)
#define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ffffffU) | ((u_int32_t)(src) &\
                    0x03ffffffU)
#define MAC_PCU_NAV__VALUE__VERIFY(src)  (!(((u_int32_t)(src) & ~0x03ffffffU)))
#define MAC_PCU_NAV__TYPE                                             u_int32_t
#define MAC_PCU_NAV__READ                                           0x03ffffffU
#define MAC_PCU_NAV__WRITE                                          0x03ffffffU

#endif /* __MAC_PCU_NAV_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_NAV */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_NAV__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_SUCCESS_CNT */
#ifndef __MAC_PCU_RTS_SUCCESS_CNT_MACRO__
#define __MAC_PCU_RTS_SUCCESS_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__SHIFT                                 0
#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__WIDTH                                16
#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__MASK                        0x0000ffffU
#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_PCU_RTS_SUCCESS_CNT__TYPE                                 u_int32_t
#define MAC_PCU_RTS_SUCCESS_CNT__READ                               0x0000ffffU

#endif /* __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RTS_SUCCESS_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_SUCCESS_CNT__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_FAIL_CNT */
#ifndef __MAC_PCU_RTS_FAIL_CNT_MACRO__
#define __MAC_PCU_RTS_FAIL_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_RTS_FAIL_CNT__VALUE__SHIFT                                    0
#define MAC_PCU_RTS_FAIL_CNT__VALUE__WIDTH                                   16
#define MAC_PCU_RTS_FAIL_CNT__VALUE__MASK                           0x0000ffffU
#define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_RTS_FAIL_CNT__TYPE                                    u_int32_t
#define MAC_PCU_RTS_FAIL_CNT__READ                                  0x0000ffffU

#endif /* __MAC_PCU_RTS_FAIL_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RTS_FAIL_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_FAIL_CNT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_FAIL_CNT */
#ifndef __MAC_PCU_ACK_FAIL_CNT_MACRO__
#define __MAC_PCU_ACK_FAIL_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_ACK_FAIL_CNT__VALUE__SHIFT                                    0
#define MAC_PCU_ACK_FAIL_CNT__VALUE__WIDTH                                   16
#define MAC_PCU_ACK_FAIL_CNT__VALUE__MASK                           0x0000ffffU
#define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_ACK_FAIL_CNT__TYPE                                    u_int32_t
#define MAC_PCU_ACK_FAIL_CNT__READ                                  0x0000ffffU

#endif /* __MAC_PCU_ACK_FAIL_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_ACK_FAIL_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_FAIL_CNT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_FCS_FAIL_CNT */
#ifndef __MAC_PCU_FCS_FAIL_CNT_MACRO__
#define __MAC_PCU_FCS_FAIL_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_FCS_FAIL_CNT__VALUE__SHIFT                                    0
#define MAC_PCU_FCS_FAIL_CNT__VALUE__WIDTH                                   16
#define MAC_PCU_FCS_FAIL_CNT__VALUE__MASK                           0x0000ffffU
#define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_FCS_FAIL_CNT__TYPE                                    u_int32_t
#define MAC_PCU_FCS_FAIL_CNT__READ                                  0x0000ffffU

#endif /* __MAC_PCU_FCS_FAIL_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_FCS_FAIL_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_FCS_FAIL_CNT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BEACON_CNT */
#ifndef __MAC_PCU_BEACON_CNT_MACRO__
#define __MAC_PCU_BEACON_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BEACON_CNT__VALUE__SHIFT                                      0
#define MAC_PCU_BEACON_CNT__VALUE__WIDTH                                     16
#define MAC_PCU_BEACON_CNT__VALUE__MASK                             0x0000ffffU
#define MAC_PCU_BEACON_CNT__VALUE__READ(src)     (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_BEACON_CNT__TYPE                                      u_int32_t
#define MAC_PCU_BEACON_CNT__READ                                    0x0000ffffU

#endif /* __MAC_PCU_BEACON_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BEACON_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BEACON_CNT__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_SLOT_ALERT_CNTL */
#ifndef __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__
#define __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__SHIFT                            0
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WIDTH                           16
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MASK                   0x0000ffffU
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__TYPE                            u_int32_t
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__READ                          0x0000ffffU
#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__WRITE                         0x0000ffffU

#endif /* __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_SLOT_ALERT_CNTL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_SLOT_ALERT_CNTL__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BASIC_SET */
#ifndef __MAC_PCU_BASIC_SET_MACRO__
#define __MAC_PCU_BASIC_SET_MACRO__

/* macros for field MCS */
#define MAC_PCU_BASIC_SET__MCS__SHIFT                                         0
#define MAC_PCU_BASIC_SET__MCS__WIDTH                                        32
#define MAC_PCU_BASIC_SET__MCS__MASK                                0xffffffffU
#define MAC_PCU_BASIC_SET__MCS__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_BASIC_SET__MCS__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BASIC_SET__TYPE                                       u_int32_t
#define MAC_PCU_BASIC_SET__READ                                     0xffffffffU
#define MAC_PCU_BASIC_SET__WRITE                                    0xffffffffU

#endif /* __MAC_PCU_BASIC_SET_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BASIC_SET */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BASIC_SET__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MGMT_SEQ */
#ifndef __MAC_PCU_MGMT_SEQ_MACRO__
#define __MAC_PCU_MGMT_SEQ_MACRO__

/* macros for field MIN */
#define MAC_PCU_MGMT_SEQ__MIN__SHIFT                                          0
#define MAC_PCU_MGMT_SEQ__MIN__WIDTH                                         12
#define MAC_PCU_MGMT_SEQ__MIN__MASK                                 0x00000fffU
#define MAC_PCU_MGMT_SEQ__MIN__READ(src)         (u_int32_t)(src) & 0x00000fffU
#define MAC_PCU_MGMT_SEQ__MIN__WRITE(src)      ((u_int32_t)(src) & 0x00000fffU)
#define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field MAX */
#define MAC_PCU_MGMT_SEQ__MAX__SHIFT                                         16
#define MAC_PCU_MGMT_SEQ__MAX__WIDTH                                         12
#define MAC_PCU_MGMT_SEQ__MAX__MASK                                 0x0fff0000U
#define MAC_PCU_MGMT_SEQ__MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fff0000U) >> 16)
#define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x0fff0000U)
#define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x0fff0000U)
#define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x0fff0000U)))
#define MAC_PCU_MGMT_SEQ__TYPE                                        u_int32_t
#define MAC_PCU_MGMT_SEQ__READ                                      0x0fff0fffU
#define MAC_PCU_MGMT_SEQ__WRITE                                     0x0fff0fffU

#endif /* __MAC_PCU_MGMT_SEQ_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MGMT_SEQ */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MGMT_SEQ__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT1 */
#ifndef __MAC_PCU_BF_RPT1_MACRO__
#define __MAC_PCU_BF_RPT1_MACRO__

/* macros for field V_ACTION_VALUE */
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__SHIFT                                0
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WIDTH                                8
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MASK                       0x000000ffU
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field CV_ACTION_VALUE */
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__SHIFT                               8
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WIDTH                               8
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MASK                      0x0000ff00U
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field CATEGORY_VALUE */
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__SHIFT                               16
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WIDTH                                8
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MASK                       0x00ff0000U
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field FRAME_SUBTYPE_VALUE */
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__SHIFT                          24
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WIDTH                           4
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MASK                  0x0f000000U
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f000000U) >> 24)
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x0f000000U)
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x0f000000U)
#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field FRAME_TYPE_VALUE */
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__SHIFT                             28
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WIDTH                              2
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MASK                     0x30000000U
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x30000000U) >> 28)
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x30000000U)
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((u_int32_t)(src) <<\
                    28) & 0x30000000U)
#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x30000000U)))
#define MAC_PCU_BF_RPT1__TYPE                                         u_int32_t
#define MAC_PCU_BF_RPT1__READ                                       0x3fffffffU
#define MAC_PCU_BF_RPT1__WRITE                                      0x3fffffffU

#endif /* __MAC_PCU_BF_RPT1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT1__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT2 */
#ifndef __MAC_PCU_BF_RPT2_MACRO__
#define __MAC_PCU_BF_RPT2_MACRO__

/* macros for field FRAME_SUBTYPE_VALUE */
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__SHIFT                           0
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WIDTH                           4
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MASK                  0x0000000fU
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))
#define MAC_PCU_BF_RPT2__TYPE                                         u_int32_t
#define MAC_PCU_BF_RPT2__READ                                       0x0000000fU
#define MAC_PCU_BF_RPT2__WRITE                                      0x0000000fU

#endif /* __MAC_PCU_BF_RPT2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT2__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_1 */
#ifndef __MAC_PCU_TX_ANT_1_MACRO__
#define __MAC_PCU_TX_ANT_1_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TX_ANT_1__VALUE__SHIFT                                        0
#define MAC_PCU_TX_ANT_1__VALUE__WIDTH                                       32
#define MAC_PCU_TX_ANT_1__VALUE__MASK                               0xffffffffU
#define MAC_PCU_TX_ANT_1__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TX_ANT_1__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TX_ANT_1__TYPE                                        u_int32_t
#define MAC_PCU_TX_ANT_1__READ                                      0xffffffffU
#define MAC_PCU_TX_ANT_1__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TX_ANT_1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_1__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_2 */
#ifndef __MAC_PCU_TX_ANT_2_MACRO__
#define __MAC_PCU_TX_ANT_2_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TX_ANT_2__VALUE__SHIFT                                        0
#define MAC_PCU_TX_ANT_2__VALUE__WIDTH                                       32
#define MAC_PCU_TX_ANT_2__VALUE__MASK                               0xffffffffU
#define MAC_PCU_TX_ANT_2__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TX_ANT_2__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TX_ANT_2__TYPE                                        u_int32_t
#define MAC_PCU_TX_ANT_2__READ                                      0xffffffffU
#define MAC_PCU_TX_ANT_2__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TX_ANT_2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_2__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_3 */
#ifndef __MAC_PCU_TX_ANT_3_MACRO__
#define __MAC_PCU_TX_ANT_3_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TX_ANT_3__VALUE__SHIFT                                        0
#define MAC_PCU_TX_ANT_3__VALUE__WIDTH                                       32
#define MAC_PCU_TX_ANT_3__VALUE__MASK                               0xffffffffU
#define MAC_PCU_TX_ANT_3__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TX_ANT_3__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TX_ANT_3__TYPE                                        u_int32_t
#define MAC_PCU_TX_ANT_3__READ                                      0xffffffffU
#define MAC_PCU_TX_ANT_3__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TX_ANT_3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_3__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_4 */
#ifndef __MAC_PCU_TX_ANT_4_MACRO__
#define __MAC_PCU_TX_ANT_4_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TX_ANT_4__VALUE__SHIFT                                        0
#define MAC_PCU_TX_ANT_4__VALUE__WIDTH                                       32
#define MAC_PCU_TX_ANT_4__VALUE__MASK                               0xffffffffU
#define MAC_PCU_TX_ANT_4__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TX_ANT_4__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TX_ANT_4__TYPE                                        u_int32_t
#define MAC_PCU_TX_ANT_4__READ                                      0xffffffffU
#define MAC_PCU_TX_ANT_4__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TX_ANT_4_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_4 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_4__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRMODE */
#ifndef __MAC_PCU_XRMODE_MACRO__
#define __MAC_PCU_XRMODE_MACRO__

/* macros for field POLL_TYPE */
#define MAC_PCU_XRMODE__POLL_TYPE__SHIFT                                      0
#define MAC_PCU_XRMODE__POLL_TYPE__WIDTH                                      6
#define MAC_PCU_XRMODE__POLL_TYPE__MASK                             0x0000003fU
#define MAC_PCU_XRMODE__POLL_TYPE__READ(src)     (u_int32_t)(src) & 0x0000003fU
#define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src)  ((u_int32_t)(src) & 0x0000003fU)
#define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field WAIT_FOR_POLL */
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SHIFT                                  7
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WIDTH                                  1
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MASK                         0x00000080U
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_XRMODE__WAIT_FOR_POLL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field FRAME_HOLD */
#define MAC_PCU_XRMODE__FRAME_HOLD__SHIFT                                    20
#define MAC_PCU_XRMODE__FRAME_HOLD__WIDTH                                    12
#define MAC_PCU_XRMODE__FRAME_HOLD__MASK                            0xfff00000U
#define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfff00000U) >> 20)
#define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0xfff00000U)
#define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfff00000U) | (((u_int32_t)(src) <<\
                    20) & 0xfff00000U)
#define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0xfff00000U)))
#define MAC_PCU_XRMODE__TYPE                                          u_int32_t
#define MAC_PCU_XRMODE__READ                                        0xfff000bfU
#define MAC_PCU_XRMODE__WRITE                                       0xfff000bfU

#endif /* __MAC_PCU_XRMODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_XRMODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRMODE__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRDEL */
#ifndef __MAC_PCU_XRDEL_MACRO__
#define __MAC_PCU_XRDEL_MACRO__

/* macros for field SLOT_DELAY */
#define MAC_PCU_XRDEL__SLOT_DELAY__SHIFT                                      0
#define MAC_PCU_XRDEL__SLOT_DELAY__WIDTH                                     16
#define MAC_PCU_XRDEL__SLOT_DELAY__MASK                             0x0000ffffU
#define MAC_PCU_XRDEL__SLOT_DELAY__READ(src)     (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src)  ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field CHIRP_DATA_DELAY */
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__SHIFT                               16
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WIDTH                               16
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MASK                       0xffff0000U
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_XRDEL__TYPE                                           u_int32_t
#define MAC_PCU_XRDEL__READ                                         0xffffffffU
#define MAC_PCU_XRDEL__WRITE                                        0xffffffffU

#endif /* __MAC_PCU_XRDEL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_XRDEL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRDEL__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRTO */
#ifndef __MAC_PCU_XRTO_MACRO__
#define __MAC_PCU_XRTO_MACRO__

/* macros for field CHIRP_TIMEOUT */
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__SHIFT                                    0
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WIDTH                                   16
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MASK                           0x0000ffffU
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src)   (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field POLL_TIMEOUT */
#define MAC_PCU_XRTO__POLL_TIMEOUT__SHIFT                                    16
#define MAC_PCU_XRTO__POLL_TIMEOUT__WIDTH                                    16
#define MAC_PCU_XRTO__POLL_TIMEOUT__MASK                            0xffff0000U
#define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_XRTO__TYPE                                            u_int32_t
#define MAC_PCU_XRTO__READ                                          0xffffffffU
#define MAC_PCU_XRTO__WRITE                                         0xffffffffU

#endif /* __MAC_PCU_XRTO_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_XRTO */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRTO__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRCRP */
#ifndef __MAC_PCU_XRCRP_MACRO__
#define __MAC_PCU_XRCRP_MACRO__

/* macros for field SEND_CHIRP */
#define MAC_PCU_XRCRP__SEND_CHIRP__SHIFT                                      0
#define MAC_PCU_XRCRP__SEND_CHIRP__WIDTH                                      1
#define MAC_PCU_XRCRP__SEND_CHIRP__MASK                             0x00000001U
#define MAC_PCU_XRCRP__SEND_CHIRP__READ(src)     (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
#define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_XRCRP__SEND_CHIRP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_XRCRP__SEND_CHIRP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field CHIRP_GAP */
#define MAC_PCU_XRCRP__CHIRP_GAP__SHIFT                                      16
#define MAC_PCU_XRCRP__CHIRP_GAP__WIDTH                                      16
#define MAC_PCU_XRCRP__CHIRP_GAP__MASK                              0xffff0000U
#define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_XRCRP__TYPE                                           u_int32_t
#define MAC_PCU_XRCRP__READ                                         0xffff0001U
#define MAC_PCU_XRCRP__WRITE                                        0xffff0001U

#endif /* __MAC_PCU_XRCRP_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_XRCRP */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRCRP__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRSTMP */
#ifndef __MAC_PCU_XRSTMP_MACRO__
#define __MAC_PCU_XRSTMP_MACRO__

/* macros for field RX_ABORT_RSSI */
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SHIFT                                  0
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WIDTH                                  1
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MASK                         0x00000001U
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field RX_ABORT_BSSID */
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SHIFT                                 1
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WIDTH                                 1
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MASK                        0x00000002U
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field TX_STOMP_RSSI */
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SHIFT                                  2
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WIDTH                                  1
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MASK                         0x00000004U
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field TX_STOMP_BSSID */
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SHIFT                                 3
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WIDTH                                 1
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MASK                        0x00000008U
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field TX_STOMP_DATA */
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SHIFT                                  4
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WIDTH                                  1
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MASK                         0x00000010U
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_XRSTMP__TX_STOMP_DATA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field RX_ABORT_DATA */
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SHIFT                                  5
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WIDTH                                  1
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MASK                         0x00000020U
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_XRSTMP__RX_ABORT_DATA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field TX_STOMP_RSSI_THRESH */
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__SHIFT                           8
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WIDTH                           8
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MASK                  0x0000ff00U
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field RX_ABORT_RSSI_THRESH */
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__SHIFT                          16
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WIDTH                           8
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MASK                  0x00ff0000U
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))
#define MAC_PCU_XRSTMP__TYPE                                          u_int32_t
#define MAC_PCU_XRSTMP__READ                                        0x00ffff3fU
#define MAC_PCU_XRSTMP__WRITE                                       0x00ffff3fU

#endif /* __MAC_PCU_XRSTMP_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_XRSTMP */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRSTMP__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP1 */
#ifndef __MAC_PCU_SLP1_MACRO__
#define __MAC_PCU_SLP1_MACRO__

/* macros for field ASSUME_DTIM */
#define MAC_PCU_SLP1__ASSUME_DTIM__SHIFT                                     19
#define MAC_PCU_SLP1__ASSUME_DTIM__WIDTH                                      1
#define MAC_PCU_SLP1__ASSUME_DTIM__MASK                             0x00080000U
#define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_SLP1__ASSUME_DTIM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_SLP1__ASSUME_DTIM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field CAB_TIMEOUT */
#define MAC_PCU_SLP1__CAB_TIMEOUT__SHIFT                                     21
#define MAC_PCU_SLP1__CAB_TIMEOUT__WIDTH                                     11
#define MAC_PCU_SLP1__CAB_TIMEOUT__MASK                             0xffe00000U
#define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffe00000U) >> 21)
#define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0xffe00000U)
#define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffe00000U) | (((u_int32_t)(src) <<\
                    21) & 0xffe00000U)
#define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0xffe00000U)))
#define MAC_PCU_SLP1__TYPE                                            u_int32_t
#define MAC_PCU_SLP1__READ                                          0xffe80000U
#define MAC_PCU_SLP1__WRITE                                         0xffe80000U

#endif /* __MAC_PCU_SLP1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP1__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP2 */
#ifndef __MAC_PCU_SLP2_MACRO__
#define __MAC_PCU_SLP2_MACRO__

/* macros for field BEACON_TIMEOUT */
#define MAC_PCU_SLP2__BEACON_TIMEOUT__SHIFT                                  21
#define MAC_PCU_SLP2__BEACON_TIMEOUT__WIDTH                                  11
#define MAC_PCU_SLP2__BEACON_TIMEOUT__MASK                          0xffe00000U
#define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffe00000U) >> 21)
#define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0xffe00000U)
#define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffe00000U) | (((u_int32_t)(src) <<\
                    21) & 0xffe00000U)
#define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0xffe00000U)))
#define MAC_PCU_SLP2__TYPE                                            u_int32_t
#define MAC_PCU_SLP2__READ                                          0xffe00000U
#define MAC_PCU_SLP2__WRITE                                         0xffe00000U

#endif /* __MAC_PCU_SLP2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP2__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_DEFAULT */
#ifndef __MAC_PCU_SELF_GEN_DEFAULT_MACRO__
#define __MAC_PCU_SELF_GEN_DEFAULT_MACRO__

/* macros for field MMSS */
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__SHIFT                                 0
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WIDTH                                 3
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MASK                        0x00000007U
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field CEC */
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__SHIFT                                  3
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WIDTH                                  2
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MASK                         0x00000018U
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000018U) >> 3)
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000018U)
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000018U) | (((u_int32_t)(src) <<\
                    3) & 0x00000018U)
#define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000018U)))

/* macros for field STAGGER_SOUNDING */
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SHIFT                     5
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WIDTH                     1
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MASK            0x00000020U
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define MAC_PCU_SELF_GEN_DEFAULT__TYPE                                u_int32_t
#define MAC_PCU_SELF_GEN_DEFAULT__READ                              0x0000003fU
#define MAC_PCU_SELF_GEN_DEFAULT__WRITE                             0x0000003fU

#endif /* __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_DEFAULT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_DEFAULT__NUM                   1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_L32 */
#ifndef __MAC_PCU_ADDR1_MASK_L32_MACRO__
#define __MAC_PCU_ADDR1_MASK_L32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_ADDR1_MASK_L32__VALUE__SHIFT                                  0
#define MAC_PCU_ADDR1_MASK_L32__VALUE__WIDTH                                 32
#define MAC_PCU_ADDR1_MASK_L32__VALUE__MASK                         0xffffffffU
#define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_ADDR1_MASK_L32__TYPE                                  u_int32_t
#define MAC_PCU_ADDR1_MASK_L32__READ                                0xffffffffU
#define MAC_PCU_ADDR1_MASK_L32__WRITE                               0xffffffffU

#endif /* __MAC_PCU_ADDR1_MASK_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_L32__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_U16 */
#ifndef __MAC_PCU_ADDR1_MASK_U16_MACRO__
#define __MAC_PCU_ADDR1_MASK_U16_MACRO__

/* macros for field VALUE */
#define MAC_PCU_ADDR1_MASK_U16__VALUE__SHIFT                                  0
#define MAC_PCU_ADDR1_MASK_U16__VALUE__WIDTH                                 16
#define MAC_PCU_ADDR1_MASK_U16__VALUE__MASK                         0x0000ffffU
#define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_ADDR1_MASK_U16__TYPE                                  u_int32_t
#define MAC_PCU_ADDR1_MASK_U16__READ                                0x0000ffffU
#define MAC_PCU_ADDR1_MASK_U16__WRITE                               0x0000ffffU

#endif /* __MAC_PCU_ADDR1_MASK_U16_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_U16 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_U16__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TPC */
#ifndef __MAC_PCU_TPC_MACRO__
#define __MAC_PCU_TPC_MACRO__

/* macros for field ACK_PWR */
#define MAC_PCU_TPC__ACK_PWR__SHIFT                                           0
#define MAC_PCU_TPC__ACK_PWR__WIDTH                                           6
#define MAC_PCU_TPC__ACK_PWR__MASK                                  0x0000003fU
#define MAC_PCU_TPC__ACK_PWR__READ(src)          (u_int32_t)(src) & 0x0000003fU
#define MAC_PCU_TPC__ACK_PWR__WRITE(src)       ((u_int32_t)(src) & 0x0000003fU)
#define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field CTS_PWR */
#define MAC_PCU_TPC__CTS_PWR__SHIFT                                           8
#define MAC_PCU_TPC__CTS_PWR__WIDTH                                           6
#define MAC_PCU_TPC__CTS_PWR__MASK                                  0x00003f00U
#define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8)
#define MAC_PCU_TPC__CTS_PWR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field CHIRP_PWR */
#define MAC_PCU_TPC__CHIRP_PWR__SHIFT                                        16
#define MAC_PCU_TPC__CHIRP_PWR__WIDTH                                         6
#define MAC_PCU_TPC__CHIRP_PWR__MASK                                0x003f0000U
#define MAC_PCU_TPC__CHIRP_PWR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field RPT_PWR */
#define MAC_PCU_TPC__RPT_PWR__SHIFT                                          24
#define MAC_PCU_TPC__RPT_PWR__WIDTH                                           6
#define MAC_PCU_TPC__RPT_PWR__MASK                                  0x3f000000U
#define MAC_PCU_TPC__RPT_PWR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define MAC_PCU_TPC__RPT_PWR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define MAC_PCU_TPC__TYPE                                             u_int32_t
#define MAC_PCU_TPC__READ                                           0x3f3f3f3fU
#define MAC_PCU_TPC__WRITE                                          0x3f3f3f3fU

#endif /* __MAC_PCU_TPC_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TPC */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TPC__NUM                                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_FRAME_CNT */
#ifndef __MAC_PCU_TX_FRAME_CNT_MACRO__
#define __MAC_PCU_TX_FRAME_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TX_FRAME_CNT__VALUE__SHIFT                                    0
#define MAC_PCU_TX_FRAME_CNT__VALUE__WIDTH                                   32
#define MAC_PCU_TX_FRAME_CNT__VALUE__MASK                           0xffffffffU
#define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TX_FRAME_CNT__TYPE                                    u_int32_t
#define MAC_PCU_TX_FRAME_CNT__READ                                  0xffffffffU
#define MAC_PCU_TX_FRAME_CNT__WRITE                                 0xffffffffU

#endif /* __MAC_PCU_TX_FRAME_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TX_FRAME_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_FRAME_CNT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FRAME_CNT */
#ifndef __MAC_PCU_RX_FRAME_CNT_MACRO__
#define __MAC_PCU_RX_FRAME_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_RX_FRAME_CNT__VALUE__SHIFT                                    0
#define MAC_PCU_RX_FRAME_CNT__VALUE__WIDTH                                   32
#define MAC_PCU_RX_FRAME_CNT__VALUE__MASK                           0xffffffffU
#define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_RX_FRAME_CNT__TYPE                                    u_int32_t
#define MAC_PCU_RX_FRAME_CNT__READ                                  0xffffffffU
#define MAC_PCU_RX_FRAME_CNT__WRITE                                 0xffffffffU

#endif /* __MAC_PCU_RX_FRAME_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RX_FRAME_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FRAME_CNT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_CNT */
#ifndef __MAC_PCU_RX_CLEAR_CNT_MACRO__
#define __MAC_PCU_RX_CLEAR_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_RX_CLEAR_CNT__VALUE__SHIFT                                    0
#define MAC_PCU_RX_CLEAR_CNT__VALUE__WIDTH                                   32
#define MAC_PCU_RX_CLEAR_CNT__VALUE__MASK                           0xffffffffU
#define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_RX_CLEAR_CNT__TYPE                                    u_int32_t
#define MAC_PCU_RX_CLEAR_CNT__READ                                  0xffffffffU
#define MAC_PCU_RX_CLEAR_CNT__WRITE                                 0xffffffffU

#endif /* __MAC_PCU_RX_CLEAR_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_CNT__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_CYCLE_CNT */
#ifndef __MAC_PCU_CYCLE_CNT_MACRO__
#define __MAC_PCU_CYCLE_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_CYCLE_CNT__VALUE__SHIFT                                       0
#define MAC_PCU_CYCLE_CNT__VALUE__WIDTH                                      32
#define MAC_PCU_CYCLE_CNT__VALUE__MASK                              0xffffffffU
#define MAC_PCU_CYCLE_CNT__VALUE__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_CYCLE_CNT__TYPE                                       u_int32_t
#define MAC_PCU_CYCLE_CNT__READ                                     0xffffffffU
#define MAC_PCU_CYCLE_CNT__WRITE                                    0xffffffffU

#endif /* __MAC_PCU_CYCLE_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_CYCLE_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_CYCLE_CNT__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_1 */
#ifndef __MAC_PCU_QUIET_TIME_1_MACRO__
#define __MAC_PCU_QUIET_TIME_1_MACRO__

/* macros for field ACK_CTS_ENABLE */
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SHIFT                          17
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WIDTH                           1
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MASK                  0x00020000U
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)
#define MAC_PCU_QUIET_TIME_1__TYPE                                    u_int32_t
#define MAC_PCU_QUIET_TIME_1__READ                                  0x00020000U
#define MAC_PCU_QUIET_TIME_1__WRITE                                 0x00020000U

#endif /* __MAC_PCU_QUIET_TIME_1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_1__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_2 */
#ifndef __MAC_PCU_QUIET_TIME_2_MACRO__
#define __MAC_PCU_QUIET_TIME_2_MACRO__

/* macros for field DURATION */
#define MAC_PCU_QUIET_TIME_2__DURATION__SHIFT                                16
#define MAC_PCU_QUIET_TIME_2__DURATION__WIDTH                                16
#define MAC_PCU_QUIET_TIME_2__DURATION__MASK                        0xffff0000U
#define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_QUIET_TIME_2__TYPE                                    u_int32_t
#define MAC_PCU_QUIET_TIME_2__READ                                  0xffff0000U
#define MAC_PCU_QUIET_TIME_2__WRITE                                 0xffff0000U

#endif /* __MAC_PCU_QUIET_TIME_2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_2__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_QOS_NO_ACK */
#ifndef __MAC_PCU_QOS_NO_ACK_MACRO__
#define __MAC_PCU_QOS_NO_ACK_MACRO__

/* macros for field TWO_BIT_VALUES */
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__SHIFT                             0
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WIDTH                             4
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MASK                    0x0000000fU
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field BIT_OFFSET */
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__SHIFT                                 4
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WIDTH                                 3
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MASK                        0x00000070U
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000070U) >> 4)
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000070U)
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((u_int32_t)(src) <<\
                    4) & 0x00000070U)
#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field BYTE_OFFSET */
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__SHIFT                                7
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WIDTH                                2
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MASK                       0x00000180U
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000180U) >> 7)
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000180U)
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000180U) | (((u_int32_t)(src) <<\
                    7) & 0x00000180U)
#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000180U)))
#define MAC_PCU_QOS_NO_ACK__TYPE                                      u_int32_t
#define MAC_PCU_QOS_NO_ACK__READ                                    0x000001ffU
#define MAC_PCU_QOS_NO_ACK__WRITE                                   0x000001ffU

#endif /* __MAC_PCU_QOS_NO_ACK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_QOS_NO_ACK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_QOS_NO_ACK__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK */
#ifndef __MAC_PCU_PHY_ERROR_MASK_MACRO__
#define __MAC_PCU_PHY_ERROR_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERROR_MASK__VALUE__SHIFT                                  0
#define MAC_PCU_PHY_ERROR_MASK__VALUE__WIDTH                                 32
#define MAC_PCU_PHY_ERROR_MASK__VALUE__MASK                         0xffffffffU
#define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_PHY_ERROR_MASK__TYPE                                  u_int32_t
#define MAC_PCU_PHY_ERROR_MASK__READ                                0xffffffffU
#define MAC_PCU_PHY_ERROR_MASK__WRITE                               0xffffffffU

#endif /* __MAC_PCU_PHY_ERROR_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRLAT */
#ifndef __MAC_PCU_XRLAT_MACRO__
#define __MAC_PCU_XRLAT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_XRLAT__VALUE__SHIFT                                           0
#define MAC_PCU_XRLAT__VALUE__WIDTH                                          12
#define MAC_PCU_XRLAT__VALUE__MASK                                  0x00000fffU
#define MAC_PCU_XRLAT__VALUE__READ(src)          (u_int32_t)(src) & 0x00000fffU
#define MAC_PCU_XRLAT__VALUE__WRITE(src)       ((u_int32_t)(src) & 0x00000fffU)
#define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define MAC_PCU_XRLAT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))
#define MAC_PCU_XRLAT__TYPE                                           u_int32_t
#define MAC_PCU_XRLAT__READ                                         0x00000fffU
#define MAC_PCU_XRLAT__WRITE                                        0x00000fffU

#endif /* __MAC_PCU_XRLAT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_XRLAT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRLAT__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RXBUF */
#ifndef __MAC_PCU_RXBUF_MACRO__
#define __MAC_PCU_RXBUF_MACRO__

/* macros for field HIGH_PRIORITY_THRSHD */
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__SHIFT                            0
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WIDTH                           11
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MASK                   0x000007ffU
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000007ffU
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000007ffU)
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((u_int32_t)(src) &\
                    0x000007ffU)
#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field REG_RD_ENABLE */
#define MAC_PCU_RXBUF__REG_RD_ENABLE__SHIFT                                  11
#define MAC_PCU_RXBUF__REG_RD_ENABLE__WIDTH                                   1
#define MAC_PCU_RXBUF__REG_RD_ENABLE__MASK                          0x00000800U
#define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_RXBUF__REG_RD_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_RXBUF__REG_RD_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)
#define MAC_PCU_RXBUF__TYPE                                           u_int32_t
#define MAC_PCU_RXBUF__READ                                         0x00000fffU
#define MAC_PCU_RXBUF__WRITE                                        0x00000fffU

#endif /* __MAC_PCU_RXBUF_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RXBUF */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RXBUF__NUM                              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_CONTROL */
#ifndef __MAC_PCU_MIC_QOS_CONTROL_MACRO__
#define __MAC_PCU_MIC_QOS_CONTROL_MACRO__

/* macros for field VALUE_0 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__SHIFT                               0
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MASK                      0x00000003U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field VALUE_1 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__SHIFT                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MASK                      0x0000000cU
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field VALUE_2 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__SHIFT                               4
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MASK                      0x00000030U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field VALUE_3 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__SHIFT                               6
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MASK                      0x000000c0U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field VALUE_4 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__SHIFT                               8
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MASK                      0x00000300U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field VALUE_5 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__SHIFT                              10
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MASK                      0x00000c00U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))

/* macros for field VALUE_6 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__SHIFT                              12
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MASK                      0x00003000U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003000U) >> 12)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00003000U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((u_int32_t)(src) <<\
                    12) & 0x00003000U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field VALUE_7 */
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__SHIFT                              14
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WIDTH                               2
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MASK                      0x0000c000U
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000c000U) >> 14)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0000c000U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0000c000U)
#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field ENABLE */
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SHIFT                               16
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WIDTH                                1
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MASK                       0x00010000U
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)
#define MAC_PCU_MIC_QOS_CONTROL__TYPE                                 u_int32_t
#define MAC_PCU_MIC_QOS_CONTROL__READ                               0x0001ffffU
#define MAC_PCU_MIC_QOS_CONTROL__WRITE                              0x0001ffffU

#endif /* __MAC_PCU_MIC_QOS_CONTROL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_CONTROL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_CONTROL__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_SELECT */
#ifndef __MAC_PCU_MIC_QOS_SELECT_MACRO__
#define __MAC_PCU_MIC_QOS_SELECT_MACRO__

/* macros for field VALUE_0 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__SHIFT                                0
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MASK                       0x0000000fU
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field VALUE_1 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__SHIFT                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MASK                       0x000000f0U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field VALUE_2 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__SHIFT                                8
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MASK                       0x00000f00U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field VALUE_3 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__SHIFT                               12
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MASK                       0x0000f000U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field VALUE_4 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__SHIFT                               16
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MASK                       0x000f0000U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field VALUE_5 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__SHIFT                               20
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MASK                       0x00f00000U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00f00000U) >> 20)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00f00000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x00f00000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field VALUE_6 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__SHIFT                               24
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MASK                       0x0f000000U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f000000U) >> 24)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x0f000000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x0f000000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field VALUE_7 */
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__SHIFT                               28
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WIDTH                                4
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MASK                       0xf0000000U
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf0000000U) >> 28)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0xf0000000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((u_int32_t)(src) <<\
                    28) & 0xf0000000U)
#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define MAC_PCU_MIC_QOS_SELECT__TYPE                                  u_int32_t
#define MAC_PCU_MIC_QOS_SELECT__READ                                0xffffffffU
#define MAC_PCU_MIC_QOS_SELECT__WRITE                               0xffffffffU

#endif /* __MAC_PCU_MIC_QOS_SELECT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_SELECT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_SELECT__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE */
#ifndef __MAC_PCU_MISC_MODE_MACRO__
#define __MAC_PCU_MISC_MODE_MACRO__

/* macros for field BSSID_MATCH_FORCE */
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SHIFT                           0
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WIDTH                           1
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MASK                  0x00000001U
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field DEBUG_MODE_AD */
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SHIFT                               1
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WIDTH                               1
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MASK                      0x00000002U
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field MIC_NEW_LOCATION_ENABLE */
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SHIFT                     2
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WIDTH                     1
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MASK            0x00000004U
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field TX_ADD_TSF */
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SHIFT                                  3
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WIDTH                                  1
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MASK                         0x00000008U
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_MISC_MODE__TX_ADD_TSF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field CCK_SIFS_MODE */
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SHIFT                               4
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WIDTH                               1
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MASK                      0x00000010U
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field RXSM2SVD_PRE_RST */
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SHIFT                            5
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WIDTH                            1
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MASK                   0x00000020U
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field RCV_DELAY_SOUNDING_IM_TXBF */
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SHIFT                  6
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WIDTH                  1
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MASK         0x00000040U
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field DEBUG_MODE_BA_BITMAP */
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SHIFT                        9
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WIDTH                        1
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MASK               0x00000200U
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field DEBUG_MODE_SIFS */
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SHIFT                            10
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WIDTH                             1
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MASK                    0x00000400U
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field KC_RX_ANT_UPDATE */
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SHIFT                           11
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WIDTH                            1
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MASK                   0x00000800U
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field TXOP_TBTT_LIMIT_ENABLE */
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SHIFT                     12
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WIDTH                      1
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MASK             0x00001000U
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field MISS_BEACON_IN_SLEEP */
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SHIFT                       14
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WIDTH                        1
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MASK               0x00004000U
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field FORCE_QUIET_COLLISION */
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SHIFT                      18
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WIDTH                       1
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MASK              0x00040000U
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field BT_ANT_PREVENTS_RX */
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SHIFT                         20
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WIDTH                          1
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MASK                 0x00100000U
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field TBTT_PROTECT */
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SHIFT                               21
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WIDTH                                1
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MASK                       0x00200000U
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_MISC_MODE__TBTT_PROTECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field HCF_POLL_CANCELS_NAV */
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SHIFT                       22
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WIDTH                        1
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MASK               0x00400000U
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field RX_HCF_POLL_ENABLE */
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SHIFT                         23
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WIDTH                          1
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MASK                 0x00800000U
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field CLEAR_VMF */
#define MAC_PCU_MISC_MODE__CLEAR_VMF__SHIFT                                  24
#define MAC_PCU_MISC_MODE__CLEAR_VMF__WIDTH                                   1
#define MAC_PCU_MISC_MODE__CLEAR_VMF__MASK                          0x01000000U
#define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_MISC_MODE__CLEAR_VMF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_MISC_MODE__CLEAR_VMF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field CLEAR_FIRST_HCF */
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SHIFT                            25
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WIDTH                             1
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MASK                    0x02000000U
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field CLEAR_BA_VALID */
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SHIFT                             26
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WIDTH                              1
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MASK                     0x04000000U
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field SEL_EVM */
#define MAC_PCU_MISC_MODE__SEL_EVM__SHIFT                                    27
#define MAC_PCU_MISC_MODE__SEL_EVM__WIDTH                                     1
#define MAC_PCU_MISC_MODE__SEL_EVM__MASK                            0x08000000U
#define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define MAC_PCU_MISC_MODE__SEL_EVM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define MAC_PCU_MISC_MODE__SEL_EVM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field ALWAYS_PERFORM_KEY_SEARCH */
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SHIFT                  28
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WIDTH                   1
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MASK          0x10000000U
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field USE_EOP_PTR_FOR_DMA_WR */
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SHIFT                     29
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WIDTH                      1
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MASK             0x20000000U
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field DEBUG_MODE */
#define MAC_PCU_MISC_MODE__DEBUG_MODE__SHIFT                                 30
#define MAC_PCU_MISC_MODE__DEBUG_MODE__WIDTH                                  2
#define MAC_PCU_MISC_MODE__DEBUG_MODE__MASK                         0xc0000000U
#define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define MAC_PCU_MISC_MODE__TYPE                                       u_int32_t
#define MAC_PCU_MISC_MODE__READ                                     0xfff45e7fU
#define MAC_PCU_MISC_MODE__WRITE                                    0xfff45e7fU

#endif /* __MAC_PCU_MISC_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_OFDM_CNT */
#ifndef __MAC_PCU_FILTER_OFDM_CNT_MACRO__
#define __MAC_PCU_FILTER_OFDM_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__SHIFT                                 0
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WIDTH                                24
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MASK                        0x00ffffffU
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00ffffffU
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))
#define MAC_PCU_FILTER_OFDM_CNT__TYPE                                 u_int32_t
#define MAC_PCU_FILTER_OFDM_CNT__READ                               0x00ffffffU
#define MAC_PCU_FILTER_OFDM_CNT__WRITE                              0x00ffffffU

#endif /* __MAC_PCU_FILTER_OFDM_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_OFDM_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_OFDM_CNT__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_CCK_CNT */
#ifndef __MAC_PCU_FILTER_CCK_CNT_MACRO__
#define __MAC_PCU_FILTER_CCK_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_FILTER_CCK_CNT__VALUE__SHIFT                                  0
#define MAC_PCU_FILTER_CCK_CNT__VALUE__WIDTH                                 24
#define MAC_PCU_FILTER_CCK_CNT__VALUE__MASK                         0x00ffffffU
#define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
#define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))
#define MAC_PCU_FILTER_CCK_CNT__TYPE                                  u_int32_t
#define MAC_PCU_FILTER_CCK_CNT__READ                                0x00ffffffU
#define MAC_PCU_FILTER_CCK_CNT__WRITE                               0x00ffffffU

#endif /* __MAC_PCU_FILTER_CCK_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_CCK_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_CCK_CNT__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1 */
#ifndef __MAC_PCU_PHY_ERR_CNT_1_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_1_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__SHIFT                                   0
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WIDTH                                  24
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MASK                          0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src)  (u_int32_t)(src) & 0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))
#define MAC_PCU_PHY_ERR_CNT_1__TYPE                                   u_int32_t
#define MAC_PCU_PHY_ERR_CNT_1__READ                                 0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_1__WRITE                                0x00ffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1__NUM                      1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1_MASK */
#ifndef __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__SHIFT                              0
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WIDTH                             32
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MASK                     0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_PHY_ERR_CNT_1_MASK__TYPE                              u_int32_t
#define MAC_PCU_PHY_ERR_CNT_1_MASK__READ                            0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_1_MASK__WRITE                           0xffffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1_MASK__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2 */
#ifndef __MAC_PCU_PHY_ERR_CNT_2_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_2_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__SHIFT                                   0
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WIDTH                                  24
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MASK                          0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src)  (u_int32_t)(src) & 0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))
#define MAC_PCU_PHY_ERR_CNT_2__TYPE                                   u_int32_t
#define MAC_PCU_PHY_ERR_CNT_2__READ                                 0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_2__WRITE                                0x00ffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2__NUM                      1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2_MASK */
#ifndef __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__SHIFT                              0
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WIDTH                             32
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MASK                     0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_PHY_ERR_CNT_2_MASK__TYPE                              u_int32_t
#define MAC_PCU_PHY_ERR_CNT_2_MASK__READ                            0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_2_MASK__WRITE                           0xffffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2_MASK__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_THRESHOLD */
#ifndef __MAC_PCU_TSF_THRESHOLD_MACRO__
#define __MAC_PCU_TSF_THRESHOLD_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TSF_THRESHOLD__VALUE__SHIFT                                   0
#define MAC_PCU_TSF_THRESHOLD__VALUE__WIDTH                                  16
#define MAC_PCU_TSF_THRESHOLD__VALUE__MASK                          0x0000ffffU
#define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src)  (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_TSF_THRESHOLD__TYPE                                   u_int32_t
#define MAC_PCU_TSF_THRESHOLD__READ                                 0x0000ffffU
#define MAC_PCU_TSF_THRESHOLD__WRITE                                0x0000ffffU

#endif /* __MAC_PCU_TSF_THRESHOLD_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TSF_THRESHOLD */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_THRESHOLD__NUM                      1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE4 */
#ifndef __MAC_PCU_MISC_MODE4_MACRO__
#define __MAC_PCU_MISC_MODE4_MACRO__

/* macros for field EV_85395_FIX_DISABLE */
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SHIFT                       0
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MASK              0x00000001U
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field MIN_AVAILABLE_FIFO_DEPTH */
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__SHIFT                   1
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WIDTH                  12
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MASK          0x00001ffeU
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001ffeU) >> 1)
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00001ffeU)
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001ffeU) | (((u_int32_t)(src) <<\
                    1) & 0x00001ffeU)
#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00001ffeU)))

/* macros for field EV_83864_FIX_ENABLE */
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SHIFT                       13
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WIDTH                        1
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MASK               0x00002000U
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)
#define MAC_PCU_MISC_MODE4__TYPE                                      u_int32_t
#define MAC_PCU_MISC_MODE4__READ                                    0x00003fffU
#define MAC_PCU_MISC_MODE4__WRITE                                   0x00003fffU

#endif /* __MAC_PCU_MISC_MODE4_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE4 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE4__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_EIFS_MASK */
#ifndef __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__
#define __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__SHIFT                             0
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WIDTH                            32
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MASK                    0xffffffffU
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_PHY_ERROR_EIFS_MASK__TYPE                             u_int32_t
#define MAC_PCU_PHY_ERROR_EIFS_MASK__READ                           0xffffffffU
#define MAC_PCU_PHY_ERROR_EIFS_MASK__WRITE                          0xffffffffU

#endif /* __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_EIFS_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_EIFS_MASK__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3 */
#ifndef __MAC_PCU_PHY_ERR_CNT_3_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_3_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__SHIFT                                   0
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WIDTH                                  24
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MASK                          0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src)  (u_int32_t)(src) & 0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))
#define MAC_PCU_PHY_ERR_CNT_3__TYPE                                   u_int32_t
#define MAC_PCU_PHY_ERR_CNT_3__READ                                 0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_3__WRITE                                0x00ffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3__NUM                      1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3_MASK */
#ifndef __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__SHIFT                              0
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WIDTH                             32
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MASK                     0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_PHY_ERR_CNT_3_MASK__TYPE                              u_int32_t
#define MAC_PCU_PHY_ERR_CNT_3_MASK__READ                            0xffffffffU
#define MAC_PCU_PHY_ERR_CNT_3_MASK__WRITE                           0xffffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3_MASK__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE */
#ifndef __MAC_PCU_BLUETOOTH_MODE_MACRO__
#define __MAC_PCU_BLUETOOTH_MODE_MACRO__

/* macros for field TIME_EXTEND */
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__SHIFT                            0
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WIDTH                            8
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MASK                   0x000000ffU
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field TX_STATE_EXTEND */
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SHIFT                        8
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WIDTH                        1
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MASK               0x00000100U
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field TX_FRAME_EXTEND */
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SHIFT                        9
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WIDTH                        1
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MASK               0x00000200U
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field MODE */
#define MAC_PCU_BLUETOOTH_MODE__MODE__SHIFT                                  10
#define MAC_PCU_BLUETOOTH_MODE__MODE__WIDTH                                   2
#define MAC_PCU_BLUETOOTH_MODE__MODE__MASK                          0x00000c00U
#define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))

/* macros for field QUIET */
#define MAC_PCU_BLUETOOTH_MODE__QUIET__SHIFT                                 12
#define MAC_PCU_BLUETOOTH_MODE__QUIET__WIDTH                                  1
#define MAC_PCU_BLUETOOTH_MODE__QUIET__MASK                         0x00001000U
#define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_BLUETOOTH_MODE__QUIET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_BLUETOOTH_MODE__QUIET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field QCU_THRESH */
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__SHIFT                            13
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WIDTH                             4
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MASK                    0x0001e000U
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001e000U) >> 13)
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0001e000U)
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0001e000U)
#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0001e000U)))

/* macros for field RX_CLEAR_POLARITY */
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SHIFT                     17
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WIDTH                      1
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MASK             0x00020000U
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field PRIORITY_TIME */
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__SHIFT                         18
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WIDTH                          6
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MASK                 0x00fc0000U
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00fc0000U)
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field FIRST_SLOT_TIME */
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__SHIFT                       24
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WIDTH                        8
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MASK               0xff000000U
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_BLUETOOTH_MODE__TYPE                                  u_int32_t
#define MAC_PCU_BLUETOOTH_MODE__READ                                0xffffffffU
#define MAC_PCU_BLUETOOTH_MODE__WRITE                               0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */
#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__
#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__SHIFT                           0
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WIDTH                          32
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MASK                  0xffffffffU
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__TYPE                           u_int32_t
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__READ                         0xffffffffU
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__WRITE                        0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS0__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_HCF_TIMEOUT */
#ifndef __MAC_PCU_HCF_TIMEOUT_MACRO__
#define __MAC_PCU_HCF_TIMEOUT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_HCF_TIMEOUT__VALUE__SHIFT                                     0
#define MAC_PCU_HCF_TIMEOUT__VALUE__WIDTH                                    16
#define MAC_PCU_HCF_TIMEOUT__VALUE__MASK                            0x0000ffffU
#define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src)    (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_HCF_TIMEOUT__TYPE                                     u_int32_t
#define MAC_PCU_HCF_TIMEOUT__READ                                   0x0000ffffU
#define MAC_PCU_HCF_TIMEOUT__WRITE                                  0x0000ffffU

#endif /* __MAC_PCU_HCF_TIMEOUT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_HCF_TIMEOUT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_HCF_TIMEOUT__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE2 */
#ifndef __MAC_PCU_BLUETOOTH_MODE2_MACRO__
#define __MAC_PCU_BLUETOOTH_MODE2_MACRO__

/* macros for field BCN_MISS_THRESH */
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__SHIFT                       0
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WIDTH                       8
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MASK              0x000000ffU
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field BCN_MISS_CNT */
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__SHIFT                          8
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__WIDTH                          8
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__MASK                 0x0000ff00U
#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field HOLD_RX_CLEAR */
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SHIFT                        16
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WIDTH                         1
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MASK                0x00010000U
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field SLEEP_ALLOW_BT_ACCESS */
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SHIFT                17
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WIDTH                 1
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MASK        0x00020000U
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field PROTECT_BT_AFTER_WAKEUP */
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SHIFT              19
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WIDTH               1
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MASK      0x00080000U
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field DISABLE_BT_ANT */
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SHIFT                       20
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WIDTH                        1
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MASK               0x00100000U
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field QUIET_2_WIRE */
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SHIFT                         21
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WIDTH                          1
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MASK                 0x00200000U
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field WL_ACTIVE_MODE */
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__SHIFT                       22
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WIDTH                        2
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MASK               0x00c00000U
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00c00000U) >> 22)
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00c00000U)
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x00c00000U)
#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00c00000U)))

/* macros for field WL_TXRX_SEPARATE */
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SHIFT                     24
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WIDTH                      1
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MASK             0x01000000U
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field RS_DISCARD_EXTEND */
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SHIFT                    25
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WIDTH                     1
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MASK            0x02000000U
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field TSF_BT_ACTIVE_CTRL */
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__SHIFT                   26
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WIDTH                    2
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MASK           0x0c000000U
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0c000000U) >> 26)
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x0c000000U)
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x0c000000U)
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x0c000000U)))

/* macros for field TSF_BT_PRIORITY_CTRL */
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__SHIFT                 28
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WIDTH                  2
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MASK         0x30000000U
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x30000000U) >> 28)
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x30000000U)
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((u_int32_t)(src) <<\
                    28) & 0x30000000U)
#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field INTERRUPT_ENABLE */
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SHIFT                     30
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WIDTH                      1
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MASK             0x40000000U
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field PHY_ERR_BT_COLL_ENABLE */
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SHIFT               31
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WIDTH                1
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MASK       0x80000000U
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define MAC_PCU_BLUETOOTH_MODE2__TYPE                                 u_int32_t
#define MAC_PCU_BLUETOOTH_MODE2__READ                               0xfffbffffU
#define MAC_PCU_BLUETOOTH_MODE2__WRITE                              0xfffbffffU

#endif /* __MAC_PCU_BLUETOOTH_MODE2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE2__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2 */
#ifndef __MAC_PCU_GENERIC_TIMERS2_MACRO__
#define __MAC_PCU_GENERIC_TIMERS2_MACRO__

/* macros for field DATA */
#define MAC_PCU_GENERIC_TIMERS2__DATA__SHIFT                                  0
#define MAC_PCU_GENERIC_TIMERS2__DATA__WIDTH                                 32
#define MAC_PCU_GENERIC_TIMERS2__DATA__MASK                         0xffffffffU
#define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_GENERIC_TIMERS2__TYPE                                 u_int32_t
#define MAC_PCU_GENERIC_TIMERS2__READ                               0xffffffffU
#define MAC_PCU_GENERIC_TIMERS2__WRITE                              0xffffffffU

#endif /* __MAC_PCU_GENERIC_TIMERS2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2__NUM                   16

/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2_MODE */
#ifndef __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__
#define __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__

/* macros for field ENABLE */
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__SHIFT                           0
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WIDTH                           8
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MASK                  0x000000ffU
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field OVERFLOW_INDEX */
#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__SHIFT                   8
#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__WIDTH                   3
#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__MASK          0x00000700U
#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)
#define MAC_PCU_GENERIC_TIMERS2_MODE__TYPE                            u_int32_t
#define MAC_PCU_GENERIC_TIMERS2_MODE__READ                          0x000007ffU
#define MAC_PCU_GENERIC_TIMERS2_MODE__WRITE                         0x000007ffU

#endif /* __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2_MODE__NUM               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */
#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__
#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__SHIFT                           0
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WIDTH                          32
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MASK                  0xffffffffU
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__TYPE                           u_int32_t
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__READ                         0xffffffffU
#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__WRITE                        0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS1__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */
#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__
#define __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__SHIFT                         0
#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__WIDTH                        32
#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__MASK                0xffffffffU
#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__TYPE                         u_int32_t
#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__READ                       0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__NUM            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */
#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__
#define __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__SHIFT                       0
#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__WIDTH                      32
#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__MASK              0xffffffffU
#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__TYPE                       u_int32_t
#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__READ                     0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__NUM          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXSIFS */
#ifndef __MAC_PCU_TXSIFS_MACRO__
#define __MAC_PCU_TXSIFS_MACRO__

/* macros for field SIFS_TIME */
#define MAC_PCU_TXSIFS__SIFS_TIME__SHIFT                                      0
#define MAC_PCU_TXSIFS__SIFS_TIME__WIDTH                                      8
#define MAC_PCU_TXSIFS__SIFS_TIME__MASK                             0x000000ffU
#define MAC_PCU_TXSIFS__SIFS_TIME__READ(src)     (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field TX_LATENCY */
#define MAC_PCU_TXSIFS__TX_LATENCY__SHIFT                                     8
#define MAC_PCU_TXSIFS__TX_LATENCY__WIDTH                                     4
#define MAC_PCU_TXSIFS__TX_LATENCY__MASK                            0x00000f00U
#define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field ACK_SHIFT */
#define MAC_PCU_TXSIFS__ACK_SHIFT__SHIFT                                     12
#define MAC_PCU_TXSIFS__ACK_SHIFT__WIDTH                                      3
#define MAC_PCU_TXSIFS__ACK_SHIFT__MASK                             0x00007000U
#define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007000U) >> 12)
#define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00007000U)
#define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00007000U)))
#define MAC_PCU_TXSIFS__TYPE                                          u_int32_t
#define MAC_PCU_TXSIFS__READ                                        0x00007fffU
#define MAC_PCU_TXSIFS__WRITE                                       0x00007fffU

#endif /* __MAC_PCU_TXSIFS_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXSIFS */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXSIFS__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE3 */
#ifndef __MAC_PCU_BLUETOOTH_MODE3_MACRO__
#define __MAC_PCU_BLUETOOTH_MODE3_MACRO__

/* macros for field WL_ACTIVE_TIME */
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__SHIFT                        0
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WIDTH                        8
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MASK               0x000000ffU
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field WL_QC_TIME */
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__SHIFT                            8
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WIDTH                            8
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MASK                   0x0000ff00U
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field ALLOW_CONCURRENT_ACCESS */
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__SHIFT              16
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WIDTH               4
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MASK      0x000f0000U
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field AGC_SATURATION_CNT_ENABLE */
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SHIFT            20
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WIDTH             1
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MASK    0x00100000U
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)
#define MAC_PCU_BLUETOOTH_MODE3__TYPE                                 u_int32_t
#define MAC_PCU_BLUETOOTH_MODE3__READ                               0x001fffffU
#define MAC_PCU_BLUETOOTH_MODE3__WRITE                              0x001fffffU

#endif /* __MAC_PCU_BLUETOOTH_MODE3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE3__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_X */
#ifndef __MAC_PCU_TXOP_X_MACRO__
#define __MAC_PCU_TXOP_X_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TXOP_X__VALUE__SHIFT                                          0
#define MAC_PCU_TXOP_X__VALUE__WIDTH                                          8
#define MAC_PCU_TXOP_X__VALUE__MASK                                 0x000000ffU
#define MAC_PCU_TXOP_X__VALUE__READ(src)         (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_TXOP_X__VALUE__WRITE(src)      ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))
#define MAC_PCU_TXOP_X__TYPE                                          u_int32_t
#define MAC_PCU_TXOP_X__READ                                        0x000000ffU
#define MAC_PCU_TXOP_X__WRITE                                       0x000000ffU

#endif /* __MAC_PCU_TXOP_X_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_X */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_X__NUM                             1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_0_3 */
#ifndef __MAC_PCU_TXOP_0_3_MACRO__
#define __MAC_PCU_TXOP_0_3_MACRO__

/* macros for field VALUE_0 */
#define MAC_PCU_TXOP_0_3__VALUE_0__SHIFT                                      0
#define MAC_PCU_TXOP_0_3__VALUE_0__WIDTH                                      8
#define MAC_PCU_TXOP_0_3__VALUE_0__MASK                             0x000000ffU
#define MAC_PCU_TXOP_0_3__VALUE_0__READ(src)     (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field VALUE_1 */
#define MAC_PCU_TXOP_0_3__VALUE_1__SHIFT                                      8
#define MAC_PCU_TXOP_0_3__VALUE_1__WIDTH                                      8
#define MAC_PCU_TXOP_0_3__VALUE_1__MASK                             0x0000ff00U
#define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field VALUE_2 */
#define MAC_PCU_TXOP_0_3__VALUE_2__SHIFT                                     16
#define MAC_PCU_TXOP_0_3__VALUE_2__WIDTH                                      8
#define MAC_PCU_TXOP_0_3__VALUE_2__MASK                             0x00ff0000U
#define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field VALUE_3 */
#define MAC_PCU_TXOP_0_3__VALUE_3__SHIFT                                     24
#define MAC_PCU_TXOP_0_3__VALUE_3__WIDTH                                      8
#define MAC_PCU_TXOP_0_3__VALUE_3__MASK                             0xff000000U
#define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_TXOP_0_3__TYPE                                        u_int32_t
#define MAC_PCU_TXOP_0_3__READ                                      0xffffffffU
#define MAC_PCU_TXOP_0_3__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TXOP_0_3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_0_3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_0_3__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_4_7 */
#ifndef __MAC_PCU_TXOP_4_7_MACRO__
#define __MAC_PCU_TXOP_4_7_MACRO__

/* macros for field VALUE_4 */
#define MAC_PCU_TXOP_4_7__VALUE_4__SHIFT                                      0
#define MAC_PCU_TXOP_4_7__VALUE_4__WIDTH                                      8
#define MAC_PCU_TXOP_4_7__VALUE_4__MASK                             0x000000ffU
#define MAC_PCU_TXOP_4_7__VALUE_4__READ(src)     (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field VALUE_5 */
#define MAC_PCU_TXOP_4_7__VALUE_5__SHIFT                                      8
#define MAC_PCU_TXOP_4_7__VALUE_5__WIDTH                                      8
#define MAC_PCU_TXOP_4_7__VALUE_5__MASK                             0x0000ff00U
#define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field VALUE_6 */
#define MAC_PCU_TXOP_4_7__VALUE_6__SHIFT                                     16
#define MAC_PCU_TXOP_4_7__VALUE_6__WIDTH                                      8
#define MAC_PCU_TXOP_4_7__VALUE_6__MASK                             0x00ff0000U
#define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field VALUE_7 */
#define MAC_PCU_TXOP_4_7__VALUE_7__SHIFT                                     24
#define MAC_PCU_TXOP_4_7__VALUE_7__WIDTH                                      8
#define MAC_PCU_TXOP_4_7__VALUE_7__MASK                             0xff000000U
#define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_TXOP_4_7__TYPE                                        u_int32_t
#define MAC_PCU_TXOP_4_7__READ                                      0xffffffffU
#define MAC_PCU_TXOP_4_7__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TXOP_4_7_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_4_7 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_4_7__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_8_11 */
#ifndef __MAC_PCU_TXOP_8_11_MACRO__
#define __MAC_PCU_TXOP_8_11_MACRO__

/* macros for field VALUE_8 */
#define MAC_PCU_TXOP_8_11__VALUE_8__SHIFT                                     0
#define MAC_PCU_TXOP_8_11__VALUE_8__WIDTH                                     8
#define MAC_PCU_TXOP_8_11__VALUE_8__MASK                            0x000000ffU
#define MAC_PCU_TXOP_8_11__VALUE_8__READ(src)    (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field VALUE_9 */
#define MAC_PCU_TXOP_8_11__VALUE_9__SHIFT                                     8
#define MAC_PCU_TXOP_8_11__VALUE_9__WIDTH                                     8
#define MAC_PCU_TXOP_8_11__VALUE_9__MASK                            0x0000ff00U
#define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field VALUE_10 */
#define MAC_PCU_TXOP_8_11__VALUE_10__SHIFT                                   16
#define MAC_PCU_TXOP_8_11__VALUE_10__WIDTH                                    8
#define MAC_PCU_TXOP_8_11__VALUE_10__MASK                           0x00ff0000U
#define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field VALUE_11 */
#define MAC_PCU_TXOP_8_11__VALUE_11__SHIFT                                   24
#define MAC_PCU_TXOP_8_11__VALUE_11__WIDTH                                    8
#define MAC_PCU_TXOP_8_11__VALUE_11__MASK                           0xff000000U
#define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_TXOP_8_11__TYPE                                       u_int32_t
#define MAC_PCU_TXOP_8_11__READ                                     0xffffffffU
#define MAC_PCU_TXOP_8_11__WRITE                                    0xffffffffU

#endif /* __MAC_PCU_TXOP_8_11_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_8_11 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_8_11__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_12_15 */
#ifndef __MAC_PCU_TXOP_12_15_MACRO__
#define __MAC_PCU_TXOP_12_15_MACRO__

/* macros for field VALUE_12 */
#define MAC_PCU_TXOP_12_15__VALUE_12__SHIFT                                   0
#define MAC_PCU_TXOP_12_15__VALUE_12__WIDTH                                   8
#define MAC_PCU_TXOP_12_15__VALUE_12__MASK                          0x000000ffU
#define MAC_PCU_TXOP_12_15__VALUE_12__READ(src)  (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field VALUE_13 */
#define MAC_PCU_TXOP_12_15__VALUE_13__SHIFT                                   8
#define MAC_PCU_TXOP_12_15__VALUE_13__WIDTH                                   8
#define MAC_PCU_TXOP_12_15__VALUE_13__MASK                          0x0000ff00U
#define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field VALUE_14 */
#define MAC_PCU_TXOP_12_15__VALUE_14__SHIFT                                  16
#define MAC_PCU_TXOP_12_15__VALUE_14__WIDTH                                   8
#define MAC_PCU_TXOP_12_15__VALUE_14__MASK                          0x00ff0000U
#define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field VALUE_15 */
#define MAC_PCU_TXOP_12_15__VALUE_15__SHIFT                                  24
#define MAC_PCU_TXOP_12_15__VALUE_15__WIDTH                                   8
#define MAC_PCU_TXOP_12_15__VALUE_15__MASK                          0xff000000U
#define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_TXOP_12_15__TYPE                                      u_int32_t
#define MAC_PCU_TXOP_12_15__READ                                    0xffffffffU
#define MAC_PCU_TXOP_12_15__WRITE                                   0xffffffffU

#endif /* __MAC_PCU_TXOP_12_15_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_12_15 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_12_15__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS */
#ifndef __MAC_PCU_GENERIC_TIMERS_MACRO__
#define __MAC_PCU_GENERIC_TIMERS_MACRO__

/* macros for field DATA */
#define MAC_PCU_GENERIC_TIMERS__DATA__SHIFT                                   0
#define MAC_PCU_GENERIC_TIMERS__DATA__WIDTH                                  32
#define MAC_PCU_GENERIC_TIMERS__DATA__MASK                          0xffffffffU
#define MAC_PCU_GENERIC_TIMERS__DATA__READ(src)  (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_GENERIC_TIMERS__TYPE                                  u_int32_t
#define MAC_PCU_GENERIC_TIMERS__READ                                0xffffffffU
#define MAC_PCU_GENERIC_TIMERS__WRITE                               0xffffffffU

#endif /* __MAC_PCU_GENERIC_TIMERS_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS__NUM                    16

/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS_MODE */
#ifndef __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__
#define __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__

/* macros for field ENABLE */
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__SHIFT                            0
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WIDTH                            8
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MASK                   0x000000ffU
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field OVERFLOW_INDEX */
#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__SHIFT                    8
#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__WIDTH                    3
#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__MASK           0x00000700U
#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field THRESH */
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__SHIFT                           12
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WIDTH                           20
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MASK                   0xfffff000U
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfffff000U) >> 12)
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0xfffff000U)
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffff000U) | (((u_int32_t)(src) <<\
                    12) & 0xfffff000U)
#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0xfffff000U)))
#define MAC_PCU_GENERIC_TIMERS_MODE__TYPE                             u_int32_t
#define MAC_PCU_GENERIC_TIMERS_MODE__READ                           0xfffff7ffU
#define MAC_PCU_GENERIC_TIMERS_MODE__WRITE                          0xfffff7ffU

#endif /* __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS_MODE__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_MODE */
#ifndef __MAC_PCU_SLP32_MODE_MACRO__
#define __MAC_PCU_SLP32_MODE_MACRO__

/* macros for field HALF_CLK_LATENCY */
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__SHIFT                           0
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WIDTH                          20
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MASK                  0x000fffffU
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000fffffU
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000fffffU)
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fffffU) | ((u_int32_t)(src) &\
                    0x000fffffU)
#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000fffffU)))

/* macros for field ENABLE */
#define MAC_PCU_SLP32_MODE__ENABLE__SHIFT                                    20
#define MAC_PCU_SLP32_MODE__ENABLE__WIDTH                                     1
#define MAC_PCU_SLP32_MODE__ENABLE__MASK                            0x00100000U
#define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_SLP32_MODE__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_SLP32_MODE__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field TSF_WRITE_STATUS */
#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SHIFT                          21
#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__WIDTH                           1
#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__MASK                  0x00200000U
#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field DISABLE_32KHZ */
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SHIFT                             22
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WIDTH                              1
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MASK                     0x00400000U
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field FORCE_BIAS_BLOCK_ON */
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SHIFT                       23
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WIDTH                        1
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MASK               0x00800000U
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field TSF2_WRITE_STATUS */
#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SHIFT                         24
#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__WIDTH                          1
#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__MASK                 0x01000000U
#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define MAC_PCU_SLP32_MODE__TYPE                                      u_int32_t
#define MAC_PCU_SLP32_MODE__READ                                    0x01ffffffU
#define MAC_PCU_SLP32_MODE__WRITE                                   0x01ffffffU

#endif /* __MAC_PCU_SLP32_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_MODE__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_WAKE */
#ifndef __MAC_PCU_SLP32_WAKE_MACRO__
#define __MAC_PCU_SLP32_WAKE_MACRO__

/* macros for field XTL_TIME */
#define MAC_PCU_SLP32_WAKE__XTL_TIME__SHIFT                                   0
#define MAC_PCU_SLP32_WAKE__XTL_TIME__WIDTH                                  16
#define MAC_PCU_SLP32_WAKE__XTL_TIME__MASK                          0x0000ffffU
#define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src)  (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_SLP32_WAKE__TYPE                                      u_int32_t
#define MAC_PCU_SLP32_WAKE__READ                                    0x0000ffffU
#define MAC_PCU_SLP32_WAKE__WRITE                                   0x0000ffffU

#endif /* __MAC_PCU_SLP32_WAKE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_WAKE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_WAKE__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_INC */
#ifndef __MAC_PCU_SLP32_INC_MACRO__
#define __MAC_PCU_SLP32_INC_MACRO__

/* macros for field TSF_INC */
#define MAC_PCU_SLP32_INC__TSF_INC__SHIFT                                     0
#define MAC_PCU_SLP32_INC__TSF_INC__WIDTH                                    20
#define MAC_PCU_SLP32_INC__TSF_INC__MASK                            0x000fffffU
#define MAC_PCU_SLP32_INC__TSF_INC__READ(src)    (u_int32_t)(src) & 0x000fffffU
#define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU)
#define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fffffU) | ((u_int32_t)(src) &\
                    0x000fffffU)
#define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000fffffU)))
#define MAC_PCU_SLP32_INC__TYPE                                       u_int32_t
#define MAC_PCU_SLP32_INC__READ                                     0x000fffffU
#define MAC_PCU_SLP32_INC__WRITE                                    0x000fffffU

#endif /* __MAC_PCU_SLP32_INC_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_INC */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_INC__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB1 */
#ifndef __MAC_PCU_SLP_MIB1_MACRO__
#define __MAC_PCU_SLP_MIB1_MACRO__

/* macros for field SLEEP_CNT */
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__SHIFT                                    0
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WIDTH                                   32
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MASK                           0xffffffffU
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src)   (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_SLP_MIB1__TYPE                                        u_int32_t
#define MAC_PCU_SLP_MIB1__READ                                      0xffffffffU
#define MAC_PCU_SLP_MIB1__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_SLP_MIB1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB1__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB2 */
#ifndef __MAC_PCU_SLP_MIB2_MACRO__
#define __MAC_PCU_SLP_MIB2_MACRO__

/* macros for field CYCLE_CNT */
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__SHIFT                                    0
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WIDTH                                   32
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MASK                           0xffffffffU
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src)   (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_SLP_MIB2__TYPE                                        u_int32_t
#define MAC_PCU_SLP_MIB2__READ                                      0xffffffffU
#define MAC_PCU_SLP_MIB2__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_SLP_MIB2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB2__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB3 */
#ifndef __MAC_PCU_SLP_MIB3_MACRO__
#define __MAC_PCU_SLP_MIB3_MACRO__

/* macros for field CLR_CNT */
#define MAC_PCU_SLP_MIB3__CLR_CNT__SHIFT                                      0
#define MAC_PCU_SLP_MIB3__CLR_CNT__WIDTH                                      1
#define MAC_PCU_SLP_MIB3__CLR_CNT__MASK                             0x00000001U
#define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src)     (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
#define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_SLP_MIB3__CLR_CNT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_SLP_MIB3__CLR_CNT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field PENDING */
#define MAC_PCU_SLP_MIB3__PENDING__SHIFT                                      1
#define MAC_PCU_SLP_MIB3__PENDING__WIDTH                                      1
#define MAC_PCU_SLP_MIB3__PENDING__MASK                             0x00000002U
#define MAC_PCU_SLP_MIB3__PENDING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_SLP_MIB3__PENDING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_SLP_MIB3__PENDING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define MAC_PCU_SLP_MIB3__TYPE                                        u_int32_t
#define MAC_PCU_SLP_MIB3__READ                                      0x00000003U
#define MAC_PCU_SLP_MIB3__WRITE                                     0x00000003U

#endif /* __MAC_PCU_SLP_MIB3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB3__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW1 */
#ifndef __MAC_PCU_WOW1_MACRO__
#define __MAC_PCU_WOW1_MACRO__

/* macros for field PATTERN_ENABLE */
#define MAC_PCU_WOW1__PATTERN_ENABLE__SHIFT                                   0
#define MAC_PCU_WOW1__PATTERN_ENABLE__WIDTH                                   8
#define MAC_PCU_WOW1__PATTERN_ENABLE__MASK                          0x000000ffU
#define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src)  (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field PATTERN_DETECT */
#define MAC_PCU_WOW1__PATTERN_DETECT__SHIFT                                   8
#define MAC_PCU_WOW1__PATTERN_DETECT__WIDTH                                   8
#define MAC_PCU_WOW1__PATTERN_DETECT__MASK                          0x0000ff00U
#define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field MAGIC_ENABLE */
#define MAC_PCU_WOW1__MAGIC_ENABLE__SHIFT                                    16
#define MAC_PCU_WOW1__MAGIC_ENABLE__WIDTH                                     1
#define MAC_PCU_WOW1__MAGIC_ENABLE__MASK                            0x00010000U
#define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_WOW1__MAGIC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_WOW1__MAGIC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field MAGIC_DETECT */
#define MAC_PCU_WOW1__MAGIC_DETECT__SHIFT                                    17
#define MAC_PCU_WOW1__MAGIC_DETECT__WIDTH                                     1
#define MAC_PCU_WOW1__MAGIC_DETECT__MASK                            0x00020000U
#define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_WOW1__MAGIC_DETECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_WOW1__MAGIC_DETECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field INTR_ENABLE */
#define MAC_PCU_WOW1__INTR_ENABLE__SHIFT                                     18
#define MAC_PCU_WOW1__INTR_ENABLE__WIDTH                                      1
#define MAC_PCU_WOW1__INTR_ENABLE__MASK                             0x00040000U
#define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_PCU_WOW1__INTR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_WOW1__INTR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field INTR_DETECT */
#define MAC_PCU_WOW1__INTR_DETECT__SHIFT                                     19
#define MAC_PCU_WOW1__INTR_DETECT__WIDTH                                      1
#define MAC_PCU_WOW1__INTR_DETECT__MASK                             0x00080000U
#define MAC_PCU_WOW1__INTR_DETECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_WOW1__INTR_DETECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_WOW1__INTR_DETECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field KEEP_ALIVE_FAIL */
#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SHIFT                                 20
#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__WIDTH                                  1
#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__MASK                         0x00100000U
#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field BEACON_FAIL */
#define MAC_PCU_WOW1__BEACON_FAIL__SHIFT                                     21
#define MAC_PCU_WOW1__BEACON_FAIL__WIDTH                                      1
#define MAC_PCU_WOW1__BEACON_FAIL__MASK                             0x00200000U
#define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_WOW1__BEACON_FAIL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_WOW1__BEACON_FAIL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field CW_BITS */
#define MAC_PCU_WOW1__CW_BITS__SHIFT                                         28
#define MAC_PCU_WOW1__CW_BITS__WIDTH                                          4
#define MAC_PCU_WOW1__CW_BITS__MASK                                 0xf0000000U
#define MAC_PCU_WOW1__CW_BITS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf0000000U) >> 28)
#define MAC_PCU_WOW1__CW_BITS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0xf0000000U)
#define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((u_int32_t)(src) <<\
                    28) & 0xf0000000U)
#define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define MAC_PCU_WOW1__TYPE                                            u_int32_t
#define MAC_PCU_WOW1__READ                                          0xf03fffffU
#define MAC_PCU_WOW1__WRITE                                         0xf03fffffU

#endif /* __MAC_PCU_WOW1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW1__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW2 */
#ifndef __MAC_PCU_WOW2_MACRO__
#define __MAC_PCU_WOW2_MACRO__

/* macros for field AIFS */
#define MAC_PCU_WOW2__AIFS__SHIFT                                             0
#define MAC_PCU_WOW2__AIFS__WIDTH                                             8
#define MAC_PCU_WOW2__AIFS__MASK                                    0x000000ffU
#define MAC_PCU_WOW2__AIFS__READ(src)            (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_WOW2__AIFS__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
#define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW2__AIFS__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field SLOT */
#define MAC_PCU_WOW2__SLOT__SHIFT                                             8
#define MAC_PCU_WOW2__SLOT__WIDTH                                             8
#define MAC_PCU_WOW2__SLOT__MASK                                    0x0000ff00U
#define MAC_PCU_WOW2__SLOT__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define MAC_PCU_WOW2__SLOT__WRITE(src)  (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_WOW2__SLOT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field TRY_CNT */
#define MAC_PCU_WOW2__TRY_CNT__SHIFT                                         16
#define MAC_PCU_WOW2__TRY_CNT__WIDTH                                          8
#define MAC_PCU_WOW2__TRY_CNT__MASK                                 0x00ff0000U
#define MAC_PCU_WOW2__TRY_CNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))
#define MAC_PCU_WOW2__TYPE                                            u_int32_t
#define MAC_PCU_WOW2__READ                                          0x00ffffffU
#define MAC_PCU_WOW2__WRITE                                         0x00ffffffU

#endif /* __MAC_PCU_WOW2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW2__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER */
#ifndef __MAC_PCU_LOGIC_ANALYZER_MACRO__
#define __MAC_PCU_LOGIC_ANALYZER_MACRO__

/* macros for field HOLD */
#define MAC_PCU_LOGIC_ANALYZER__HOLD__SHIFT                                   0
#define MAC_PCU_LOGIC_ANALYZER__HOLD__WIDTH                                   1
#define MAC_PCU_LOGIC_ANALYZER__HOLD__MASK                          0x00000001U
#define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src)  (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_LOGIC_ANALYZER__HOLD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_LOGIC_ANALYZER__HOLD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field CLEAR */
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SHIFT                                  1
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WIDTH                                  1
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MASK                         0x00000002U
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_LOGIC_ANALYZER__CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field STATE */
#define MAC_PCU_LOGIC_ANALYZER__STATE__SHIFT                                  2
#define MAC_PCU_LOGIC_ANALYZER__STATE__WIDTH                                  1
#define MAC_PCU_LOGIC_ANALYZER__STATE__MASK                         0x00000004U
#define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_LOGIC_ANALYZER__STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_LOGIC_ANALYZER__STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field ENABLE */
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SHIFT                                 3
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WIDTH                                 1
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MASK                        0x00000008U
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_LOGIC_ANALYZER__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field QCU_SEL */
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__SHIFT                                4
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WIDTH                                4
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MASK                       0x000000f0U
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field INT_ADDR */
#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__SHIFT                               8
#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__WIDTH                              10
#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__MASK                      0x0003ff00U
#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003ff00U) >> 8)

/* macros for field DIAG_MODE */
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__SHIFT                             18
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WIDTH                             14
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MASK                     0xfffc0000U
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfffc0000U) >> 18)
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0xfffc0000U)
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffc0000U) | (((u_int32_t)(src) <<\
                    18) & 0xfffc0000U)
#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0xfffc0000U)))
#define MAC_PCU_LOGIC_ANALYZER__TYPE                                  u_int32_t
#define MAC_PCU_LOGIC_ANALYZER__READ                                0xffffffffU
#define MAC_PCU_LOGIC_ANALYZER__WRITE                               0xffffffffU

#endif /* __MAC_PCU_LOGIC_ANALYZER_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_32L */
#ifndef __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__
#define __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__

/* macros for field MASK */
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__SHIFT                               0
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WIDTH                              32
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MASK                      0xffffffffU
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_LOGIC_ANALYZER_32L__TYPE                              u_int32_t
#define MAC_PCU_LOGIC_ANALYZER_32L__READ                            0xffffffffU
#define MAC_PCU_LOGIC_ANALYZER_32L__WRITE                           0xffffffffU

#endif /* __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_32L */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_32L__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_16U */
#ifndef __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__
#define __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__

/* macros for field MASK */
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__SHIFT                               0
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WIDTH                              16
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MASK                      0x0000ffffU
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_LOGIC_ANALYZER_16U__TYPE                              u_int32_t
#define MAC_PCU_LOGIC_ANALYZER_16U__READ                            0x0000ffffU
#define MAC_PCU_LOGIC_ANALYZER_16U__WRITE                           0x0000ffffU

#endif /* __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_16U */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_16U__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON_FAIL */
#ifndef __MAC_PCU_WOW3_BEACON_FAIL_MACRO__
#define __MAC_PCU_WOW3_BEACON_FAIL_MACRO__

/* macros for field ENABLE */
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SHIFT                               0
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WIDTH                               1
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MASK                      0x00000001U
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define MAC_PCU_WOW3_BEACON_FAIL__TYPE                                u_int32_t
#define MAC_PCU_WOW3_BEACON_FAIL__READ                              0x00000001U
#define MAC_PCU_WOW3_BEACON_FAIL__WRITE                             0x00000001U

#endif /* __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON_FAIL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON_FAIL__NUM                   1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON */
#ifndef __MAC_PCU_WOW3_BEACON_MACRO__
#define __MAC_PCU_WOW3_BEACON_MACRO__

/* macros for field TIMEOUT */
#define MAC_PCU_WOW3_BEACON__TIMEOUT__SHIFT                                   0
#define MAC_PCU_WOW3_BEACON__TIMEOUT__WIDTH                                  32
#define MAC_PCU_WOW3_BEACON__TIMEOUT__MASK                          0xffffffffU
#define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src)  (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_WOW3_BEACON__TYPE                                     u_int32_t
#define MAC_PCU_WOW3_BEACON__READ                                   0xffffffffU
#define MAC_PCU_WOW3_BEACON__WRITE                                  0xffffffffU

#endif /* __MAC_PCU_WOW3_BEACON_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_KEEP_ALIVE */
#ifndef __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__
#define __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__

/* macros for field TIMEOUT */
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__SHIFT                               0
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WIDTH                              32
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MASK                      0xffffffffU
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_WOW3_KEEP_ALIVE__TYPE                                 u_int32_t
#define MAC_PCU_WOW3_KEEP_ALIVE__READ                               0xffffffffU
#define MAC_PCU_WOW3_KEEP_ALIVE__WRITE                              0xffffffffU

#endif /* __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_KEEP_ALIVE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_KEEP_ALIVE__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_KA */
#ifndef __MAC_PCU_WOW_KA_MACRO__
#define __MAC_PCU_WOW_KA_MACRO__

/* macros for field AUTO_DISABLE */
#define MAC_PCU_WOW_KA__AUTO_DISABLE__SHIFT                                   0
#define MAC_PCU_WOW_KA__AUTO_DISABLE__WIDTH                                   1
#define MAC_PCU_WOW_KA__AUTO_DISABLE__MASK                          0x00000001U
#define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src)  (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_WOW_KA__AUTO_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_WOW_KA__AUTO_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field FAIL_DISABLE */
#define MAC_PCU_WOW_KA__FAIL_DISABLE__SHIFT                                   1
#define MAC_PCU_WOW_KA__FAIL_DISABLE__WIDTH                                   1
#define MAC_PCU_WOW_KA__FAIL_DISABLE__MASK                          0x00000002U
#define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_WOW_KA__FAIL_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_WOW_KA__FAIL_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field BKOFF_CS_ENABLE */
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SHIFT                                2
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WIDTH                                1
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MASK                       0x00000004U
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)
#define MAC_PCU_WOW_KA__TYPE                                          u_int32_t
#define MAC_PCU_WOW_KA__READ                                        0x00000007U
#define MAC_PCU_WOW_KA__WRITE                                       0x00000007U

#endif /* __MAC_PCU_WOW_KA_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW_KA */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_KA__NUM                             1

/* macros for BlueprintGlobalNameSpace::PCU_1US */
#ifndef __PCU_1US_MACRO__
#define __PCU_1US_MACRO__

/* macros for field SCALER */
#define PCU_1US__SCALER__SHIFT                                                0
#define PCU_1US__SCALER__WIDTH                                                7
#define PCU_1US__SCALER__MASK                                       0x0000007fU
#define PCU_1US__SCALER__READ(src)               (u_int32_t)(src) & 0x0000007fU
#define PCU_1US__SCALER__WRITE(src)            ((u_int32_t)(src) & 0x0000007fU)
#define PCU_1US__SCALER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define PCU_1US__SCALER__VERIFY(src)     (!(((u_int32_t)(src) & ~0x0000007fU)))
#define PCU_1US__TYPE                                                 u_int32_t
#define PCU_1US__READ                                               0x0000007fU
#define PCU_1US__WRITE                                              0x0000007fU

#endif /* __PCU_1US_MACRO__ */


/* macros for mac_pcu_reg_map.PCU_1US */
#define INST_MAC_PCU_REG_MAP__PCU_1US__NUM                                    1

/* macros for BlueprintGlobalNameSpace::PCU_KA */
#ifndef __PCU_KA_MACRO__
#define __PCU_KA_MACRO__

/* macros for field DEL */
#define PCU_KA__DEL__SHIFT                                                    0
#define PCU_KA__DEL__WIDTH                                                   12
#define PCU_KA__DEL__MASK                                           0x00000fffU
#define PCU_KA__DEL__READ(src)                   (u_int32_t)(src) & 0x00000fffU
#define PCU_KA__DEL__WRITE(src)                ((u_int32_t)(src) & 0x00000fffU)
#define PCU_KA__DEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define PCU_KA__DEL__VERIFY(src)         (!(((u_int32_t)(src) & ~0x00000fffU)))
#define PCU_KA__TYPE                                                  u_int32_t
#define PCU_KA__READ                                                0x00000fffU
#define PCU_KA__WRITE                                               0x00000fffU

#endif /* __PCU_KA_MACRO__ */


/* macros for mac_pcu_reg_map.PCU_KA */
#define INST_MAC_PCU_REG_MAP__PCU_KA__NUM                                     1

/* macros for BlueprintGlobalNameSpace::WOW_EXACT */
#ifndef __WOW_EXACT_MACRO__
#define __WOW_EXACT_MACRO__

/* macros for field LENGTH */
#define WOW_EXACT__LENGTH__SHIFT                                              0
#define WOW_EXACT__LENGTH__WIDTH                                              8
#define WOW_EXACT__LENGTH__MASK                                     0x000000ffU
#define WOW_EXACT__LENGTH__READ(src)             (u_int32_t)(src) & 0x000000ffU
#define WOW_EXACT__LENGTH__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
#define WOW_EXACT__LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define WOW_EXACT__LENGTH__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field OFFSET */
#define WOW_EXACT__OFFSET__SHIFT                                              8
#define WOW_EXACT__OFFSET__WIDTH                                              8
#define WOW_EXACT__OFFSET__MASK                                     0x0000ff00U
#define WOW_EXACT__OFFSET__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define WOW_EXACT__OFFSET__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define WOW_EXACT__OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define WOW_EXACT__OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))
#define WOW_EXACT__TYPE                                               u_int32_t
#define WOW_EXACT__READ                                             0x0000ffffU
#define WOW_EXACT__WRITE                                            0x0000ffffU

#endif /* __WOW_EXACT_MACRO__ */


/* macros for mac_pcu_reg_map.WOW_EXACT */
#define INST_MAC_PCU_REG_MAP__WOW_EXACT__NUM                                  1

/* macros for BlueprintGlobalNameSpace::PCU_WOW4 */
#ifndef __PCU_WOW4_MACRO__
#define __PCU_WOW4_MACRO__

/* macros for field OFFSET0 */
#define PCU_WOW4__OFFSET0__SHIFT                                              0
#define PCU_WOW4__OFFSET0__WIDTH                                              8
#define PCU_WOW4__OFFSET0__MASK                                     0x000000ffU
#define PCU_WOW4__OFFSET0__READ(src)             (u_int32_t)(src) & 0x000000ffU
#define PCU_WOW4__OFFSET0__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
#define PCU_WOW4__OFFSET0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define PCU_WOW4__OFFSET0__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field OFFSET1 */
#define PCU_WOW4__OFFSET1__SHIFT                                              8
#define PCU_WOW4__OFFSET1__WIDTH                                              8
#define PCU_WOW4__OFFSET1__MASK                                     0x0000ff00U
#define PCU_WOW4__OFFSET1__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define PCU_WOW4__OFFSET1__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define PCU_WOW4__OFFSET1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define PCU_WOW4__OFFSET1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field OFFSET2 */
#define PCU_WOW4__OFFSET2__SHIFT                                             16
#define PCU_WOW4__OFFSET2__WIDTH                                              8
#define PCU_WOW4__OFFSET2__MASK                                     0x00ff0000U
#define PCU_WOW4__OFFSET2__READ(src)   (((u_int32_t)(src) & 0x00ff0000U) >> 16)
#define PCU_WOW4__OFFSET2__WRITE(src)  (((u_int32_t)(src) << 16) & 0x00ff0000U)
#define PCU_WOW4__OFFSET2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define PCU_WOW4__OFFSET2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field OFFSET3 */
#define PCU_WOW4__OFFSET3__SHIFT                                             24
#define PCU_WOW4__OFFSET3__WIDTH                                              8
#define PCU_WOW4__OFFSET3__MASK                                     0xff000000U
#define PCU_WOW4__OFFSET3__READ(src)   (((u_int32_t)(src) & 0xff000000U) >> 24)
#define PCU_WOW4__OFFSET3__WRITE(src)  (((u_int32_t)(src) << 24) & 0xff000000U)
#define PCU_WOW4__OFFSET3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define PCU_WOW4__OFFSET3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define PCU_WOW4__TYPE                                                u_int32_t
#define PCU_WOW4__READ                                              0xffffffffU
#define PCU_WOW4__WRITE                                             0xffffffffU

#endif /* __PCU_WOW4_MACRO__ */


/* macros for mac_pcu_reg_map.PCU_WOW4 */
#define INST_MAC_PCU_REG_MAP__PCU_WOW4__NUM                                   1

/* macros for BlueprintGlobalNameSpace::PCU_WOW5 */
#ifndef __PCU_WOW5_MACRO__
#define __PCU_WOW5_MACRO__

/* macros for field OFFSET4 */
#define PCU_WOW5__OFFSET4__SHIFT                                              0
#define PCU_WOW5__OFFSET4__WIDTH                                              8
#define PCU_WOW5__OFFSET4__MASK                                     0x000000ffU
#define PCU_WOW5__OFFSET4__READ(src)             (u_int32_t)(src) & 0x000000ffU
#define PCU_WOW5__OFFSET4__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
#define PCU_WOW5__OFFSET4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define PCU_WOW5__OFFSET4__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field OFFSET5 */
#define PCU_WOW5__OFFSET5__SHIFT                                              8
#define PCU_WOW5__OFFSET5__WIDTH                                              8
#define PCU_WOW5__OFFSET5__MASK                                     0x0000ff00U
#define PCU_WOW5__OFFSET5__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define PCU_WOW5__OFFSET5__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define PCU_WOW5__OFFSET5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define PCU_WOW5__OFFSET5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field OFFSET6 */
#define PCU_WOW5__OFFSET6__SHIFT                                             16
#define PCU_WOW5__OFFSET6__WIDTH                                              8
#define PCU_WOW5__OFFSET6__MASK                                     0x00ff0000U
#define PCU_WOW5__OFFSET6__READ(src)   (((u_int32_t)(src) & 0x00ff0000U) >> 16)
#define PCU_WOW5__OFFSET6__WRITE(src)  (((u_int32_t)(src) << 16) & 0x00ff0000U)
#define PCU_WOW5__OFFSET6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define PCU_WOW5__OFFSET6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field OFFSET7 */
#define PCU_WOW5__OFFSET7__SHIFT                                             24
#define PCU_WOW5__OFFSET7__WIDTH                                              8
#define PCU_WOW5__OFFSET7__MASK                                     0xff000000U
#define PCU_WOW5__OFFSET7__READ(src)   (((u_int32_t)(src) & 0xff000000U) >> 24)
#define PCU_WOW5__OFFSET7__WRITE(src)  (((u_int32_t)(src) << 24) & 0xff000000U)
#define PCU_WOW5__OFFSET7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define PCU_WOW5__OFFSET7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define PCU_WOW5__TYPE                                                u_int32_t
#define PCU_WOW5__READ                                              0xffffffffU
#define PCU_WOW5__WRITE                                             0xffffffffU

#endif /* __PCU_WOW5_MACRO__ */


/* macros for mac_pcu_reg_map.PCU_WOW5 */
#define INST_MAC_PCU_REG_MAP__PCU_WOW5__NUM                                   1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_MASK_CONT */
#ifndef __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__
#define __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__

/* macros for field MASK1 */
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__SHIFT                           0
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WIDTH                           8
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MASK                  0x000000ffU
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field MASK2 */
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__SHIFT                           8
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WIDTH                           8
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MASK                  0x0000ff00U
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field MASK3 */
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__SHIFT                          16
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WIDTH                           8
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MASK                  0x00ff0000U
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__TYPE                           u_int32_t
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__READ                         0x00ffffffU
#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__WRITE                        0x00ffffffU

#endif /* __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_MASK_CONT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_MASK_CONT__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_MODE */
#ifndef __MAC_PCU_AZIMUTH_MODE_MACRO__
#define __MAC_PCU_AZIMUTH_MODE_MACRO__

/* macros for field DISABLE_TSF_UPDATE */
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SHIFT                       0
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WIDTH                       1
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MASK              0x00000001U
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field KEY_SEARCH_AD1 */
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SHIFT                           1
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WIDTH                           1
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MASK                  0x00000002U
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field TX_TSF_STATUS_SEL */
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SHIFT                        2
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WIDTH                        1
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MASK               0x00000004U
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field RX_TSF_STATUS_SEL */
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SHIFT                        3
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WIDTH                        1
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MASK               0x00000008U
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field CLK_EN */
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SHIFT                                   4
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WIDTH                                   1
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MASK                          0x00000010U
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_AZIMUTH_MODE__CLK_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field TX_DESC_EN */
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SHIFT                               5
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WIDTH                               1
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MASK                      0x00000020U
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field ACK_CTS_MATCH_TX_AD2 */
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SHIFT                     6
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WIDTH                     1
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MASK            0x00000040U
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field BA_USES_AD1 */
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SHIFT                              7
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WIDTH                              1
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MASK                     0x00000080U
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field WMAC_CLK_SEL */
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SHIFT                             8
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WIDTH                             1
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MASK                    0x00000100U
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field FILTER_PASS_HOLD */
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SHIFT                         9
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WIDTH                         1
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MASK                0x00000200U
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field PROXY_STA_FIX1_ENABLE */
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SHIFT                   10
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WIDTH                    1
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MASK           0x00000400U
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field PROXY_STA_FIX2_ENABLE */
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SHIFT                   11
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WIDTH                    1
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MASK           0x00000800U
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field PROXY_STA_FIX3_ENABLE */
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SHIFT                   12
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WIDTH                    1
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MASK           0x00001000U
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)
#define MAC_PCU_AZIMUTH_MODE__TYPE                                    u_int32_t
#define MAC_PCU_AZIMUTH_MODE__READ                                  0x00001fffU
#define MAC_PCU_AZIMUTH_MODE__WRITE                                 0x00001fffU

#endif /* __MAC_PCU_AZIMUTH_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_MODE__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_TIME_STAMP */
#ifndef __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__
#define __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__

/* macros for field VALUE */
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__SHIFT                              0
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WIDTH                             32
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MASK                     0xffffffffU
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_AZIMUTH_TIME_STAMP__TYPE                              u_int32_t
#define MAC_PCU_AZIMUTH_TIME_STAMP__READ                            0xffffffffU
#define MAC_PCU_AZIMUTH_TIME_STAMP__WRITE                           0xffffffffU

#endif /* __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_TIME_STAMP */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_TIME_STAMP__NUM                 1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_20_40_MODE */
#ifndef __MAC_PCU_20_40_MODE_MACRO__
#define __MAC_PCU_20_40_MODE_MACRO__

/* macros for field JOINED_RX_CLEAR */
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SHIFT                            0
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WIDTH                            1
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MASK                   0x00000001U
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field EXT_PIFS_ENABLE */
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SHIFT                            1
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WIDTH                            1
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MASK                   0x00000002U
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field TX_HT20_ON_EXT_BUSY */
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SHIFT                        2
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WIDTH                        1
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MASK               0x00000004U
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field SWAMPED_FORCES_RX_CLEAR_CTL_IDLE */
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SHIFT           3
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WIDTH           1
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MASK  0x00000008U
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field PIFS_CYCLES */
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__SHIFT                                4
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WIDTH                               12
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MASK                       0x0000fff0U
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fff0U) >> 4)
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x0000fff0U)
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fff0U) | (((u_int32_t)(src) <<\
                    4) & 0x0000fff0U)
#define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x0000fff0U)))
#define MAC_PCU_20_40_MODE__TYPE                                      u_int32_t
#define MAC_PCU_20_40_MODE__READ                                    0x0000ffffU
#define MAC_PCU_20_40_MODE__WRITE                                   0x0000ffffU

#endif /* __MAC_PCU_20_40_MODE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_20_40_MODE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_20_40_MODE__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_H_XFER_TIMEOUT */
#ifndef __MAC_PCU_H_XFER_TIMEOUT_MACRO__
#define __MAC_PCU_H_XFER_TIMEOUT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__SHIFT                                  0
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WIDTH                                  5
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MASK                         0x0000001fU
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field DISABLE */
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SHIFT                                5
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WIDTH                                1
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MASK                       0x00000020U
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field EXTXBF_IMMEDIATE_RESP */
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SHIFT                  6
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WIDTH                  1
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MASK         0x00000040U
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field DELAY_EXTXBF_ONLY_UPLOAD_H */
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SHIFT             7
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WIDTH             1
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MASK    0x00000080U
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field EXTXBF_NOACK_NORPT */
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SHIFT                     8
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WIDTH                     1
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MASK            0x00000100U
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)
#define MAC_PCU_H_XFER_TIMEOUT__TYPE                                  u_int32_t
#define MAC_PCU_H_XFER_TIMEOUT__READ                                0x000001ffU
#define MAC_PCU_H_XFER_TIMEOUT__WRITE                               0x000001ffU

#endif /* __MAC_PCU_H_XFER_TIMEOUT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_H_XFER_TIMEOUT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_H_XFER_TIMEOUT__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_DIFF_CNT */
#ifndef __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__
#define __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__

/* macros for field VALUE */
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__SHIFT                               0
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WIDTH                              32
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MASK                      0xffffffffU
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_RX_CLEAR_DIFF_CNT__TYPE                               u_int32_t
#define MAC_PCU_RX_CLEAR_DIFF_CNT__READ                             0xffffffffU
#define MAC_PCU_RX_CLEAR_DIFF_CNT__WRITE                            0xffffffffU

#endif /* __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_DIFF_CNT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_DIFF_CNT__NUM                  1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_ANTENNA_MASK */
#ifndef __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__
#define __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__SHIFT                           0
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WIDTH                           3
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MASK                  0x00000007U
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field ONE_RESP_EN */
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SHIFT                     3
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WIDTH                     1
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MASK            0x00000008U
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field FORCE_CHAIN_0 */
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SHIFT                   4
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WIDTH                   1
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MASK          0x00000010U
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__TYPE                           u_int32_t
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__READ                         0x0000001fU
#define MAC_PCU_SELF_GEN_ANTENNA_MASK__WRITE                        0x0000001fU

#endif /* __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_ANTENNA_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_ANTENNA_MASK__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BA_BAR_CONTROL */
#ifndef __MAC_PCU_BA_BAR_CONTROL_MACRO__
#define __MAC_PCU_BA_BAR_CONTROL_MACRO__

/* macros for field COMPRESSED_OFFSET */
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__SHIFT                      0
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WIDTH                      4
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MASK             0x0000000fU
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field ACK_POLICY_OFFSET */
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__SHIFT                      4
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WIDTH                      4
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MASK             0x000000f0U
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field COMPRESSED_VALUE */
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SHIFT                       8
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WIDTH                       1
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MASK              0x00000100U
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field ACK_POLICY_VALUE */
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SHIFT                       9
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WIDTH                       1
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MASK              0x00000200U
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field FORCE_NO_MATCH */
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SHIFT                        10
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WIDTH                         1
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MASK                0x00000400U
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field TX_BA_CLEAR_BA_VALID */
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SHIFT                  11
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WIDTH                   1
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MASK          0x00000800U
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field UPDATE_BA_BITMAP_QOS_NULL */
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SHIFT             12
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WIDTH              1
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MASK     0x00001000U
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)
#define MAC_PCU_BA_BAR_CONTROL__TYPE                                  u_int32_t
#define MAC_PCU_BA_BAR_CONTROL__READ                                0x00001fffU
#define MAC_PCU_BA_BAR_CONTROL__WRITE                               0x00001fffU

#endif /* __MAC_PCU_BA_BAR_CONTROL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BA_BAR_CONTROL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BA_BAR_CONTROL__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LEGACY_PLCP_SPOOF */
#ifndef __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__
#define __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__

/* macros for field EIFS_MINUS_DIFS */
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__SHIFT                     0
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WIDTH                     8
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MASK            0x000000ffU
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field MIN_LENGTH */
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__SHIFT                          8
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WIDTH                          5
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MASK                 0x00001f00U
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00001f00U)
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00001f00U)
#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00001f00U)))
#define MAC_PCU_LEGACY_PLCP_SPOOF__TYPE                               u_int32_t
#define MAC_PCU_LEGACY_PLCP_SPOOF__READ                             0x00001fffU
#define MAC_PCU_LEGACY_PLCP_SPOOF__WRITE                            0x00001fffU

#endif /* __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LEGACY_PLCP_SPOOF */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LEGACY_PLCP_SPOOF__NUM                  1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK_CONT */
#ifndef __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__
#define __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__

/* macros for field MASK_VALUE */
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__SHIFT                        0
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WIDTH                        8
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MASK               0x000000ffU
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field EIFS_VALUE */
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__SHIFT                       16
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WIDTH                        8
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MASK               0x00ff0000U
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field AIFS_VALUE */
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__SHIFT                       24
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WIDTH                        8
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MASK               0xff000000U
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_PHY_ERROR_MASK_CONT__TYPE                             u_int32_t
#define MAC_PCU_PHY_ERROR_MASK_CONT__READ                           0xffff00ffU
#define MAC_PCU_PHY_ERROR_MASK_CONT__WRITE                          0xffff00ffU

#endif /* __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK_CONT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK_CONT__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_TIMER */
#ifndef __MAC_PCU_TX_TIMER_MACRO__
#define __MAC_PCU_TX_TIMER_MACRO__

/* macros for field TX_TIMER */
#define MAC_PCU_TX_TIMER__TX_TIMER__SHIFT                                     0
#define MAC_PCU_TX_TIMER__TX_TIMER__WIDTH                                    15
#define MAC_PCU_TX_TIMER__TX_TIMER__MASK                            0x00007fffU
#define MAC_PCU_TX_TIMER__TX_TIMER__READ(src)    (u_int32_t)(src) & 0x00007fffU
#define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU)
#define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007fffU) | ((u_int32_t)(src) &\
                    0x00007fffU)
#define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00007fffU)))

/* macros for field TX_TIMER_ENABLE */
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SHIFT                             15
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WIDTH                              1
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MASK                     0x00008000U
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field RIFS_TIMER */
#define MAC_PCU_TX_TIMER__RIFS_TIMER__SHIFT                                  16
#define MAC_PCU_TX_TIMER__RIFS_TIMER__WIDTH                                   4
#define MAC_PCU_TX_TIMER__RIFS_TIMER__MASK                          0x000f0000U
#define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field QUIET_TIMER */
#define MAC_PCU_TX_TIMER__QUIET_TIMER__SHIFT                                 20
#define MAC_PCU_TX_TIMER__QUIET_TIMER__WIDTH                                  5
#define MAC_PCU_TX_TIMER__QUIET_TIMER__MASK                         0x01f00000U
#define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field QUIET_TIMER_ENABLE */
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SHIFT                          25
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WIDTH                           1
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MASK                  0x02000000U
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)
#define MAC_PCU_TX_TIMER__TYPE                                        u_int32_t
#define MAC_PCU_TX_TIMER__READ                                      0x03ffffffU
#define MAC_PCU_TX_TIMER__WRITE                                     0x03ffffffU

#endif /* __MAC_PCU_TX_TIMER_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TX_TIMER */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_TIMER__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_CTRL */
#ifndef __MAC_PCU_TXBUF_CTRL_MACRO__
#define __MAC_PCU_TXBUF_CTRL_MACRO__

/* macros for field USABLE_ENTRIES */
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__SHIFT                             0
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WIDTH                            12
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MASK                    0x00000fffU
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000fffU)
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field TX_FIFO_WRAP_ENABLE */
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SHIFT                       16
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WIDTH                        1
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MASK               0x00010000U
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)
#define MAC_PCU_TXBUF_CTRL__TYPE                                      u_int32_t
#define MAC_PCU_TXBUF_CTRL__READ                                    0x00010fffU
#define MAC_PCU_TXBUF_CTRL__WRITE                                   0x00010fffU

#endif /* __MAC_PCU_TXBUF_CTRL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_CTRL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_CTRL__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE2 */
#ifndef __MAC_PCU_MISC_MODE2_MACRO__
#define __MAC_PCU_MISC_MODE2_MACRO__

/* macros for field BUG_21532_FIX_ENABLE */
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SHIFT                       0
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MASK              0x00000001U
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field MGMT_CRYPTO_ENABLE */
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SHIFT                         1
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WIDTH                         1
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MASK                0x00000002U
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field NO_CRYPTO_FOR_NON_DATA_PKT */
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SHIFT                 2
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WIDTH                 1
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MASK        0x00000004U
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field BUG_58603_FIX_ENABLE */
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SHIFT                       3
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MASK              0x00000008U
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field BUG_58057_FIX_ENABLE */
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SHIFT                       4
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MASK              0x00000010U
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field RESERVED_0 */
#define MAC_PCU_MISC_MODE2__RESERVED_0__SHIFT                                 5
#define MAC_PCU_MISC_MODE2__RESERVED_0__WIDTH                                 1
#define MAC_PCU_MISC_MODE2__RESERVED_0__MASK                        0x00000020U
#define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_MISC_MODE2__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_MISC_MODE2__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field ADHOC_MCAST_KEYID_ENABLE */
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SHIFT                   6
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WIDTH                   1
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MASK          0x00000040U
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field CFP_IGNORE */
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SHIFT                                 7
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WIDTH                                 1
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MASK                        0x00000080U
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_MISC_MODE2__CFP_IGNORE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field MGMT_QOS */
#define MAC_PCU_MISC_MODE2__MGMT_QOS__SHIFT                                   8
#define MAC_PCU_MISC_MODE2__MGMT_QOS__WIDTH                                   8
#define MAC_PCU_MISC_MODE2__MGMT_QOS__MASK                          0x0000ff00U
#define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field ENABLE_LOAD_NAV_BEACON_DURATION */
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SHIFT           16
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WIDTH            1
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MASK   0x00010000U
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field AGG_WEP */
#define MAC_PCU_MISC_MODE2__AGG_WEP__SHIFT                                   17
#define MAC_PCU_MISC_MODE2__AGG_WEP__WIDTH                                    1
#define MAC_PCU_MISC_MODE2__AGG_WEP__MASK                           0x00020000U
#define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_MISC_MODE2__AGG_WEP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_MISC_MODE2__AGG_WEP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field BC_MC_WAPI_MODE */
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SHIFT                           18
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WIDTH                            1
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MASK                   0x00040000U
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field DUR_ACCOUNT_BY_BA */
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SHIFT                         19
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WIDTH                          1
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MASK                 0x00080000U
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field BUG_28676 */
#define MAC_PCU_MISC_MODE2__BUG_28676__SHIFT                                 20
#define MAC_PCU_MISC_MODE2__BUG_28676__WIDTH                                  1
#define MAC_PCU_MISC_MODE2__BUG_28676__MASK                         0x00100000U
#define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_MISC_MODE2__BUG_28676__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_MISC_MODE2__BUG_28676__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field CLEAR_MORE_FRAG */
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SHIFT                           21
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WIDTH                            1
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MASK                   0x00200000U
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field IGNORE_TXOP_1ST_PKT */
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SHIFT                       22
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WIDTH                        1
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MASK               0x00400000U
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field MPDU_DENSITY_STS_FIX */
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SHIFT                      23
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WIDTH                       1
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MASK              0x00800000U
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field MPDU_DENSITY_WAIT_WEP */
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SHIFT                     24
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WIDTH                      1
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MASK             0x01000000U
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field RCV_TIMESTAMP_FIX */
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SHIFT                         25
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WIDTH                          1
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MASK                 0x02000000U
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field PM_FIELD_FOR_NON_CTRL */
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SHIFT                     26
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WIDTH                      1
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MASK             0x04000000U
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field DECOUPLE_DECRYPTION */
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SHIFT                       27
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WIDTH                        1
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MASK               0x08000000U
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field H_TO_SW_DEBUG_MODE */
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SHIFT                        28
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WIDTH                         1
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MASK                0x10000000U
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field TXBF_ACT_RPT_DONE_PASS */
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SHIFT                    29
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WIDTH                     1
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MASK            0x20000000U
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field PCU_LOOP_TXBF */
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SHIFT                             30
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WIDTH                              1
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MASK                     0x40000000U
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field CLEAR_WEP_TXBUSY_ON_TXURN */
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SHIFT                 31
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WIDTH                  1
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MASK         0x80000000U
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define MAC_PCU_MISC_MODE2__TYPE                                      u_int32_t
#define MAC_PCU_MISC_MODE2__READ                                    0xffffffffU
#define MAC_PCU_MISC_MODE2__WRITE                                   0xffffffffU

#endif /* __MAC_PCU_MISC_MODE2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE2__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_ALT_AES_MUTE_MASK */
#ifndef __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__
#define __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__

/* macros for field QOS */
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__SHIFT                                16
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WIDTH                                16
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MASK                        0xffff0000U
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define MAC_PCU_ALT_AES_MUTE_MASK__TYPE                               u_int32_t
#define MAC_PCU_ALT_AES_MUTE_MASK__READ                             0xffff0000U
#define MAC_PCU_ALT_AES_MUTE_MASK__WRITE                            0xffff0000U

#endif /* __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_ALT_AES_MUTE_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_ALT_AES_MUTE_MASK__NUM                  1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW6 */
#ifndef __MAC_PCU_WOW6_MACRO__
#define __MAC_PCU_WOW6_MACRO__

/* macros for field RXBUF_START_ADDR */
#define MAC_PCU_WOW6__RXBUF_START_ADDR__SHIFT                                 0
#define MAC_PCU_WOW6__RXBUF_START_ADDR__WIDTH                                16
#define MAC_PCU_WOW6__RXBUF_START_ADDR__MASK                        0x0000ffffU
#define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define MAC_PCU_WOW6__TYPE                                            u_int32_t
#define MAC_PCU_WOW6__READ                                          0x0000ffffU

#endif /* __MAC_PCU_WOW6_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW6 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW6__NUM                               1

/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG1 */
#ifndef __ASYNC_FIFO_REG1_MACRO__
#define __ASYNC_FIFO_REG1_MACRO__

/* macros for field DBG */
#define ASYNC_FIFO_REG1__DBG__SHIFT                                           0
#define ASYNC_FIFO_REG1__DBG__WIDTH                                          30
#define ASYNC_FIFO_REG1__DBG__MASK                                  0x3fffffffU
#define ASYNC_FIFO_REG1__DBG__READ(src)          (u_int32_t)(src) & 0x3fffffffU
#define ASYNC_FIFO_REG1__DBG__WRITE(src)       ((u_int32_t)(src) & 0x3fffffffU)
#define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((u_int32_t)(src) &\
                    0x3fffffffU)
#define ASYNC_FIFO_REG1__DBG__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x3fffffffU)))
#define ASYNC_FIFO_REG1__TYPE                                         u_int32_t
#define ASYNC_FIFO_REG1__READ                                       0x3fffffffU
#define ASYNC_FIFO_REG1__WRITE                                      0x3fffffffU

#endif /* __ASYNC_FIFO_REG1_MACRO__ */


/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG1 */
#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG1__NUM                            1

/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG2 */
#ifndef __ASYNC_FIFO_REG2_MACRO__
#define __ASYNC_FIFO_REG2_MACRO__

/* macros for field DBG */
#define ASYNC_FIFO_REG2__DBG__SHIFT                                           0
#define ASYNC_FIFO_REG2__DBG__WIDTH                                          28
#define ASYNC_FIFO_REG2__DBG__MASK                                  0x0fffffffU
#define ASYNC_FIFO_REG2__DBG__READ(src)          (u_int32_t)(src) & 0x0fffffffU
#define ASYNC_FIFO_REG2__DBG__WRITE(src)       ((u_int32_t)(src) & 0x0fffffffU)
#define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffffffU) | ((u_int32_t)(src) &\
                    0x0fffffffU)
#define ASYNC_FIFO_REG2__DBG__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0fffffffU)))
#define ASYNC_FIFO_REG2__TYPE                                         u_int32_t
#define ASYNC_FIFO_REG2__READ                                       0x0fffffffU
#define ASYNC_FIFO_REG2__WRITE                                      0x0fffffffU

#endif /* __ASYNC_FIFO_REG2_MACRO__ */


/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG2 */
#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG2__NUM                            1

/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG3 */
#ifndef __ASYNC_FIFO_REG3_MACRO__
#define __ASYNC_FIFO_REG3_MACRO__

/* macros for field DBG */
#define ASYNC_FIFO_REG3__DBG__SHIFT                                           0
#define ASYNC_FIFO_REG3__DBG__WIDTH                                          10
#define ASYNC_FIFO_REG3__DBG__MASK                                  0x000003ffU
#define ASYNC_FIFO_REG3__DBG__READ(src)          (u_int32_t)(src) & 0x000003ffU
#define ASYNC_FIFO_REG3__DBG__WRITE(src)       ((u_int32_t)(src) & 0x000003ffU)
#define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define ASYNC_FIFO_REG3__DBG__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field DATAPATH_SEL */
#define ASYNC_FIFO_REG3__DATAPATH_SEL__SHIFT                                 10
#define ASYNC_FIFO_REG3__DATAPATH_SEL__WIDTH                                  1
#define ASYNC_FIFO_REG3__DATAPATH_SEL__MASK                         0x00000400U
#define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define ASYNC_FIFO_REG3__DATAPATH_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define ASYNC_FIFO_REG3__DATAPATH_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field SFT_RST_N */
#define ASYNC_FIFO_REG3__SFT_RST_N__SHIFT                                    31
#define ASYNC_FIFO_REG3__SFT_RST_N__WIDTH                                     1
#define ASYNC_FIFO_REG3__SFT_RST_N__MASK                            0x80000000U
#define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define ASYNC_FIFO_REG3__SFT_RST_N__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define ASYNC_FIFO_REG3__SFT_RST_N__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define ASYNC_FIFO_REG3__TYPE                                         u_int32_t
#define ASYNC_FIFO_REG3__READ                                       0x800007ffU
#define ASYNC_FIFO_REG3__WRITE                                      0x800007ffU

#endif /* __ASYNC_FIFO_REG3_MACRO__ */


/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG3 */
#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG3__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW5 */
#ifndef __MAC_PCU_WOW5_MACRO__
#define __MAC_PCU_WOW5_MACRO__

/* macros for field RX_ABORT_ENABLE */
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__SHIFT                                  0
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WIDTH                                 16
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MASK                         0x0000ffffU
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define MAC_PCU_WOW5__TYPE                                            u_int32_t
#define MAC_PCU_WOW5__READ                                          0x0000ffffU
#define MAC_PCU_WOW5__WRITE                                         0x0000ffffU

#endif /* __MAC_PCU_WOW5_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW5 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW5__NUM                               1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH1 */
#ifndef __MAC_PCU_WOW_LENGTH1_MACRO__
#define __MAC_PCU_WOW_LENGTH1_MACRO__

/* macros for field PATTERN_3 */
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__SHIFT                                 0
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MASK                        0x000000ffU
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field PATTERN_2 */
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__SHIFT                                 8
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MASK                        0x0000ff00U
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field PATTERN_1 */
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__SHIFT                                16
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MASK                        0x00ff0000U
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field PATTERN_0 */
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__SHIFT                                24
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MASK                        0xff000000U
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_WOW_LENGTH1__TYPE                                     u_int32_t
#define MAC_PCU_WOW_LENGTH1__READ                                   0xffffffffU
#define MAC_PCU_WOW_LENGTH1__WRITE                                  0xffffffffU

#endif /* __MAC_PCU_WOW_LENGTH1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH1__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH2 */
#ifndef __MAC_PCU_WOW_LENGTH2_MACRO__
#define __MAC_PCU_WOW_LENGTH2_MACRO__

/* macros for field PATTERN_7 */
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__SHIFT                                 0
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MASK                        0x000000ffU
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field PATTERN_6 */
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__SHIFT                                 8
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MASK                        0x0000ff00U
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field PATTERN_5 */
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__SHIFT                                16
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MASK                        0x00ff0000U
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field PATTERN_4 */
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__SHIFT                                24
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MASK                        0xff000000U
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_WOW_LENGTH2__TYPE                                     u_int32_t
#define MAC_PCU_WOW_LENGTH2__READ                                   0xffffffffU
#define MAC_PCU_WOW_LENGTH2__WRITE                                  0xffffffffU

#endif /* __MAC_PCU_WOW_LENGTH2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH2__NUM                        1

/* macros for BlueprintGlobalNameSpace::WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */
#ifndef __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__
#define __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__

/* macros for field EN */
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__SHIFT                      0
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WIDTH                     16
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MASK             0x0000ffffU
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__TYPE                   u_int32_t
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__READ                 0x0000ffffU
#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__WRITE                0x0000ffffU

#endif /* __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ */


/* macros for mac_pcu_reg_map.WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */
#define INST_MAC_PCU_REG_MAP__WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__NUM      1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW4 */
#ifndef __MAC_PCU_WOW4_MACRO__
#define __MAC_PCU_WOW4_MACRO__

/* macros for field PATTERN_ENABLE */
#define MAC_PCU_WOW4__PATTERN_ENABLE__SHIFT                                   0
#define MAC_PCU_WOW4__PATTERN_ENABLE__WIDTH                                   8
#define MAC_PCU_WOW4__PATTERN_ENABLE__MASK                          0x000000ffU
#define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src)  (u_int32_t)(src) & 0x000000ffU
#define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field PATTERN_DETECT */
#define MAC_PCU_WOW4__PATTERN_DETECT__SHIFT                                   8
#define MAC_PCU_WOW4__PATTERN_DETECT__WIDTH                                   8
#define MAC_PCU_WOW4__PATTERN_DETECT__MASK                          0x0000ff00U
#define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_WOW4__TYPE                                            u_int32_t
#define MAC_PCU_WOW4__READ                                          0x0000ffffU
#define MAC_PCU_WOW4__WRITE                                         0x0000ffffU

#endif /* __MAC_PCU_WOW4_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW4 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW4__NUM                               1

/* macros for BlueprintGlobalNameSpace::WOW2_EXACT */
#ifndef __WOW2_EXACT_MACRO__
#define __WOW2_EXACT_MACRO__

/* macros for field LENGTH */
#define WOW2_EXACT__LENGTH__SHIFT                                             0
#define WOW2_EXACT__LENGTH__WIDTH                                             8
#define WOW2_EXACT__LENGTH__MASK                                    0x000000ffU
#define WOW2_EXACT__LENGTH__READ(src)            (u_int32_t)(src) & 0x000000ffU
#define WOW2_EXACT__LENGTH__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
#define WOW2_EXACT__LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define WOW2_EXACT__LENGTH__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field OFFSET */
#define WOW2_EXACT__OFFSET__SHIFT                                             8
#define WOW2_EXACT__OFFSET__WIDTH                                             8
#define WOW2_EXACT__OFFSET__MASK                                    0x0000ff00U
#define WOW2_EXACT__OFFSET__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define WOW2_EXACT__OFFSET__WRITE(src)  (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define WOW2_EXACT__OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define WOW2_EXACT__OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))
#define WOW2_EXACT__TYPE                                              u_int32_t
#define WOW2_EXACT__READ                                            0x0000ffffU
#define WOW2_EXACT__WRITE                                           0x0000ffffU

#endif /* __WOW2_EXACT_MACRO__ */


/* macros for mac_pcu_reg_map.WOW2_EXACT */
#define INST_MAC_PCU_REG_MAP__WOW2_EXACT__NUM                                 1

/* macros for BlueprintGlobalNameSpace::PCU_WOW6 */
#ifndef __PCU_WOW6_MACRO__
#define __PCU_WOW6_MACRO__

/* macros for field OFFSET8 */
#define PCU_WOW6__OFFSET8__SHIFT                                              0
#define PCU_WOW6__OFFSET8__WIDTH                                              8
#define PCU_WOW6__OFFSET8__MASK                                     0x000000ffU
#define PCU_WOW6__OFFSET8__READ(src)             (u_int32_t)(src) & 0x000000ffU
#define PCU_WOW6__OFFSET8__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
#define PCU_WOW6__OFFSET8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define PCU_WOW6__OFFSET8__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field OFFSET9 */
#define PCU_WOW6__OFFSET9__SHIFT                                              8
#define PCU_WOW6__OFFSET9__WIDTH                                              8
#define PCU_WOW6__OFFSET9__MASK                                     0x0000ff00U
#define PCU_WOW6__OFFSET9__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define PCU_WOW6__OFFSET9__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define PCU_WOW6__OFFSET9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define PCU_WOW6__OFFSET9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field OFFSET10 */
#define PCU_WOW6__OFFSET10__SHIFT                                            16
#define PCU_WOW6__OFFSET10__WIDTH                                             8
#define PCU_WOW6__OFFSET10__MASK                                    0x00ff0000U
#define PCU_WOW6__OFFSET10__READ(src)  (((u_int32_t)(src) & 0x00ff0000U) >> 16)
#define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
#define PCU_WOW6__OFFSET10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define PCU_WOW6__OFFSET10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field OFFSET11 */
#define PCU_WOW6__OFFSET11__SHIFT                                            24
#define PCU_WOW6__OFFSET11__WIDTH                                             8
#define PCU_WOW6__OFFSET11__MASK                                    0xff000000U
#define PCU_WOW6__OFFSET11__READ(src)  (((u_int32_t)(src) & 0xff000000U) >> 24)
#define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
#define PCU_WOW6__OFFSET11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define PCU_WOW6__OFFSET11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define PCU_WOW6__TYPE                                                u_int32_t
#define PCU_WOW6__READ                                              0xffffffffU
#define PCU_WOW6__WRITE                                             0xffffffffU

#endif /* __PCU_WOW6_MACRO__ */


/* macros for mac_pcu_reg_map.PCU_WOW6 */
#define INST_MAC_PCU_REG_MAP__PCU_WOW6__NUM                                   1

/* macros for BlueprintGlobalNameSpace::PCU_WOW7 */
#ifndef __PCU_WOW7_MACRO__
#define __PCU_WOW7_MACRO__

/* macros for field OFFSET12 */
#define PCU_WOW7__OFFSET12__SHIFT                                             0
#define PCU_WOW7__OFFSET12__WIDTH                                             8
#define PCU_WOW7__OFFSET12__MASK                                    0x000000ffU
#define PCU_WOW7__OFFSET12__READ(src)            (u_int32_t)(src) & 0x000000ffU
#define PCU_WOW7__OFFSET12__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
#define PCU_WOW7__OFFSET12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define PCU_WOW7__OFFSET12__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field OFFSET13 */
#define PCU_WOW7__OFFSET13__SHIFT                                             8
#define PCU_WOW7__OFFSET13__WIDTH                                             8
#define PCU_WOW7__OFFSET13__MASK                                    0x0000ff00U
#define PCU_WOW7__OFFSET13__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define PCU_WOW7__OFFSET13__WRITE(src)  (((u_int32_t)(src) << 8) & 0x0000ff00U)
#define PCU_WOW7__OFFSET13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define PCU_WOW7__OFFSET13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field OFFSET14 */
#define PCU_WOW7__OFFSET14__SHIFT                                            16
#define PCU_WOW7__OFFSET14__WIDTH                                             8
#define PCU_WOW7__OFFSET14__MASK                                    0x00ff0000U
#define PCU_WOW7__OFFSET14__READ(src)  (((u_int32_t)(src) & 0x00ff0000U) >> 16)
#define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
#define PCU_WOW7__OFFSET14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define PCU_WOW7__OFFSET14__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field OFFSET15 */
#define PCU_WOW7__OFFSET15__SHIFT                                            24
#define PCU_WOW7__OFFSET15__WIDTH                                             8
#define PCU_WOW7__OFFSET15__MASK                                    0xff000000U
#define PCU_WOW7__OFFSET15__READ(src)  (((u_int32_t)(src) & 0xff000000U) >> 24)
#define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
#define PCU_WOW7__OFFSET15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define PCU_WOW7__OFFSET15__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define PCU_WOW7__TYPE                                                u_int32_t
#define PCU_WOW7__READ                                              0xffffffffU
#define PCU_WOW7__WRITE                                             0xffffffffU

#endif /* __PCU_WOW7_MACRO__ */


/* macros for mac_pcu_reg_map.PCU_WOW7 */
#define INST_MAC_PCU_REG_MAP__PCU_WOW7__NUM                                   1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH3 */
#ifndef __MAC_PCU_WOW_LENGTH3_MACRO__
#define __MAC_PCU_WOW_LENGTH3_MACRO__

/* macros for field PATTERN_11 */
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__SHIFT                                0
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WIDTH                                8
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MASK                       0x000000ffU
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field PATTERN_10 */
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__SHIFT                                8
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WIDTH                                8
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MASK                       0x0000ff00U
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field PATTERN_9 */
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__SHIFT                                16
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MASK                        0x00ff0000U
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field PATTERN_8 */
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__SHIFT                                24
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WIDTH                                 8
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MASK                        0xff000000U
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_WOW_LENGTH3__TYPE                                     u_int32_t
#define MAC_PCU_WOW_LENGTH3__READ                                   0xffffffffU
#define MAC_PCU_WOW_LENGTH3__WRITE                                  0xffffffffU

#endif /* __MAC_PCU_WOW_LENGTH3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH3__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH4 */
#ifndef __MAC_PCU_WOW_LENGTH4_MACRO__
#define __MAC_PCU_WOW_LENGTH4_MACRO__

/* macros for field PATTERN_15 */
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__SHIFT                                0
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WIDTH                                8
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MASK                       0x000000ffU
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field PATTERN_14 */
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__SHIFT                                8
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WIDTH                                8
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MASK                       0x0000ff00U
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field PATTERN_13 */
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__SHIFT                               16
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WIDTH                                8
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MASK                       0x00ff0000U
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field PATTERN_12 */
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__SHIFT                               24
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WIDTH                                8
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MASK                       0xff000000U
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_WOW_LENGTH4__TYPE                                     u_int32_t
#define MAC_PCU_WOW_LENGTH4__READ                                   0xffffffffU
#define MAC_PCU_WOW_LENGTH4__WRITE                                  0xffffffffU

#endif /* __MAC_PCU_WOW_LENGTH4_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH4 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH4__NUM                        1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_CONTROL */
#ifndef __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__
#define __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__

/* macros for field ENABLE */
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SHIFT                          0
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WIDTH                          1
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MASK                 0x00000001U
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field UPLOAD_H_DISABLE */
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SHIFT                1
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WIDTH                1
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MASK       0x00000002U
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define MAC_PCU_LOCATION_MODE_CONTROL__TYPE                           u_int32_t
#define MAC_PCU_LOCATION_MODE_CONTROL__READ                         0x00000003U
#define MAC_PCU_LOCATION_MODE_CONTROL__WRITE                        0x00000003U

#endif /* __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_CONTROL */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_CONTROL__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_TIMER */
#ifndef __MAC_PCU_LOCATION_MODE_TIMER_MACRO__
#define __MAC_PCU_LOCATION_MODE_TIMER_MACRO__

/* macros for field VALUE */
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__SHIFT                             0
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WIDTH                            32
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MASK                    0xffffffffU
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_LOCATION_MODE_TIMER__TYPE                             u_int32_t
#define MAC_PCU_LOCATION_MODE_TIMER__READ                           0xffffffffU
#define MAC_PCU_LOCATION_MODE_TIMER__WRITE                          0xffffffffU

#endif /* __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_TIMER */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_TIMER__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_L32 */
#ifndef __MAC_PCU_TSF2_L32_MACRO__
#define __MAC_PCU_TSF2_L32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TSF2_L32__VALUE__SHIFT                                        0
#define MAC_PCU_TSF2_L32__VALUE__WIDTH                                       32
#define MAC_PCU_TSF2_L32__VALUE__MASK                               0xffffffffU
#define MAC_PCU_TSF2_L32__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TSF2_L32__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TSF2_L32__TYPE                                        u_int32_t
#define MAC_PCU_TSF2_L32__READ                                      0xffffffffU
#define MAC_PCU_TSF2_L32__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TSF2_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TSF2_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_L32__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_U32 */
#ifndef __MAC_PCU_TSF2_U32_MACRO__
#define __MAC_PCU_TSF2_U32_MACRO__

/* macros for field VALUE */
#define MAC_PCU_TSF2_U32__VALUE__SHIFT                                        0
#define MAC_PCU_TSF2_U32__VALUE__WIDTH                                       32
#define MAC_PCU_TSF2_U32__VALUE__MASK                               0xffffffffU
#define MAC_PCU_TSF2_U32__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TSF2_U32__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TSF2_U32__TYPE                                        u_int32_t
#define MAC_PCU_TSF2_U32__READ                                      0xffffffffU
#define MAC_PCU_TSF2_U32__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TSF2_U32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TSF2_U32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_U32__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_L32 */
#ifndef __MAC_PCU_BSSID2_L32_MACRO__
#define __MAC_PCU_BSSID2_L32_MACRO__

/* macros for field ADDR */
#define MAC_PCU_BSSID2_L32__ADDR__SHIFT                                       0
#define MAC_PCU_BSSID2_L32__ADDR__WIDTH                                      32
#define MAC_PCU_BSSID2_L32__ADDR__MASK                              0xffffffffU
#define MAC_PCU_BSSID2_L32__ADDR__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_BSSID2_L32__ADDR__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BSSID2_L32__TYPE                                      u_int32_t
#define MAC_PCU_BSSID2_L32__READ                                    0xffffffffU
#define MAC_PCU_BSSID2_L32__WRITE                                   0xffffffffU

#endif /* __MAC_PCU_BSSID2_L32_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_L32 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_L32__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_U16 */
#ifndef __MAC_PCU_BSSID2_U16_MACRO__
#define __MAC_PCU_BSSID2_U16_MACRO__

/* macros for field ADDR */
#define MAC_PCU_BSSID2_U16__ADDR__SHIFT                                       0
#define MAC_PCU_BSSID2_U16__ADDR__WIDTH                                      16
#define MAC_PCU_BSSID2_U16__ADDR__MASK                              0x0000ffffU
#define MAC_PCU_BSSID2_U16__ADDR__READ(src)      (u_int32_t)(src) & 0x0000ffffU
#define MAC_PCU_BSSID2_U16__ADDR__WRITE(src)   ((u_int32_t)(src) & 0x0000ffffU)
#define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field ENABLE */
#define MAC_PCU_BSSID2_U16__ENABLE__SHIFT                                    16
#define MAC_PCU_BSSID2_U16__ENABLE__WIDTH                                     1
#define MAC_PCU_BSSID2_U16__ENABLE__MASK                            0x00010000U
#define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_BSSID2_U16__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_BSSID2_U16__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)
#define MAC_PCU_BSSID2_U16__TYPE                                      u_int32_t
#define MAC_PCU_BSSID2_U16__READ                                    0x0001ffffU
#define MAC_PCU_BSSID2_U16__WRITE                                   0x0001ffffU

#endif /* __MAC_PCU_BSSID2_U16_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_U16 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_U16__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIRECT_CONNECT */
#ifndef __MAC_PCU_DIRECT_CONNECT_MACRO__
#define __MAC_PCU_DIRECT_CONNECT_MACRO__

/* macros for field AP_STA_ENABLE */
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SHIFT                          0
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WIDTH                          1
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MASK                 0x00000001U
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field TBTT_TIMER_0_8_SEL */
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SHIFT                     4
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WIDTH                     1
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MASK            0x00000010U
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field DMA_BALERT_TIMER_1_9_SEL */
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SHIFT               5
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WIDTH               1
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MASK      0x00000020U
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field SW_BALERT_TIMER_2_10_SEL */
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SHIFT               6
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WIDTH               1
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MASK      0x00000040U
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field HCF_TO_TIMER_3_11_SEL */
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SHIFT                  7
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WIDTH                  1
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MASK         0x00000080U
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field NEXT_TIM_TIMER_4_12_SEL */
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SHIFT                8
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WIDTH                1
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MASK       0x00000100U
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field NEXT_DTIM_TIMER_5_13_SEL */
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SHIFT               9
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WIDTH               1
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MASK      0x00000200U
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field QUIET_TM_TIMER_6_14_SEL */
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SHIFT               10
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WIDTH                1
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MASK       0x00000400U
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field TBTT2_TIMER_0_8_SEL */
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SHIFT                   11
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WIDTH                    1
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MASK           0x00000800U
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field AP_TSF_1_2_SEL */
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SHIFT                        12
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WIDTH                         1
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MASK                0x00001000U
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field STA_TSF_1_2_SEL */
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SHIFT                       13
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WIDTH                        1
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MASK               0x00002000U
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field BC_MC_WAPI_MODE2_EN */
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SHIFT                   14
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WIDTH                    1
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MASK           0x00004000U
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field BC_MC_WAPI_MODE_AP_SEL */
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SHIFT                15
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WIDTH                 1
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MASK        0x00008000U
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field DESC_SVD_TSF_SEL_EN */
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SHIFT                   16
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WIDTH                    1
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MASK           0x00010000U
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)
#define MAC_PCU_DIRECT_CONNECT__TYPE                                  u_int32_t
#define MAC_PCU_DIRECT_CONNECT__READ                                0x0001fff1U
#define MAC_PCU_DIRECT_CONNECT__WRITE                               0x0001fff1U

#endif /* __MAC_PCU_DIRECT_CONNECT_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_DIRECT_CONNECT */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_DIRECT_CONNECT__NUM                     1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TID_TO_AC */
#ifndef __MAC_PCU_TID_TO_AC_MACRO__
#define __MAC_PCU_TID_TO_AC_MACRO__

/* macros for field DATA */
#define MAC_PCU_TID_TO_AC__DATA__SHIFT                                        0
#define MAC_PCU_TID_TO_AC__DATA__WIDTH                                       32
#define MAC_PCU_TID_TO_AC__DATA__MASK                               0xffffffffU
#define MAC_PCU_TID_TO_AC__DATA__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TID_TO_AC__DATA__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TID_TO_AC__TYPE                                       u_int32_t
#define MAC_PCU_TID_TO_AC__READ                                     0xffffffffU
#define MAC_PCU_TID_TO_AC__WRITE                                    0xffffffffU

#endif /* __MAC_PCU_TID_TO_AC_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TID_TO_AC */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TID_TO_AC__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_HP_QUEUE */
#ifndef __MAC_PCU_HP_QUEUE_MACRO__
#define __MAC_PCU_HP_QUEUE_MACRO__

/* macros for field ENABLE */
#define MAC_PCU_HP_QUEUE__ENABLE__SHIFT                                       0
#define MAC_PCU_HP_QUEUE__ENABLE__WIDTH                                       1
#define MAC_PCU_HP_QUEUE__ENABLE__MASK                              0x00000001U
#define MAC_PCU_HP_QUEUE__ENABLE__READ(src)      (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
#define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_HP_QUEUE__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_HP_QUEUE__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field AC_MASK_BE */
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SHIFT                                   1
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WIDTH                                   1
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MASK                          0x00000002U
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_HP_QUEUE__AC_MASK_BE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field AC_MASK_BK */
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SHIFT                                   2
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WIDTH                                   1
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MASK                          0x00000004U
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_HP_QUEUE__AC_MASK_BK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field AC_MASK_VI */
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SHIFT                                   3
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WIDTH                                   1
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MASK                          0x00000008U
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_HP_QUEUE__AC_MASK_VI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field AC_MASK_VO */
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SHIFT                                   4
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WIDTH                                   1
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MASK                          0x00000010U
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_HP_QUEUE__AC_MASK_VO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field HPQON_UAPSD */
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SHIFT                                  5
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WIDTH                                  1
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MASK                         0x00000020U
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field FRAME_FILTER_ENABLE0 */
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SHIFT                         6
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WIDTH                         1
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MASK                0x00000040U
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field FRAME_BSSID_MATCH0 */
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SHIFT                           7
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WIDTH                           1
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MASK                  0x00000080U
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field FRAME_TYPE0 */
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__SHIFT                                  8
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WIDTH                                  2
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MASK                         0x00000300U
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field FRAME_TYPE_MASK0 */
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__SHIFT                            10
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WIDTH                             2
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MASK                    0x00000c00U
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))

/* macros for field FRAME_SUBTYPE0 */
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__SHIFT                              12
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WIDTH                               4
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MASK                      0x0000f000U
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field FRAME_SUBTYPE_MASK0 */
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__SHIFT                         16
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WIDTH                          4
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MASK                 0x000f0000U
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field UAPSD_EN */
#define MAC_PCU_HP_QUEUE__UAPSD_EN__SHIFT                                    20
#define MAC_PCU_HP_QUEUE__UAPSD_EN__WIDTH                                     1
#define MAC_PCU_HP_QUEUE__UAPSD_EN__MASK                            0x00100000U
#define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_HP_QUEUE__UAPSD_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_HP_QUEUE__UAPSD_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field PM_CHANGE */
#define MAC_PCU_HP_QUEUE__PM_CHANGE__SHIFT                                   21
#define MAC_PCU_HP_QUEUE__PM_CHANGE__WIDTH                                    1
#define MAC_PCU_HP_QUEUE__PM_CHANGE__MASK                           0x00200000U
#define MAC_PCU_HP_QUEUE__PM_CHANGE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_HP_QUEUE__PM_CHANGE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_HP_QUEUE__PM_CHANGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_HP_QUEUE__PM_CHANGE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_HP_QUEUE__PM_CHANGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_HP_QUEUE__PM_CHANGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field NON_UAPSD_EN */
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SHIFT                                22
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WIDTH                                 1
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MASK                        0x00400000U
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)
#define MAC_PCU_HP_QUEUE__TYPE                                        u_int32_t
#define MAC_PCU_HP_QUEUE__READ                                      0x007fffffU
#define MAC_PCU_HP_QUEUE__WRITE                                     0x007fffffU

#endif /* __MAC_PCU_HP_QUEUE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_HP_QUEUE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_HP_QUEUE__NUM                           1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */
#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__
#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__SHIFT                           0
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WIDTH                          32
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MASK                  0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__TYPE                           u_int32_t
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__READ                         0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__WRITE                        0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS0__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */
#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__
#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__SHIFT                           0
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WIDTH                          32
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MASK                  0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__TYPE                           u_int32_t
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__READ                         0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__WRITE                        0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS1__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */
#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__
#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__SHIFT                           0
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WIDTH                          32
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MASK                  0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__TYPE                           u_int32_t
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__READ                         0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__WRITE                        0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS2__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */
#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__
#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__

/* macros for field VALUE */
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__SHIFT                           0
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WIDTH                          32
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MASK                  0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__TYPE                           u_int32_t
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__READ                         0xffffffffU
#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__WRITE                        0xffffffffU

#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS3__NUM              1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT0 */
#ifndef __MAC_PCU_AGC_SATURATION_CNT0_MACRO__
#define __MAC_PCU_AGC_SATURATION_CNT0_MACRO__

/* macros for field VALUE */
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__SHIFT                             0
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WIDTH                            32
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MASK                    0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_AGC_SATURATION_CNT0__TYPE                             u_int32_t
#define MAC_PCU_AGC_SATURATION_CNT0__READ                           0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT0__WRITE                          0xffffffffU

#endif /* __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT0 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT0__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT1 */
#ifndef __MAC_PCU_AGC_SATURATION_CNT1_MACRO__
#define __MAC_PCU_AGC_SATURATION_CNT1_MACRO__

/* macros for field VALUE */
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__SHIFT                             0
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WIDTH                            32
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MASK                    0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_AGC_SATURATION_CNT1__TYPE                             u_int32_t
#define MAC_PCU_AGC_SATURATION_CNT1__READ                           0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT1__WRITE                          0xffffffffU

#endif /* __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT1__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT2 */
#ifndef __MAC_PCU_AGC_SATURATION_CNT2_MACRO__
#define __MAC_PCU_AGC_SATURATION_CNT2_MACRO__

/* macros for field VALUE */
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__SHIFT                             0
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WIDTH                            32
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MASK                    0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_AGC_SATURATION_CNT2__TYPE                             u_int32_t
#define MAC_PCU_AGC_SATURATION_CNT2__READ                           0xffffffffU
#define MAC_PCU_AGC_SATURATION_CNT2__WRITE                          0xffffffffU

#endif /* __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT2__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC1 */
#ifndef __MAC_PCU_HW_BCN_PROC1_MACRO__
#define __MAC_PCU_HW_BCN_PROC1_MACRO__

/* macros for field CRC_ENABLE */
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SHIFT                               0
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WIDTH                               1
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MASK                      0x00000001U
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field RESET_CRC */
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SHIFT                                1
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WIDTH                                1
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MASK                       0x00000002U
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field EXCLUDE_BCN_INTVL */
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SHIFT                        2
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WIDTH                        1
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MASK               0x00000004U
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field EXCLUDE_CAP_INFO */
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SHIFT                         3
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WIDTH                         1
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MASK                0x00000008U
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field EXCLUDE_TIM_ELM */
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SHIFT                          4
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WIDTH                          1
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MASK                 0x00000010U
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field EXCLUDE_ELM0 */
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SHIFT                             5
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WIDTH                             1
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MASK                    0x00000020U
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field EXCLUDE_ELM1 */
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SHIFT                             6
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WIDTH                             1
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MASK                    0x00000040U
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field EXCLUDE_ELM2 */
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SHIFT                             7
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WIDTH                             1
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MASK                    0x00000080U
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field ELM0_ID */
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__SHIFT                                  8
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WIDTH                                  8
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MASK                         0x0000ff00U
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field ELM1_ID */
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__SHIFT                                 16
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WIDTH                                  8
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MASK                         0x00ff0000U
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field ELM2_ID */
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__SHIFT                                 24
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WIDTH                                  8
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MASK                         0xff000000U
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define MAC_PCU_HW_BCN_PROC1__TYPE                                    u_int32_t
#define MAC_PCU_HW_BCN_PROC1__READ                                  0xffffffffU
#define MAC_PCU_HW_BCN_PROC1__WRITE                                 0xffffffffU

#endif /* __MAC_PCU_HW_BCN_PROC1_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC1 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC1__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC2 */
#ifndef __MAC_PCU_HW_BCN_PROC2_MACRO__
#define __MAC_PCU_HW_BCN_PROC2_MACRO__

/* macros for field FILTER_INTERVAL_ENABLE */
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SHIFT                   0
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WIDTH                   1
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MASK          0x00000001U
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field RESET_INTERVAL */
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SHIFT                           1
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WIDTH                           1
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MASK                  0x00000002U
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field EXCLUDE_ELM3 */
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SHIFT                             2
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WIDTH                             1
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MASK                    0x00000004U
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field FILTER_INTERVAL */
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__SHIFT                          8
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WIDTH                          8
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MASK                 0x0000ff00U
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field ELM3_ID */
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__SHIFT                                 16
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WIDTH                                  8
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MASK                         0x00ff0000U
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))
#define MAC_PCU_HW_BCN_PROC2__TYPE                                    u_int32_t
#define MAC_PCU_HW_BCN_PROC2__READ                                  0x00ffff07U
#define MAC_PCU_HW_BCN_PROC2__WRITE                                 0x00ffff07U

#endif /* __MAC_PCU_HW_BCN_PROC2_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC2 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC2__NUM                       1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE3 */
#ifndef __MAC_PCU_MISC_MODE3_MACRO__
#define __MAC_PCU_MISC_MODE3_MACRO__

/* macros for field BUG_55702_FIX_ENABLE */
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SHIFT                       0
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MASK              0x00000001U
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field AES_3STREAM */
#define MAC_PCU_MISC_MODE3__AES_3STREAM__SHIFT                                1
#define MAC_PCU_MISC_MODE3__AES_3STREAM__WIDTH                                1
#define MAC_PCU_MISC_MODE3__AES_3STREAM__MASK                       0x00000002U
#define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_MISC_MODE3__AES_3STREAM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_MISC_MODE3__AES_3STREAM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field REGULAR_SOUNDING */
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SHIFT                           2
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WIDTH                           1
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MASK                  0x00000004U
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field BUG_58011_FIX_ENABLE */
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SHIFT                       3
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MASK              0x00000008U
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field BUG_56991_FIX_ENABLE */
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SHIFT                       4
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MASK              0x00000010U
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field WOW_ADDR1_MASK_ENABLE */
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SHIFT                      5
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WIDTH                      1
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MASK             0x00000020U
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field BUG_61936_FIX_ENABLE */
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SHIFT                       6
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WIDTH                       1
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MASK              0x00000040U
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field CHECK_LENGTH_FOR_BA */
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SHIFT                        7
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WIDTH                        1
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MASK               0x00000080U
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field BA_FRAME_LENGTH */
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__SHIFT                            8
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WIDTH                            8
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MASK                   0x0000ff00U
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field MATCH_TID_FOR_BA */
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SHIFT                          16
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WIDTH                           1
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MASK                  0x00010000U
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field WAPI_ORDER_MASK */
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SHIFT                           17
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WIDTH                            1
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MASK                   0x00020000U
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field BB_LDPC_EN */
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SHIFT                                18
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WIDTH                                 1
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MASK                        0x00040000U
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field SELF_GEN_SMOOTHING */
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SHIFT                        19
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WIDTH                         1
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MASK                0x00080000U
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field SMOOTHING_FORCE */
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SHIFT                           20
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WIDTH                            1
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MASK                   0x00100000U
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field KEY_MISS_FIX */
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SHIFT                              21
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WIDTH                               1
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MASK                      0x00200000U
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field RESERVED1 */
#define MAC_PCU_MISC_MODE3__RESERVED1__SHIFT                                 22
#define MAC_PCU_MISC_MODE3__RESERVED1__WIDTH                                  4
#define MAC_PCU_MISC_MODE3__RESERVED1__MASK                         0x03c00000U
#define MAC_PCU_MISC_MODE3__RESERVED1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03c00000U) >> 22)
#define MAC_PCU_MISC_MODE3__RESERVED1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x03c00000U)
#define MAC_PCU_MISC_MODE3__RESERVED1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x03c00000U)
#define MAC_PCU_MISC_MODE3__RESERVED1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x03c00000U)))

/* macros for field PHY_ERROR_AIFS_MASK_ENABLE */
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SHIFT                26
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WIDTH                 1
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MASK        0x04000000U
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field RESERVED */
#define MAC_PCU_MISC_MODE3__RESERVED__SHIFT                                  27
#define MAC_PCU_MISC_MODE3__RESERVED__WIDTH                                   3
#define MAC_PCU_MISC_MODE3__RESERVED__MASK                          0x38000000U
#define MAC_PCU_MISC_MODE3__RESERVED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x38000000U) >> 27)
#define MAC_PCU_MISC_MODE3__RESERVED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x38000000U)
#define MAC_PCU_MISC_MODE3__RESERVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x38000000U) | (((u_int32_t)(src) <<\
                    27) & 0x38000000U)
#define MAC_PCU_MISC_MODE3__RESERVED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x38000000U)))

/* macros for field PER_STA_WEP_ENTRY_ENABLE */
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SHIFT                  30
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WIDTH                   1
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MASK          0x40000000U
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field BC_MC_WAPI_MODE2 */
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SHIFT                          31
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WIDTH                           1
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MASK                  0x80000000U
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define MAC_PCU_MISC_MODE3__TYPE                                      u_int32_t
#define MAC_PCU_MISC_MODE3__READ                                    0xffffffffU
#define MAC_PCU_MISC_MODE3__WRITE                                   0xffffffffU

#endif /* __MAC_PCU_MISC_MODE3_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE3 */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE3__NUM                         1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_RSSI_AVE */
#ifndef __MAC_PCU_FILTER_RSSI_AVE_MACRO__
#define __MAC_PCU_FILTER_RSSI_AVE_MACRO__

/* macros for field AVE_VALUE */
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__SHIFT                             0
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WIDTH                             8
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MASK                    0x000000ffU
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field NUM_FRAMES_EXPONENT */
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__SHIFT                   8
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WIDTH                   3
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MASK          0x00000700U
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000700U)
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field ENABLE */
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SHIFT                               11
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WIDTH                                1
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MASK                       0x00000800U
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field RESET */
#define MAC_PCU_FILTER_RSSI_AVE__RESET__SHIFT                                12
#define MAC_PCU_FILTER_RSSI_AVE__RESET__WIDTH                                 1
#define MAC_PCU_FILTER_RSSI_AVE__RESET__MASK                        0x00001000U
#define MAC_PCU_FILTER_RSSI_AVE__RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define MAC_PCU_FILTER_RSSI_AVE__RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define MAC_PCU_FILTER_RSSI_AVE__RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define MAC_PCU_FILTER_RSSI_AVE__RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define MAC_PCU_FILTER_RSSI_AVE__RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define MAC_PCU_FILTER_RSSI_AVE__RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)
#define MAC_PCU_FILTER_RSSI_AVE__TYPE                                 u_int32_t
#define MAC_PCU_FILTER_RSSI_AVE__READ                               0x00001fffU
#define MAC_PCU_FILTER_RSSI_AVE__WRITE                              0x00001fffU

#endif /* __MAC_PCU_FILTER_RSSI_AVE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_RSSI_AVE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_RSSI_AVE__NUM                    1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_AIFS_MASK */
#ifndef __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__
#define __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__

/* macros for field VALUE */
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__SHIFT                             0
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WIDTH                            32
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MASK                    0xffffffffU
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_PHY_ERROR_AIFS_MASK__TYPE                             u_int32_t
#define MAC_PCU_PHY_ERROR_AIFS_MASK__READ                           0xffffffffU
#define MAC_PCU_PHY_ERROR_AIFS_MASK__WRITE                          0xffffffffU

#endif /* __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_AIFS_MASK */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_AIFS_MASK__NUM                1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_PS_FILTER */
#ifndef __MAC_PCU_PS_FILTER_MACRO__
#define __MAC_PCU_PS_FILTER_MACRO__

/* macros for field ENABLE */
#define MAC_PCU_PS_FILTER__ENABLE__SHIFT                                      0
#define MAC_PCU_PS_FILTER__ENABLE__WIDTH                                      1
#define MAC_PCU_PS_FILTER__ENABLE__MASK                             0x00000001U
#define MAC_PCU_PS_FILTER__ENABLE__READ(src)     (u_int32_t)(src) & 0x00000001U
#define MAC_PCU_PS_FILTER__ENABLE__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
#define MAC_PCU_PS_FILTER__ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MAC_PCU_PS_FILTER__ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MAC_PCU_PS_FILTER__ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MAC_PCU_PS_FILTER__ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field PS_SAVE_ENABLE */
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SHIFT                              1
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WIDTH                              1
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MASK                     0x00000002U
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define MAC_PCU_PS_FILTER__TYPE                                       u_int32_t
#define MAC_PCU_PS_FILTER__READ                                     0x00000003U
#define MAC_PCU_PS_FILTER__WRITE                                    0x00000003U

#endif /* __MAC_PCU_PS_FILTER_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_PS_FILTER */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_PS_FILTER__NUM                          1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_BA */
#ifndef __MAC_PCU_TXBUF_BA_MACRO__
#define __MAC_PCU_TXBUF_BA_MACRO__

/* macros for field DATA */
#define MAC_PCU_TXBUF_BA__DATA__SHIFT                                         0
#define MAC_PCU_TXBUF_BA__DATA__WIDTH                                        32
#define MAC_PCU_TXBUF_BA__DATA__MASK                                0xffffffffU
#define MAC_PCU_TXBUF_BA__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_TXBUF_BA__DATA__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_TXBUF_BA__TYPE                                        u_int32_t
#define MAC_PCU_TXBUF_BA__READ                                      0xffffffffU
#define MAC_PCU_TXBUF_BA__WRITE                                     0xffffffffU

#endif /* __MAC_PCU_TXBUF_BA_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_BA */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_BA__NUM                          64

/* macros for BlueprintGlobalNameSpace::MAC_PCU_KEY_CACHE */
#ifndef __MAC_PCU_KEY_CACHE_MACRO__
#define __MAC_PCU_KEY_CACHE_MACRO__

/* macros for field DATA */
#define MAC_PCU_KEY_CACHE__DATA__SHIFT                                        0
#define MAC_PCU_KEY_CACHE__DATA__WIDTH                                       32
#define MAC_PCU_KEY_CACHE__DATA__MASK                               0xffffffffU
#define MAC_PCU_KEY_CACHE__DATA__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_KEY_CACHE__DATA__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define MAC_PCU_KEY_CACHE__TYPE                                       u_int32_t
#define MAC_PCU_KEY_CACHE__READ                                     0xffffffffU
#define MAC_PCU_KEY_CACHE__WRITE                                    0xffffffffU

#endif /* __MAC_PCU_KEY_CACHE_MACRO__ */


/* macros for mac_pcu_reg_map.MAC_PCU_KEY_CACHE */
#define INST_MAC_PCU_REG_MAP__MAC_PCU_KEY_CACHE__NUM                       1024

/* macros for BlueprintGlobalNameSpace::timing_controls_1 */
#ifndef __TIMING_CONTROLS_1_MACRO__
#define __TIMING_CONTROLS_1_MACRO__

/* macros for field ste_thr */
#define TIMING_CONTROLS_1__STE_THR__SHIFT                                     0
#define TIMING_CONTROLS_1__STE_THR__WIDTH                                     7
#define TIMING_CONTROLS_1__STE_THR__MASK                            0x0000007fU
#define TIMING_CONTROLS_1__STE_THR__READ(src)    (u_int32_t)(src) & 0x0000007fU
#define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU)
#define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field ste_to_long1 */
#define TIMING_CONTROLS_1__STE_TO_LONG1__SHIFT                                7
#define TIMING_CONTROLS_1__STE_TO_LONG1__WIDTH                                6
#define TIMING_CONTROLS_1__STE_TO_LONG1__MASK                       0x00001f80U
#define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f80U) >> 7)
#define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00001f80U)
#define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00001f80U)
#define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00001f80U)))

/* macros for field timing_backoff */
#define TIMING_CONTROLS_1__TIMING_BACKOFF__SHIFT                             13
#define TIMING_CONTROLS_1__TIMING_BACKOFF__WIDTH                              4
#define TIMING_CONTROLS_1__TIMING_BACKOFF__MASK                     0x0001e000U
#define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001e000U) >> 13)
#define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0001e000U)
#define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0001e000U)
#define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0001e000U)))

/* macros for field enable_ht_fine_ppm */
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SHIFT                         17
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WIDTH                          1
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MASK                 0x00020000U
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field ht_fine_ppm_stream */
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__SHIFT                         18
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WIDTH                          2
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MASK                 0x000c0000U
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000c0000U) >> 18)
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x000c0000U)
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x000c0000U)
#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x000c0000U)))

/* macros for field ht_fine_ppm_qam */
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__SHIFT                            20
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WIDTH                             2
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MASK                    0x00300000U
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00300000U) >> 20)
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00300000U)
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00300000U) | (((u_int32_t)(src) <<\
                    20) & 0x00300000U)
#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00300000U)))

/* macros for field enable_long_chanfil */
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SHIFT                        22
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WIDTH                         1
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MASK                0x00400000U
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field enable_rx_stbc */
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SHIFT                             23
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WIDTH                              1
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MASK                     0x00800000U
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TIMING_CONTROLS_1__ENABLE_RX_STBC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field enable_channel_filter */
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SHIFT                      24
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WIDTH                       1
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MASK              0x01000000U
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field false_alarm */
#define TIMING_CONTROLS_1__FALSE_ALARM__SHIFT                                25
#define TIMING_CONTROLS_1__FALSE_ALARM__WIDTH                                 2
#define TIMING_CONTROLS_1__FALSE_ALARM__MASK                        0x06000000U
#define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x06000000U) >> 25)
#define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x06000000U)
#define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x06000000U) | (((u_int32_t)(src) <<\
                    25) & 0x06000000U)
#define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x06000000U)))

/* macros for field enable_long_rescale */
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SHIFT                        27
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WIDTH                         1
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MASK                0x08000000U
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field timing_leak_enable */
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SHIFT                         28
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WIDTH                          1
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MASK                 0x10000000U
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field coarse_ppm_select */
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__SHIFT                          29
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WIDTH                           2
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MASK                  0x60000000U
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x60000000U) >> 29)
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x60000000U)
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x60000000U) | (((u_int32_t)(src) <<\
                    29) & 0x60000000U)
#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x60000000U)))

/* macros for field fft_scaling */
#define TIMING_CONTROLS_1__FFT_SCALING__SHIFT                                31
#define TIMING_CONTROLS_1__FFT_SCALING__WIDTH                                 1
#define TIMING_CONTROLS_1__FFT_SCALING__MASK                        0x80000000U
#define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TIMING_CONTROLS_1__FFT_SCALING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TIMING_CONTROLS_1__FFT_SCALING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TIMING_CONTROLS_1__TYPE                                       u_int32_t
#define TIMING_CONTROLS_1__READ                                     0xffffffffU
#define TIMING_CONTROLS_1__WRITE                                    0xffffffffU

#endif /* __TIMING_CONTROLS_1_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_1 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_1__NUM            1

/* macros for BlueprintGlobalNameSpace::timing_controls_2 */
#ifndef __TIMING_CONTROLS_2_MACRO__
#define __TIMING_CONTROLS_2_MACRO__

/* macros for field forced_delta_phi_symbol */
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__SHIFT                     0
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WIDTH                    12
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MASK            0x00000fffU
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000fffU)
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field force_delta_phi_symbol */
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SHIFT                     12
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WIDTH                      1
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MASK             0x00001000U
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field enable_magnitude_track */
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SHIFT                     13
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WIDTH                      1
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MASK             0x00002000U
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field enable_slope_filter */
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SHIFT                        14
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WIDTH                         1
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MASK                0x00004000U
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field enable_offset_filter */
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SHIFT                       15
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WIDTH                        1
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MASK               0x00008000U
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field dc_off_deltaf_thres */
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__SHIFT                        16
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WIDTH                         7
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MASK                0x007f0000U
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x007f0000U)
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x007f0000U)
#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x007f0000U)))

/* macros for field dc_off_tim_const */
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__SHIFT                           24
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WIDTH                            3
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MASK                   0x07000000U
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07000000U) >> 24)
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x07000000U)
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((u_int32_t)(src) <<\
                    24) & 0x07000000U)
#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x07000000U)))

/* macros for field enable_dc_offset */
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SHIFT                           27
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WIDTH                            1
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MASK                   0x08000000U
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field enable_dc_offset_track */
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SHIFT                     28
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WIDTH                      1
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MASK             0x10000000U
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field enable_weighting */
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SHIFT                           29
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WIDTH                            1
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MASK                   0x20000000U
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field traceback128 */
#define TIMING_CONTROLS_2__TRACEBACK128__SHIFT                               30
#define TIMING_CONTROLS_2__TRACEBACK128__WIDTH                                1
#define TIMING_CONTROLS_2__TRACEBACK128__MASK                       0x40000000U
#define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define TIMING_CONTROLS_2__TRACEBACK128__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define TIMING_CONTROLS_2__TRACEBACK128__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field enable_ht_fine_timing */
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SHIFT                      31
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WIDTH                       1
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MASK              0x80000000U
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TIMING_CONTROLS_2__TYPE                                       u_int32_t
#define TIMING_CONTROLS_2__READ                                     0xff7fffffU
#define TIMING_CONTROLS_2__WRITE                                    0xff7fffffU

#endif /* __TIMING_CONTROLS_2_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_2 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_2__NUM            1

/* macros for BlueprintGlobalNameSpace::timing_controls_3 */
#ifndef __TIMING_CONTROLS_3_MACRO__
#define __TIMING_CONTROLS_3_MACRO__

/* macros for field ppm_rescue_interval */
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__SHIFT                         0
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WIDTH                         8
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MASK                0x000000ffU
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field enable_ppm_rescue */
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SHIFT                           8
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WIDTH                           1
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MASK                  0x00000100U
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field enable_fine_ppm */
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SHIFT                             9
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WIDTH                             1
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MASK                    0x00000200U
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field enable_fine_interp */
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SHIFT                         10
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WIDTH                          1
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MASK                 0x00000400U
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field continuous_ppm_rescue */
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SHIFT                      11
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WIDTH                       1
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MASK              0x00000800U
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field enable_df_chanest */
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SHIFT                          12
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WIDTH                           1
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MASK                  0x00001000U
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field delta_slope_coef_exp */
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__SHIFT                       13
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WIDTH                        4
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MASK               0x0001e000U
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001e000U) >> 13)
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0001e000U)
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0001e000U)
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0001e000U)))

/* macros for field delta_slope_coef_man */
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__SHIFT                       17
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WIDTH                       15
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MASK               0xfffe0000U
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0xfffe0000U)
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffe0000U) | (((u_int32_t)(src) <<\
                    17) & 0xfffe0000U)
#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0xfffe0000U)))
#define TIMING_CONTROLS_3__TYPE                                       u_int32_t
#define TIMING_CONTROLS_3__READ                                     0xffffffffU
#define TIMING_CONTROLS_3__WRITE                                    0xffffffffU

#endif /* __TIMING_CONTROLS_3_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_3 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_3__NUM            1

/* macros for BlueprintGlobalNameSpace::timing_control_4 */
#ifndef __TIMING_CONTROL_4_MACRO__
#define __TIMING_CONTROL_4_MACRO__

/* macros for field cal_lg_count_max */
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__SHIFT                            12
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WIDTH                             4
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MASK                    0x0000f000U
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field do_gain_dc_iq_cal */
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SHIFT                           16
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WIDTH                            1
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MASK                   0x00010000U
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field use_pilot_track_df */
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__SHIFT                          17
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WIDTH                           4
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MASK                  0x001e0000U
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001e0000U) >> 17)
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x001e0000U)
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x001e0000U)
#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x001e0000U)))

/* macros for field early_trigger_thr */
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__SHIFT                           21
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WIDTH                            7
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MASK                   0x0fe00000U
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fe00000U) >> 21)
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x0fe00000U)
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x0fe00000U)
#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x0fe00000U)))

/* macros for field enable_pilot_mask */
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SHIFT                           28
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WIDTH                            1
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MASK                   0x10000000U
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field enable_chan_mask */
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SHIFT                            29
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WIDTH                             1
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MASK                    0x20000000U
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field enable_spur_filter */
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SHIFT                          30
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WIDTH                           1
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MASK                  0x40000000U
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field enable_spur_rssi */
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SHIFT                            31
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WIDTH                             1
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MASK                    0x80000000U
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TIMING_CONTROL_4__TYPE                                        u_int32_t
#define TIMING_CONTROL_4__READ                                      0xfffff000U
#define TIMING_CONTROL_4__WRITE                                     0xfffff000U

#endif /* __TIMING_CONTROL_4_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_4 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_4__NUM             1

/* macros for BlueprintGlobalNameSpace::timing_control_5 */
#ifndef __TIMING_CONTROL_5_MACRO__
#define __TIMING_CONTROL_5_MACRO__

/* macros for field enable_cycpwr_thr1 */
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SHIFT                           0
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WIDTH                           1
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MASK                  0x00000001U
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cycpwr_thr1 */
#define TIMING_CONTROL_5__CYCPWR_THR1__SHIFT                                  1
#define TIMING_CONTROL_5__CYCPWR_THR1__WIDTH                                  7
#define TIMING_CONTROL_5__CYCPWR_THR1__MASK                         0x000000feU
#define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000feU) >> 1)
#define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000000feU)
#define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000feU) | (((u_int32_t)(src) <<\
                    1) & 0x000000feU)
#define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000000feU)))

/* macros for field enable_rssi_thr1a */
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SHIFT                           15
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WIDTH                            1
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MASK                   0x00008000U
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field rssi_thr1a */
#define TIMING_CONTROL_5__RSSI_THR1A__SHIFT                                  16
#define TIMING_CONTROL_5__RSSI_THR1A__WIDTH                                   7
#define TIMING_CONTROL_5__RSSI_THR1A__MASK                          0x007f0000U
#define TIMING_CONTROL_5__RSSI_THR1A__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)
#define TIMING_CONTROL_5__RSSI_THR1A__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x007f0000U)
#define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x007f0000U)
#define TIMING_CONTROL_5__RSSI_THR1A__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x007f0000U)))

/* macros for field long_sc_thresh_hi_rssi */
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__SHIFT                      23
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WIDTH                       7
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MASK              0x3f800000U
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f800000U) >> 23)
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x3f800000U)
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))

/* macros for field forced_agc_str_pri */
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SHIFT                          30
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WIDTH                           1
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MASK                  0x40000000U
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field forced_agc_str_pri_en */
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SHIFT                       31
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WIDTH                        1
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MASK               0x80000000U
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TIMING_CONTROL_5__TYPE                                        u_int32_t
#define TIMING_CONTROL_5__READ                                      0xffff80ffU
#define TIMING_CONTROL_5__WRITE                                     0xffff80ffU

#endif /* __TIMING_CONTROL_5_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_5 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_5__NUM             1

/* macros for BlueprintGlobalNameSpace::timing_control_6 */
#ifndef __TIMING_CONTROL_6_MACRO__
#define __TIMING_CONTROL_6_MACRO__

/* macros for field hi_rssi_thresh */
#define TIMING_CONTROL_6__HI_RSSI_THRESH__SHIFT                               0
#define TIMING_CONTROL_6__HI_RSSI_THRESH__WIDTH                               8
#define TIMING_CONTROL_6__HI_RSSI_THRESH__MASK                      0x000000ffU
#define TIMING_CONTROL_6__HI_RSSI_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define TIMING_CONTROL_6__HI_RSSI_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TIMING_CONTROL_6__HI_RSSI_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field early_trigger_thr_hi_rssi */
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__SHIFT                    8
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WIDTH                    7
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MASK           0x00007f00U
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007f00U) >> 8)
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00007f00U)
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00007f00U)
#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00007f00U)))

/* macros for field ofdm_xcorr_thresh */
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__SHIFT                           15
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WIDTH                            6
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MASK                   0x001f8000U
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f8000U) >> 15)
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x001f8000U)
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x001f8000U)
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x001f8000U)))

/* macros for field ofdm_xcorr_thresh_hi_rssi */
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__SHIFT                   21
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WIDTH                    7
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MASK           0x0fe00000U
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fe00000U) >> 21)
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x0fe00000U)
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x0fe00000U)
#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x0fe00000U)))

/* macros for field long_medium_ratio_thr */
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__SHIFT                       28
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WIDTH                        4
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MASK               0xf0000000U
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf0000000U) >> 28)
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0xf0000000U)
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((u_int32_t)(src) <<\
                    28) & 0xf0000000U)
#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define TIMING_CONTROL_6__TYPE                                        u_int32_t
#define TIMING_CONTROL_6__READ                                      0xffffffffU
#define TIMING_CONTROL_6__WRITE                                     0xffffffffU

#endif /* __TIMING_CONTROL_6_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_6 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_6__NUM             1

/* macros for BlueprintGlobalNameSpace::timing_control_11 */
#ifndef __TIMING_CONTROL_11_MACRO__
#define __TIMING_CONTROL_11_MACRO__

/* macros for field spur_delta_phase */
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__SHIFT                            0
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WIDTH                           20
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MASK                   0x000fffffU
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000fffffU
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000fffffU)
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fffffU) | ((u_int32_t)(src) &\
                    0x000fffffU)
#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000fffffU)))

/* macros for field spur_freq_sd */
#define TIMING_CONTROL_11__SPUR_FREQ_SD__SHIFT                               20
#define TIMING_CONTROL_11__SPUR_FREQ_SD__WIDTH                               10
#define TIMING_CONTROL_11__SPUR_FREQ_SD__MASK                       0x3ff00000U
#define TIMING_CONTROL_11__SPUR_FREQ_SD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3ff00000U) >> 20)
#define TIMING_CONTROL_11__SPUR_FREQ_SD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x3ff00000U)
#define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
                    20) & 0x3ff00000U)
#define TIMING_CONTROL_11__SPUR_FREQ_SD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x3ff00000U)))

/* macros for field use_spur_filter_in_agc */
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SHIFT                     30
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WIDTH                      1
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MASK             0x40000000U
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field use_spur_filter_in_selfcor */
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SHIFT                 31
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WIDTH                  1
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MASK         0x80000000U
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TIMING_CONTROL_11__TYPE                                       u_int32_t
#define TIMING_CONTROL_11__READ                                     0xffffffffU
#define TIMING_CONTROL_11__WRITE                                    0xffffffffU

#endif /* __TIMING_CONTROL_11_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_11 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_11__NUM            1

/* macros for BlueprintGlobalNameSpace::spur_mask_controls */
#ifndef __SPUR_MASK_CONTROLS_MACRO__
#define __SPUR_MASK_CONTROLS_MACRO__

/* macros for field spur_rssi_thresh */
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__SHIFT                           0
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WIDTH                           8
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MASK                  0x000000ffU
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field en_vit_spur_rssi */
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SHIFT                           8
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WIDTH                           1
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MASK                  0x00000100U
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field enable_mask_ppm */
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SHIFT                           17
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WIDTH                            1
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MASK                   0x00020000U
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field mask_rate_cntl */
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__SHIFT                            18
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WIDTH                             8
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MASK                    0x03fc0000U
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03fc0000U) >> 18)
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x03fc0000U)
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x03fc0000U)
#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x03fc0000U)))

/* macros for field enable_nf_rssi_spur_mit */
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SHIFT                   26
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WIDTH                    1
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MASK           0x04000000U
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)
#define SPUR_MASK_CONTROLS__TYPE                                      u_int32_t
#define SPUR_MASK_CONTROLS__READ                                    0x07fe01ffU
#define SPUR_MASK_CONTROLS__WRITE                                   0x07fe01ffU

#endif /* __SPUR_MASK_CONTROLS_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_spur_mask_controls */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SPUR_MASK_CONTROLS__NUM           1

/* macros for BlueprintGlobalNameSpace::find_signal_low */
#ifndef __FIND_SIGNAL_LOW_MACRO__
#define __FIND_SIGNAL_LOW_MACRO__

/* macros for field relstep_low */
#define FIND_SIGNAL_LOW__RELSTEP_LOW__SHIFT                                   0
#define FIND_SIGNAL_LOW__RELSTEP_LOW__WIDTH                                   6
#define FIND_SIGNAL_LOW__RELSTEP_LOW__MASK                          0x0000003fU
#define FIND_SIGNAL_LOW__RELSTEP_LOW__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define FIND_SIGNAL_LOW__RELSTEP_LOW__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define FIND_SIGNAL_LOW__RELSTEP_LOW__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field firstep_low */
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__SHIFT                                   6
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WIDTH                                   6
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MASK                          0x00000fc0U
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define FIND_SIGNAL_LOW__FIRSTEP_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field firpwr_low */
#define FIND_SIGNAL_LOW__FIRPWR_LOW__SHIFT                                   12
#define FIND_SIGNAL_LOW__FIRPWR_LOW__WIDTH                                    8
#define FIND_SIGNAL_LOW__FIRPWR_LOW__MASK                           0x000ff000U
#define FIND_SIGNAL_LOW__FIRPWR_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ff000U) >> 12)
#define FIND_SIGNAL_LOW__FIRPWR_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x000ff000U)
#define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x000ff000U)
#define FIND_SIGNAL_LOW__FIRPWR_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x000ff000U)))

/* macros for field ycok_max_low */
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__SHIFT                                 20
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WIDTH                                  4
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MASK                         0x00f00000U
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00f00000U) >> 20)
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00f00000U)
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x00f00000U)
#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field long_sc_thresh */
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__SHIFT                               24
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WIDTH                                7
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MASK                       0x7f000000U
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7f000000U) >> 24)
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x7f000000U)
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define FIND_SIGNAL_LOW__LONG_SC_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))
#define FIND_SIGNAL_LOW__TYPE                                         u_int32_t
#define FIND_SIGNAL_LOW__READ                                       0x7fffffffU
#define FIND_SIGNAL_LOW__WRITE                                      0x7fffffffU

#endif /* __FIND_SIGNAL_LOW_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_find_signal_low */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_FIND_SIGNAL_LOW__NUM              1

/* macros for BlueprintGlobalNameSpace::sfcorr */
#ifndef __SFCORR_MACRO__
#define __SFCORR_MACRO__

/* macros for field m2count_thr */
#define SFCORR__M2COUNT_THR__SHIFT                                            0
#define SFCORR__M2COUNT_THR__WIDTH                                            5
#define SFCORR__M2COUNT_THR__MASK                                   0x0000001fU
#define SFCORR__M2COUNT_THR__READ(src)           (u_int32_t)(src) & 0x0000001fU
#define SFCORR__M2COUNT_THR__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
#define SFCORR__M2COUNT_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define SFCORR__M2COUNT_THR__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))

/* macros for field adcsat_thresh */
#define SFCORR__ADCSAT_THRESH__SHIFT                                          5
#define SFCORR__ADCSAT_THRESH__WIDTH                                          6
#define SFCORR__ADCSAT_THRESH__MASK                                 0x000007e0U
#define SFCORR__ADCSAT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000007e0U) >> 5)
#define SFCORR__ADCSAT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000007e0U)
#define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000007e0U)
#define SFCORR__ADCSAT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000007e0U)))

/* macros for field adcsat_icount */
#define SFCORR__ADCSAT_ICOUNT__SHIFT                                         11
#define SFCORR__ADCSAT_ICOUNT__WIDTH                                          6
#define SFCORR__ADCSAT_ICOUNT__MASK                                 0x0001f800U
#define SFCORR__ADCSAT_ICOUNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f800U) >> 11)
#define SFCORR__ADCSAT_ICOUNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x0001f800U)
#define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f800U) | (((u_int32_t)(src) <<\
                    11) & 0x0001f800U)
#define SFCORR__ADCSAT_ICOUNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x0001f800U)))

/* macros for field m1_thres */
#define SFCORR__M1_THRES__SHIFT                                              17
#define SFCORR__M1_THRES__WIDTH                                               7
#define SFCORR__M1_THRES__MASK                                      0x00fe0000U
#define SFCORR__M1_THRES__READ(src)    (((u_int32_t)(src) & 0x00fe0000U) >> 17)
#define SFCORR__M1_THRES__WRITE(src)   (((u_int32_t)(src) << 17) & 0x00fe0000U)
#define SFCORR__M1_THRES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x00fe0000U)
#define SFCORR__M1_THRES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00fe0000U)))

/* macros for field m2_thres */
#define SFCORR__M2_THRES__SHIFT                                              24
#define SFCORR__M2_THRES__WIDTH                                               7
#define SFCORR__M2_THRES__MASK                                      0x7f000000U
#define SFCORR__M2_THRES__READ(src)    (((u_int32_t)(src) & 0x7f000000U) >> 24)
#define SFCORR__M2_THRES__WRITE(src)   (((u_int32_t)(src) << 24) & 0x7f000000U)
#define SFCORR__M2_THRES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define SFCORR__M2_THRES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))
#define SFCORR__TYPE                                                  u_int32_t
#define SFCORR__READ                                                0x7fffffffU
#define SFCORR__WRITE                                               0x7fffffffU

#endif /* __SFCORR_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_sfcorr */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SFCORR__NUM                       1

/* macros for BlueprintGlobalNameSpace::self_corr_low */
#ifndef __SELF_CORR_LOW_MACRO__
#define __SELF_CORR_LOW_MACRO__

/* macros for field use_self_corr_low */
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SHIFT                               0
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WIDTH                               1
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MASK                      0x00000001U
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SELF_CORR_LOW__USE_SELF_CORR_LOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field m1count_max_low */
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__SHIFT                                 1
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WIDTH                                 7
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MASK                        0x000000feU
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000feU) >> 1)
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000000feU)
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000feU) | (((u_int32_t)(src) <<\
                    1) & 0x000000feU)
#define SELF_CORR_LOW__M1COUNT_MAX_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000000feU)))

/* macros for field m2count_thr_low */
#define SELF_CORR_LOW__M2COUNT_THR_LOW__SHIFT                                 8
#define SELF_CORR_LOW__M2COUNT_THR_LOW__WIDTH                                 6
#define SELF_CORR_LOW__M2COUNT_THR_LOW__MASK                        0x00003f00U
#define SELF_CORR_LOW__M2COUNT_THR_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define SELF_CORR_LOW__M2COUNT_THR_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define SELF_CORR_LOW__M2COUNT_THR_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field m1_thresh_low */
#define SELF_CORR_LOW__M1_THRESH_LOW__SHIFT                                  14
#define SELF_CORR_LOW__M1_THRESH_LOW__WIDTH                                   7
#define SELF_CORR_LOW__M1_THRESH_LOW__MASK                          0x001fc000U
#define SELF_CORR_LOW__M1_THRESH_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001fc000U) >> 14)
#define SELF_CORR_LOW__M1_THRESH_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x001fc000U)
#define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x001fc000U)
#define SELF_CORR_LOW__M1_THRESH_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x001fc000U)))

/* macros for field m2_thresh_low */
#define SELF_CORR_LOW__M2_THRESH_LOW__SHIFT                                  21
#define SELF_CORR_LOW__M2_THRESH_LOW__WIDTH                                   7
#define SELF_CORR_LOW__M2_THRESH_LOW__MASK                          0x0fe00000U
#define SELF_CORR_LOW__M2_THRESH_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fe00000U) >> 21)
#define SELF_CORR_LOW__M2_THRESH_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x0fe00000U)
#define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x0fe00000U)
#define SELF_CORR_LOW__M2_THRESH_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x0fe00000U)))
#define SELF_CORR_LOW__TYPE                                           u_int32_t
#define SELF_CORR_LOW__READ                                         0x0fffffffU
#define SELF_CORR_LOW__WRITE                                        0x0fffffffU

#endif /* __SELF_CORR_LOW_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_self_corr_low */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SELF_CORR_LOW__NUM                1

/* macros for BlueprintGlobalNameSpace::ext_chan_scorr_thr */
#ifndef __EXT_CHAN_SCORR_THR_MACRO__
#define __EXT_CHAN_SCORR_THR_MACRO__

/* macros for field m1_thres_ext */
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__SHIFT                               0
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WIDTH                               7
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MASK                      0x0000007fU
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field m2_thres_ext */
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__SHIFT                               7
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WIDTH                               7
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MASK                      0x00003f80U
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f80U) >> 7)
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00003f80U)
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00003f80U)
#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00003f80U)))

/* macros for field m1_thres_low_ext */
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__SHIFT                          14
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WIDTH                           7
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MASK                  0x001fc000U
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001fc000U) >> 14)
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x001fc000U)
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x001fc000U)
#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x001fc000U)))

/* macros for field m2_thres_low_ext */
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__SHIFT                          21
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WIDTH                           7
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MASK                  0x0fe00000U
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fe00000U) >> 21)
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x0fe00000U)
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x0fe00000U)
#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x0fe00000U)))

/* macros for field spur_subchannel_sd */
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SHIFT                        28
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WIDTH                         1
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MASK                0x10000000U
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)
#define EXT_CHAN_SCORR_THR__TYPE                                      u_int32_t
#define EXT_CHAN_SCORR_THR__READ                                    0x1fffffffU
#define EXT_CHAN_SCORR_THR__WRITE                                   0x1fffffffU

#endif /* __EXT_CHAN_SCORR_THR_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_ext_chan_scorr_thr */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXT_CHAN_SCORR_THR__NUM           1

/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b0 */
#ifndef __EXT_CHAN_PWR_THR_2_B0_MACRO__
#define __EXT_CHAN_PWR_THR_2_B0_MACRO__

/* macros for field cf_maxCCApwr_ext_0 */
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__SHIFT                      0
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WIDTH                      9
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MASK             0x000001ffU
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field cycpwr_thr1_ext */
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__SHIFT                         9
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WIDTH                         7
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MASK                0x0000fe00U
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fe00U) >> 9)
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x0000fe00U)
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fe00U) | (((u_int32_t)(src) <<\
                    9) & 0x0000fe00U)
#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x0000fe00U)))

/* macros for field minCCApwr_ext_0 */
#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__SHIFT                        16
#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__WIDTH                         9
#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__MASK                0x01ff0000U
#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01ff0000U) >> 16)
#define EXT_CHAN_PWR_THR_2_B0__TYPE                                   u_int32_t
#define EXT_CHAN_PWR_THR_2_B0__READ                                 0x01ffffffU
#define EXT_CHAN_PWR_THR_2_B0__WRITE                                0x01ffffffU

#endif /* __EXT_CHAN_PWR_THR_2_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_ext_chan_pwr_thr_2_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B0__NUM        1

/* macros for BlueprintGlobalNameSpace::radar_detection */
#ifndef __RADAR_DETECTION_MACRO__
#define __RADAR_DETECTION_MACRO__

/* macros for field pulse_detect_enable */
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SHIFT                           0
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WIDTH                           1
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MASK                  0x00000001U
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RADAR_DETECTION__PULSE_DETECT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field pulse_in_band_thresh */
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__SHIFT                          1
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WIDTH                          5
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MASK                 0x0000003eU
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003eU) >> 1)
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000003eU)
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000003eU)
#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000003eU)))

/* macros for field pulse_rssi_thresh */
#define RADAR_DETECTION__PULSE_RSSI_THRESH__SHIFT                             6
#define RADAR_DETECTION__PULSE_RSSI_THRESH__WIDTH                             6
#define RADAR_DETECTION__PULSE_RSSI_THRESH__MASK                    0x00000fc0U
#define RADAR_DETECTION__PULSE_RSSI_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define RADAR_DETECTION__PULSE_RSSI_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define RADAR_DETECTION__PULSE_RSSI_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field pulse_height_thresh */
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__SHIFT                          12
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WIDTH                           6
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MASK                  0x0003f000U
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field radar_rssi_thresh */
#define RADAR_DETECTION__RADAR_RSSI_THRESH__SHIFT                            18
#define RADAR_DETECTION__RADAR_RSSI_THRESH__WIDTH                             6
#define RADAR_DETECTION__RADAR_RSSI_THRESH__MASK                    0x00fc0000U
#define RADAR_DETECTION__RADAR_RSSI_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define RADAR_DETECTION__RADAR_RSSI_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00fc0000U)
#define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define RADAR_DETECTION__RADAR_RSSI_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field radar_firpwr_thresh */
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__SHIFT                          24
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WIDTH                           7
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MASK                  0x7f000000U
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7f000000U) >> 24)
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x7f000000U)
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))

/* macros for field enable_radar_fft */
#define RADAR_DETECTION__ENABLE_RADAR_FFT__SHIFT                             31
#define RADAR_DETECTION__ENABLE_RADAR_FFT__WIDTH                              1
#define RADAR_DETECTION__ENABLE_RADAR_FFT__MASK                     0x80000000U
#define RADAR_DETECTION__ENABLE_RADAR_FFT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define RADAR_DETECTION__ENABLE_RADAR_FFT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RADAR_DETECTION__ENABLE_RADAR_FFT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RADAR_DETECTION__ENABLE_RADAR_FFT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RADAR_DETECTION__ENABLE_RADAR_FFT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RADAR_DETECTION__TYPE                                         u_int32_t
#define RADAR_DETECTION__READ                                       0xffffffffU
#define RADAR_DETECTION__WRITE                                      0xffffffffU

#endif /* __RADAR_DETECTION_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_radar_detection */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RADAR_DETECTION__NUM              1

/* macros for BlueprintGlobalNameSpace::radar_detection_2 */
#ifndef __RADAR_DETECTION_2_MACRO__
#define __RADAR_DETECTION_2_MACRO__

/* macros for field radar_length_max */
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__SHIFT                            0
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WIDTH                            8
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MASK                   0x000000ffU
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field pulse_relstep_thresh */
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__SHIFT                        8
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WIDTH                        5
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MASK               0x00001f00U
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00001f00U)
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00001f00U)
#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00001f00U)))

/* macros for field enable_pulse_relstep_check */
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SHIFT                 13
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WIDTH                  1
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MASK         0x00002000U
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field enable_max_radar_rssi */
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SHIFT                      14
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WIDTH                       1
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MASK              0x00004000U
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field enable_block_radar_check */
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SHIFT                   15
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WIDTH                    1
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MASK           0x00008000U
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field radar_relpwr_thresh */
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__SHIFT                        16
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WIDTH                         6
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MASK                0x003f0000U
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field radar_use_firpwr_128 */
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SHIFT                       22
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WIDTH                        1
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MASK               0x00400000U
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field enable_radar_relpwr_check */
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SHIFT                  23
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WIDTH                   1
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MASK          0x00800000U
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field cf_radar_bin_thresh_sel */
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__SHIFT                    24
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WIDTH                     3
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MASK            0x07000000U
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07000000U) >> 24)
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x07000000U)
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((u_int32_t)(src) <<\
                    24) & 0x07000000U)
#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x07000000U)))

/* macros for field enable_pulse_gc_count_check */
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SHIFT                27
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WIDTH                 1
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MASK        0x08000000U
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)
#define RADAR_DETECTION_2__TYPE                                       u_int32_t
#define RADAR_DETECTION_2__READ                                     0x0fffffffU
#define RADAR_DETECTION_2__WRITE                                    0x0fffffffU

#endif /* __RADAR_DETECTION_2_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_radar_detection_2 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RADAR_DETECTION_2__NUM            1

/* macros for BlueprintGlobalNameSpace::extension_radar */
#ifndef __EXTENSION_RADAR_MACRO__
#define __EXTENSION_RADAR_MACRO__

/* macros for field blocker40_max_radar */
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__SHIFT                           8
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WIDTH                           6
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MASK                  0x00003f00U
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field enable_ext_radar */
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SHIFT                             14
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WIDTH                              1
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MASK                     0x00004000U
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define EXTENSION_RADAR__ENABLE_EXT_RADAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field radar_dc_pwr_thresh */
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__SHIFT                          15
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WIDTH                           8
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MASK                  0x007f8000U
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f8000U) >> 15)
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x007f8000U)
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x007f8000U)
#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x007f8000U)))

/* macros for field radar_lb_dc_cap */
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__SHIFT                              23
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WIDTH                               8
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MASK                      0x7f800000U
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7f800000U) >> 23)
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x7f800000U)
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x7f800000U)
#define EXTENSION_RADAR__RADAR_LB_DC_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x7f800000U)))

/* macros for field disable_adcsat_hold */
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SHIFT                          31
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WIDTH                           1
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MASK                  0x80000000U
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define EXTENSION_RADAR__TYPE                                         u_int32_t
#define EXTENSION_RADAR__READ                                       0xffffff00U
#define EXTENSION_RADAR__WRITE                                      0xffffff00U

#endif /* __EXTENSION_RADAR_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_extension_radar */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXTENSION_RADAR__NUM              1

/* macros for BlueprintGlobalNameSpace::multichain_control */
#ifndef __MULTICHAIN_CONTROL_MACRO__
#define __MULTICHAIN_CONTROL_MACRO__

/* macros for field force_analog_gain_diff */
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SHIFT                     0
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WIDTH                     1
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MASK            0x00000001U
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field forced_gain_diff_01 */
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__SHIFT                        1
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WIDTH                        7
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MASK               0x000000feU
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000feU) >> 1)
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000000feU)
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000feU) | (((u_int32_t)(src) <<\
                    1) & 0x000000feU)
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000000feU)))

/* macros for field sync_synthon */
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SHIFT                               8
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WIDTH                               1
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MASK                      0x00000100U
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MULTICHAIN_CONTROL__SYNC_SYNTHON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field use_posedge_refclk */
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SHIFT                         9
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WIDTH                         1
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MASK                0x00000200U
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field cf_short_sat */
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__SHIFT                              10
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WIDTH                              11
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MASK                      0x001ffc00U
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001ffc00U) >> 10)
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x001ffc00U)
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x001ffc00U)
#define MULTICHAIN_CONTROL__CF_SHORT_SAT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x001ffc00U)))

/* macros for field forced_gain_diff_02 */
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__SHIFT                       22
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WIDTH                        7
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MASK               0x1fc00000U
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1fc00000U) >> 22)
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x1fc00000U)
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x1fc00000U)
#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x1fc00000U)))

/* macros for field force_sigma_zero */
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SHIFT                          29
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WIDTH                           1
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MASK                  0x20000000U
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define MULTICHAIN_CONTROL__TYPE                                      u_int32_t
#define MULTICHAIN_CONTROL__READ                                    0x3fdfffffU
#define MULTICHAIN_CONTROL__WRITE                                   0x3fdfffffU

#endif /* __MULTICHAIN_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_multichain_control */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_MULTICHAIN_CONTROL__NUM           1

/* macros for BlueprintGlobalNameSpace::per_chain_csd */
#ifndef __PER_CHAIN_CSD_MACRO__
#define __PER_CHAIN_CSD_MACRO__

/* macros for field csd_chn1_2chains */
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__SHIFT                                0
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WIDTH                                5
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MASK                       0x0000001fU
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field csd_chn1_3chains */
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__SHIFT                                5
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WIDTH                                5
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MASK                       0x000003e0U
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field csd_chn2_3chains */
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__SHIFT                               10
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WIDTH                                5
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MASK                       0x00007c00U
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))
#define PER_CHAIN_CSD__TYPE                                           u_int32_t
#define PER_CHAIN_CSD__READ                                         0x00007fffU
#define PER_CHAIN_CSD__WRITE                                        0x00007fffU

#endif /* __PER_CHAIN_CSD_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_per_chain_csd */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PER_CHAIN_CSD__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_crc */
#ifndef __TX_CRC_MACRO__
#define __TX_CRC_MACRO__

/* macros for field tx_crc */
#define TX_CRC__TX_CRC__SHIFT                                                 0
#define TX_CRC__TX_CRC__WIDTH                                                16
#define TX_CRC__TX_CRC__MASK                                        0x0000ffffU
#define TX_CRC__TX_CRC__READ(src)                (u_int32_t)(src) & 0x0000ffffU
#define TX_CRC__TYPE                                                  u_int32_t
#define TX_CRC__READ                                                0x0000ffffU

#endif /* __TX_CRC_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_tx_crc */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TX_CRC__NUM                       1

/* macros for BlueprintGlobalNameSpace::tstdac_constant */
#ifndef __TSTDAC_CONSTANT_MACRO__
#define __TSTDAC_CONSTANT_MACRO__

/* macros for field cf_tstdac_constant_i */
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__SHIFT                          0
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WIDTH                         11
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MASK                 0x000007ffU
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000007ffU
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000007ffU)
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((u_int32_t)(src) &\
                    0x000007ffU)
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field cf_tstdac_constant_q */
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__SHIFT                         11
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WIDTH                         11
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MASK                 0x003ff800U
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003ff800U) >> 11)
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x003ff800U)
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003ff800U) | (((u_int32_t)(src) <<\
                    11) & 0x003ff800U)
#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x003ff800U)))
#define TSTDAC_CONSTANT__TYPE                                         u_int32_t
#define TSTDAC_CONSTANT__READ                                       0x003fffffU
#define TSTDAC_CONSTANT__WRITE                                      0x003fffffU

#endif /* __TSTDAC_CONSTANT_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_tstdac_constant */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TSTDAC_CONSTANT__NUM              1

/* macros for BlueprintGlobalNameSpace::spur_report_b0 */
#ifndef __SPUR_REPORT_B0_MACRO__
#define __SPUR_REPORT_B0_MACRO__

/* macros for field spur_est_i_0 */
#define SPUR_REPORT_B0__SPUR_EST_I_0__SHIFT                                   0
#define SPUR_REPORT_B0__SPUR_EST_I_0__WIDTH                                   8
#define SPUR_REPORT_B0__SPUR_EST_I_0__MASK                          0x000000ffU
#define SPUR_REPORT_B0__SPUR_EST_I_0__READ(src)  (u_int32_t)(src) & 0x000000ffU

/* macros for field spur_est_q_0 */
#define SPUR_REPORT_B0__SPUR_EST_Q_0__SHIFT                                   8
#define SPUR_REPORT_B0__SPUR_EST_Q_0__WIDTH                                   8
#define SPUR_REPORT_B0__SPUR_EST_Q_0__MASK                          0x0000ff00U
#define SPUR_REPORT_B0__SPUR_EST_Q_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field power_with_spur_removed_0 */
#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__SHIFT                     16
#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__WIDTH                     16
#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__MASK             0xffff0000U
#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define SPUR_REPORT_B0__TYPE                                          u_int32_t
#define SPUR_REPORT_B0__READ                                        0xffffffffU

#endif /* __SPUR_REPORT_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_spur_report_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SPUR_REPORT_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::txiqcal_control_3 */
#ifndef __TXIQCAL_CONTROL_3_MACRO__
#define __TXIQCAL_CONTROL_3_MACRO__

/* macros for field pwr_high_db */
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__SHIFT                                 0
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WIDTH                                 6
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MASK                        0x0000003fU
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field pwr_low_db */
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__SHIFT                                  6
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WIDTH                                  6
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MASK                         0x00000fc0U
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define TXIQCAL_CONTROL_3__PWR_LOW_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field iqcal_tone_phs_step */
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__SHIFT                        12
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WIDTH                        10
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MASK                0x003ff000U
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003ff000U) >> 12)
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x003ff000U)
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x003ff000U)
#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x003ff000U)))

/* macros for field dc_est_len */
#define TXIQCAL_CONTROL_3__DC_EST_LEN__SHIFT                                 22
#define TXIQCAL_CONTROL_3__DC_EST_LEN__WIDTH                                  2
#define TXIQCAL_CONTROL_3__DC_EST_LEN__MASK                         0x00c00000U
#define TXIQCAL_CONTROL_3__DC_EST_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00c00000U) >> 22)
#define TXIQCAL_CONTROL_3__DC_EST_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00c00000U)
#define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x00c00000U)
#define TXIQCAL_CONTROL_3__DC_EST_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00c00000U)))

/* macros for field adc_sat_len */
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SHIFT                                24
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WIDTH                                 1
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MASK                        0x01000000U
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field adc_sat_sel */
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__SHIFT                                25
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WIDTH                                 2
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MASK                        0x06000000U
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x06000000U) >> 25)
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x06000000U)
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x06000000U) | (((u_int32_t)(src) <<\
                    25) & 0x06000000U)
#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x06000000U)))

/* macros for field iqcal_meas_len */
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__SHIFT                             27
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WIDTH                              2
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MASK                     0x18000000U
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x18000000U) >> 27)
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x18000000U)
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x18000000U) | (((u_int32_t)(src) <<\
                    27) & 0x18000000U)
#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x18000000U)))

/* macros for field desired_size_db */
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__SHIFT                            29
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WIDTH                             2
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MASK                    0x60000000U
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x60000000U) >> 29)
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x60000000U)
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x60000000U) | (((u_int32_t)(src) <<\
                    29) & 0x60000000U)
#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x60000000U)))

/* macros for field tx_iqcorr_en */
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SHIFT                               31
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WIDTH                                1
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MASK                       0x80000000U
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TXIQCAL_CONTROL_3__TYPE                                       u_int32_t
#define TXIQCAL_CONTROL_3__READ                                     0xffffffffU
#define TXIQCAL_CONTROL_3__WRITE                                    0xffffffffU

#endif /* __TXIQCAL_CONTROL_3_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_txiqcal_control_3 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TXIQCAL_CONTROL_3__NUM            1

/* macros for BlueprintGlobalNameSpace::green_tx_control_1 */
#ifndef __GREEN_TX_CONTROL_1_MACRO__
#define __GREEN_TX_CONTROL_1_MACRO__

/* macros for field green_tx_enable */
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SHIFT                            0
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WIDTH                            1
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MASK                   0x00000001U
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field green_cases */
#define GREEN_TX_CONTROL_1__GREEN_CASES__SHIFT                                1
#define GREEN_TX_CONTROL_1__GREEN_CASES__WIDTH                                1
#define GREEN_TX_CONTROL_1__GREEN_CASES__MASK                       0x00000002U
#define GREEN_TX_CONTROL_1__GREEN_CASES__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define GREEN_TX_CONTROL_1__GREEN_CASES__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define GREEN_TX_CONTROL_1__GREEN_CASES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define GREEN_TX_CONTROL_1__GREEN_CASES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define GREEN_TX_CONTROL_1__GREEN_CASES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define GREEN_TX_CONTROL_1__TYPE                                      u_int32_t
#define GREEN_TX_CONTROL_1__READ                                    0x00000003U
#define GREEN_TX_CONTROL_1__WRITE                                   0x00000003U

#endif /* __GREEN_TX_CONTROL_1_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_green_tx_control_1 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_GREEN_TX_CONTROL_1__NUM           1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b0 */
#ifndef __IQ_ADC_MEAS_0_B0_MACRO__
#define __IQ_ADC_MEAS_0_B0_MACRO__

/* macros for field gain_dc_iq_cal_meas_0_0 */
#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__SHIFT                      0
#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__WIDTH                     32
#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__MASK             0xffffffffU
#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_0_B0__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_0_B0__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_0_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_0_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_0_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b0 */
#ifndef __IQ_ADC_MEAS_1_B0_MACRO__
#define __IQ_ADC_MEAS_1_B0_MACRO__

/* macros for field gain_dc_iq_cal_meas_1_0 */
#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__SHIFT                      0
#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__WIDTH                     32
#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__MASK             0xffffffffU
#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_1_B0__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_1_B0__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_1_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_1_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_1_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b0 */
#ifndef __IQ_ADC_MEAS_2_B0_MACRO__
#define __IQ_ADC_MEAS_2_B0_MACRO__

/* macros for field gain_dc_iq_cal_meas_2_0 */
#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__SHIFT                      0
#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__WIDTH                     32
#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__MASK             0xffffffffU
#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_2_B0__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_2_B0__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_2_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_2_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_2_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b0 */
#ifndef __IQ_ADC_MEAS_3_B0_MACRO__
#define __IQ_ADC_MEAS_3_B0_MACRO__

/* macros for field gain_dc_iq_cal_meas_3_0 */
#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__SHIFT                      0
#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__WIDTH                     32
#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__MASK             0xffffffffU
#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_3_B0__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_3_B0__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_3_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_3_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_3_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b0 */
#ifndef __TX_PHASE_RAMP_B0_MACRO__
#define __TX_PHASE_RAMP_B0_MACRO__

/* macros for field cf_phase_ramp_enable_0 */
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SHIFT                       0
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WIDTH                       1
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MASK              0x00000001U
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cf_phase_ramp_bias_0 */
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__SHIFT                         1
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WIDTH                         6
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MASK                0x0000007eU
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000007eU) >> 1)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000007eU)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000007eU)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000007eU)))

/* macros for field cf_phase_ramp_init_0 */
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__SHIFT                         7
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WIDTH                        10
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MASK                0x0001ff80U
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001ff80U) >> 7)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x0001ff80U)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ff80U) | (((u_int32_t)(src) <<\
                    7) & 0x0001ff80U)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x0001ff80U)))

/* macros for field cf_phase_ramp_alpha_0 */
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__SHIFT                       17
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WIDTH                        8
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MASK               0x01fe0000U
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fe0000U) >> 17)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x01fe0000U)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x01fe0000U)
#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x01fe0000U)))
#define TX_PHASE_RAMP_B0__TYPE                                        u_int32_t
#define TX_PHASE_RAMP_B0__READ                                      0x01ffffffU
#define TX_PHASE_RAMP_B0__WRITE                                     0x01ffffffU

#endif /* __TX_PHASE_RAMP_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_tx_phase_ramp_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TX_PHASE_RAMP_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b0 */
#ifndef __ADC_GAIN_DC_CORR_B0_MACRO__
#define __ADC_GAIN_DC_CORR_B0_MACRO__

/* macros for field adc_gain_corr_q_coeff_0 */
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__SHIFT                   0
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WIDTH                   6
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MASK          0x0000003fU
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field adc_gain_corr_i_coeff_0 */
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__SHIFT                   6
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WIDTH                   6
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MASK          0x00000fc0U
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field adc_dc_corr_q_coeff_0 */
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__SHIFT                    12
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WIDTH                     9
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MASK            0x001ff000U
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001ff000U) >> 12)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x001ff000U)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x001ff000U)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x001ff000U)))

/* macros for field adc_dc_corr_i_coeff_0 */
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__SHIFT                    21
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WIDTH                     9
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MASK            0x3fe00000U
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3fe00000U) >> 21)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x3fe00000U)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x3fe00000U)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x3fe00000U)))

/* macros for field adc_gain_corr_enable */
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SHIFT                     30
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WIDTH                      1
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MASK             0x40000000U
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field adc_dc_corr_enable */
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SHIFT                       31
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WIDTH                        1
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MASK               0x80000000U
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define ADC_GAIN_DC_CORR_B0__TYPE                                     u_int32_t
#define ADC_GAIN_DC_CORR_B0__READ                                   0xffffffffU
#define ADC_GAIN_DC_CORR_B0__WRITE                                  0xffffffffU

#endif /* __ADC_GAIN_DC_CORR_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_adc_gain_dc_corr_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_ADC_GAIN_DC_CORR_B0__NUM          1

/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b0 */
#ifndef __RX_IQ_CORR_B0_MACRO__
#define __RX_IQ_CORR_B0_MACRO__

/* macros for field rx_iqcorr_q_q_coff_0 */
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__SHIFT                            0
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WIDTH                            7
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MASK                   0x0000007fU
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field rx_iqcorr_q_i_coff_0 */
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__SHIFT                            7
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WIDTH                            7
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MASK                   0x00003f80U
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f80U) >> 7)
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00003f80U)
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00003f80U)
#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00003f80U)))

/* macros for field rx_iqcorr_enable */
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SHIFT                               14
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WIDTH                                1
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MASK                       0x00004000U
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field loopback_iqcorr_q_q_coff_0 */
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__SHIFT                     15
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WIDTH                      7
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MASK             0x003f8000U
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f8000U) >> 15)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x003f8000U)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x003f8000U)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x003f8000U)))

/* macros for field loopback_iqcorr_q_i_coff_0 */
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__SHIFT                     22
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WIDTH                      7
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MASK             0x1fc00000U
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1fc00000U) >> 22)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x1fc00000U)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x1fc00000U)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x1fc00000U)))

/* macros for field loopback_iqcorr_enable */
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SHIFT                         29
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WIDTH                          1
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MASK                 0x20000000U
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define RX_IQ_CORR_B0__TYPE                                           u_int32_t
#define RX_IQ_CORR_B0__READ                                         0x3fffffffU
#define RX_IQ_CORR_B0__WRITE                                        0x3fffffffU

#endif /* __RX_IQ_CORR_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_rx_iq_corr_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RX_IQ_CORR_B0__NUM                1

/* macros for BlueprintGlobalNameSpace::paprd_am2am_mask */
#ifndef __PAPRD_AM2AM_MASK_MACRO__
#define __PAPRD_AM2AM_MASK_MACRO__

/* macros for field paprd_am2am_mask */
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__SHIFT                             0
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WIDTH                            25
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MASK                    0x01ffffffU
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x01ffffffU
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x01ffffffU)
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01ffffffU) | ((u_int32_t)(src) &\
                    0x01ffffffU)
#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x01ffffffU)))
#define PAPRD_AM2AM_MASK__TYPE                                        u_int32_t
#define PAPRD_AM2AM_MASK__READ                                      0x01ffffffU
#define PAPRD_AM2AM_MASK__WRITE                                     0x01ffffffU

#endif /* __PAPRD_AM2AM_MASK_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_am2am_mask */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_AM2AM_MASK__NUM             1

/* macros for BlueprintGlobalNameSpace::paprd_am2pm_mask */
#ifndef __PAPRD_AM2PM_MASK_MACRO__
#define __PAPRD_AM2PM_MASK_MACRO__

/* macros for field paprd_am2pm_mask */
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__SHIFT                             0
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WIDTH                            25
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MASK                    0x01ffffffU
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x01ffffffU
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x01ffffffU)
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01ffffffU) | ((u_int32_t)(src) &\
                    0x01ffffffU)
#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x01ffffffU)))
#define PAPRD_AM2PM_MASK__TYPE                                        u_int32_t
#define PAPRD_AM2PM_MASK__READ                                      0x01ffffffU
#define PAPRD_AM2PM_MASK__WRITE                                     0x01ffffffU

#endif /* __PAPRD_AM2PM_MASK_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_am2pm_mask */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_AM2PM_MASK__NUM             1

/* macros for BlueprintGlobalNameSpace::paprd_ht40_mask */
#ifndef __PAPRD_HT40_MASK_MACRO__
#define __PAPRD_HT40_MASK_MACRO__

/* macros for field paprd_ht40_mask */
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__SHIFT                               0
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WIDTH                              25
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MASK                      0x01ffffffU
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x01ffffffU
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x01ffffffU)
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01ffffffU) | ((u_int32_t)(src) &\
                    0x01ffffffU)
#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x01ffffffU)))
#define PAPRD_HT40_MASK__TYPE                                         u_int32_t
#define PAPRD_HT40_MASK__READ                                       0x01ffffffU
#define PAPRD_HT40_MASK__WRITE                                      0x01ffffffU

#endif /* __PAPRD_HT40_MASK_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ht40_mask */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_HT40_MASK__NUM              1

/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b0 */
#ifndef __PAPRD_CTRL0_B0_MACRO__
#define __PAPRD_CTRL0_B0_MACRO__

/* macros for field paprd_enable_0 */
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SHIFT                                 0
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WIDTH                                 1
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MASK                        0x00000001U
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_adaptive_use_single_table_0 */
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SHIFT              1
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WIDTH              1
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MASK     0x00000002U
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_valid_gain_0 */
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__SHIFT                             2
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WIDTH                            25
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MASK                    0x07fffffcU
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fffffcU) >> 2)
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x07fffffcU)
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fffffcU) | (((u_int32_t)(src) <<\
                    2) & 0x07fffffcU)
#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x07fffffcU)))

/* macros for field paprd_mag_thrsh_0 */
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__SHIFT                             27
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WIDTH                              5
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MASK                     0xf8000000U
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf8000000U) >> 27)
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0xf8000000U)
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define PAPRD_CTRL0_B0__TYPE                                          u_int32_t
#define PAPRD_CTRL0_B0__READ                                        0xffffffffU
#define PAPRD_CTRL0_B0__WRITE                                       0xffffffffU

#endif /* __PAPRD_CTRL0_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ctrl0_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_CTRL0_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b0 */
#ifndef __PAPRD_CTRL1_B0_MACRO__
#define __PAPRD_CTRL1_B0_MACRO__

/* macros for field paprd_adaptive_scaling_enable_0 */
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SHIFT                0
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WIDTH                1
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MASK       0x00000001U
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_adaptive_am2am_enable_0 */
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SHIFT                  1
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WIDTH                  1
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MASK         0x00000002U
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_adaptive_am2pm_enable_0 */
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SHIFT                  2
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WIDTH                  1
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MASK         0x00000004U
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field paprd_power_at_am2am_cal_0 */
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__SHIFT                     3
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WIDTH                     6
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MASK            0x000001f8U
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001f8U) >> 3)
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000001f8U)
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000001f8U)
#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000001f8U)))

/* macros for field pa_gain_scale_factor_0 */
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__SHIFT                         9
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WIDTH                         8
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MASK                0x0001fe00U
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fe00U) >> 9)
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x0001fe00U)
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001fe00U) | (((u_int32_t)(src) <<\
                    9) & 0x0001fe00U)
#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x0001fe00U)))

/* macros for field paprd_mag_scale_factor_0 */
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__SHIFT                      17
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WIDTH                      10
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MASK              0x07fe0000U
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fe0000U) >> 17)
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x07fe0000U)
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x07fe0000U)
#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x07fe0000U)))

/* macros for field paprd_trainer_iandq_sel_0 */
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SHIFT                     27
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WIDTH                      1
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MASK             0x08000000U
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)
#define PAPRD_CTRL1_B0__TYPE                                          u_int32_t
#define PAPRD_CTRL1_B0__READ                                        0x0fffffffU
#define PAPRD_CTRL1_B0__WRITE                                       0x0fffffffU

#endif /* __PAPRD_CTRL1_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ctrl1_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_CTRL1_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::pa_gain123_b0 */
#ifndef __PA_GAIN123_B0_MACRO__
#define __PA_GAIN123_B0_MACRO__

/* macros for field pa_gain1_0 */
#define PA_GAIN123_B0__PA_GAIN1_0__SHIFT                                      0
#define PA_GAIN123_B0__PA_GAIN1_0__WIDTH                                     10
#define PA_GAIN123_B0__PA_GAIN1_0__MASK                             0x000003ffU
#define PA_GAIN123_B0__PA_GAIN1_0__READ(src)     (u_int32_t)(src) & 0x000003ffU
#define PA_GAIN123_B0__PA_GAIN1_0__WRITE(src)  ((u_int32_t)(src) & 0x000003ffU)
#define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PA_GAIN123_B0__PA_GAIN1_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field pa_gain2_0 */
#define PA_GAIN123_B0__PA_GAIN2_0__SHIFT                                     10
#define PA_GAIN123_B0__PA_GAIN2_0__WIDTH                                     10
#define PA_GAIN123_B0__PA_GAIN2_0__MASK                             0x000ffc00U
#define PA_GAIN123_B0__PA_GAIN2_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define PA_GAIN123_B0__PA_GAIN2_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define PA_GAIN123_B0__PA_GAIN2_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field pa_gain3_0 */
#define PA_GAIN123_B0__PA_GAIN3_0__SHIFT                                     20
#define PA_GAIN123_B0__PA_GAIN3_0__WIDTH                                     10
#define PA_GAIN123_B0__PA_GAIN3_0__MASK                             0x3ff00000U
#define PA_GAIN123_B0__PA_GAIN3_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3ff00000U) >> 20)
#define PA_GAIN123_B0__PA_GAIN3_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x3ff00000U)
#define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
                    20) & 0x3ff00000U)
#define PA_GAIN123_B0__PA_GAIN3_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x3ff00000U)))
#define PA_GAIN123_B0__TYPE                                           u_int32_t
#define PA_GAIN123_B0__READ                                         0x3fffffffU
#define PA_GAIN123_B0__WRITE                                        0x3fffffffU

#endif /* __PA_GAIN123_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_pa_gain123_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PA_GAIN123_B0__NUM                1

/* macros for BlueprintGlobalNameSpace::pa_gain45_b0 */
#ifndef __PA_GAIN45_B0_MACRO__
#define __PA_GAIN45_B0_MACRO__

/* macros for field pa_gain4_0 */
#define PA_GAIN45_B0__PA_GAIN4_0__SHIFT                                       0
#define PA_GAIN45_B0__PA_GAIN4_0__WIDTH                                      10
#define PA_GAIN45_B0__PA_GAIN4_0__MASK                              0x000003ffU
#define PA_GAIN45_B0__PA_GAIN4_0__READ(src)      (u_int32_t)(src) & 0x000003ffU
#define PA_GAIN45_B0__PA_GAIN4_0__WRITE(src)   ((u_int32_t)(src) & 0x000003ffU)
#define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PA_GAIN45_B0__PA_GAIN4_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field pa_gain5_0 */
#define PA_GAIN45_B0__PA_GAIN5_0__SHIFT                                      10
#define PA_GAIN45_B0__PA_GAIN5_0__WIDTH                                      10
#define PA_GAIN45_B0__PA_GAIN5_0__MASK                              0x000ffc00U
#define PA_GAIN45_B0__PA_GAIN5_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define PA_GAIN45_B0__PA_GAIN5_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define PA_GAIN45_B0__PA_GAIN5_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field paprd_adaptive_table_valid_0 */
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__SHIFT                    20
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WIDTH                     5
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MASK            0x01f00000U
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))
#define PA_GAIN45_B0__TYPE                                            u_int32_t
#define PA_GAIN45_B0__READ                                          0x01ffffffU
#define PA_GAIN45_B0__WRITE                                         0x01ffffffU

#endif /* __PA_GAIN45_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_pa_gain45_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PA_GAIN45_B0__NUM                 1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_0_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_0_B0_MACRO__

/* macros for field paprd_pre_post_scaling_0_0 */
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_0_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_0_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_0_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_1_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_1_B0_MACRO__

/* macros for field paprd_pre_post_scaling_1_0 */
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_1_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_1_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_1_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_2_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_2_B0_MACRO__

/* macros for field paprd_pre_post_scaling_2_0 */
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_2_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_2_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_2_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_3_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_3_B0_MACRO__

/* macros for field paprd_pre_post_scaling_3_0 */
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_3_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_3_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_3_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_4_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_4_B0_MACRO__

/* macros for field paprd_pre_post_scaling_4_0 */
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_4_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_4_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_4_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_5_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_5_B0_MACRO__

/* macros for field paprd_pre_post_scaling_5_0 */
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_5_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_5_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_5_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_6_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_6_B0_MACRO__

/* macros for field paprd_pre_post_scaling_6_0 */
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_6_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_6_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_6_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b0 */
#ifndef __PAPRD_PRE_POST_SCALE_7_B0_MACRO__
#define __PAPRD_PRE_POST_SCALE_7_B0_MACRO__

/* macros for field paprd_pre_post_scaling_7_0 */
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__SHIFT          0
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WIDTH         18
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_7_B0__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_7_B0__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B0__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_7_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B0__NUM    1

/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */
#ifndef __PAPRD_MEM_TAB_MACRO__
#define __PAPRD_MEM_TAB_MACRO__

/* macros for field paprd_mem */
#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT                                       0
#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH                                      22
#define PAPRD_MEM_TAB__PAPRD_MEM__MASK                              0x003fffffU
#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src)      (u_int32_t)(src) & 0x003fffffU
#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src)   ((u_int32_t)(src) & 0x003fffffU)
#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003fffffU) | ((u_int32_t)(src) &\
                    0x003fffffU)
#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x003fffffU)))
#define PAPRD_MEM_TAB__TYPE                                           u_int32_t
#define PAPRD_MEM_TAB__READ                                         0x003fffffU
#define PAPRD_MEM_TAB__WRITE                                        0x003fffffU

#endif /* __PAPRD_MEM_TAB_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_mem_tab_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_MEM_TAB_B0__NUM           120

/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */
#ifndef __CHAN_INFO_CHAN_TAB_MACRO__
#define __CHAN_INFO_CHAN_TAB_MACRO__

/* macros for field chaninfo_word */
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT                              0
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH                             32
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK                     0xffffffffU
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CHAN_INFO_CHAN_TAB__TYPE                                      u_int32_t
#define CHAN_INFO_CHAN_TAB__READ                                    0xffffffffU

#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_chan_info_chan_tab_b0 */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B0__NUM       60

/* macros for BlueprintGlobalNameSpace::chn_tables_intf_addr */
#ifndef __CHN_TABLES_INTF_ADDR_MACRO__
#define __CHN_TABLES_INTF_ADDR_MACRO__

/* macros for field chn_tables_addr */
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__SHIFT                          2
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WIDTH                         16
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MASK                 0x0003fffcU
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field chn_addr_auto_incr */
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SHIFT                      31
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WIDTH                       1
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MASK              0x80000000U
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define CHN_TABLES_INTF_ADDR__TYPE                                    u_int32_t
#define CHN_TABLES_INTF_ADDR__READ                                  0x8003fffcU
#define CHN_TABLES_INTF_ADDR__WRITE                                 0x8003fffcU

#endif /* __CHN_TABLES_INTF_ADDR_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_chn_tables_intf_addr */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHN_TABLES_INTF_ADDR__NUM         1

/* macros for BlueprintGlobalNameSpace::chn_tables_intf_data */
#ifndef __CHN_TABLES_INTF_DATA_MACRO__
#define __CHN_TABLES_INTF_DATA_MACRO__

/* macros for field chn_tables_data */
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__SHIFT                          0
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WIDTH                         32
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MASK                 0xffffffffU
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CHN_TABLES_INTF_DATA__TYPE                                    u_int32_t
#define CHN_TABLES_INTF_DATA__READ                                  0xffffffffU
#define CHN_TABLES_INTF_DATA__WRITE                                 0xffffffffU

#endif /* __CHN_TABLES_INTF_DATA_MACRO__ */


/* macros for bb_reg_map.bb_chn_reg_map.BB_chn_tables_intf_data */
#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHN_TABLES_INTF_DATA__NUM         1

/* macros for BlueprintGlobalNameSpace::timing_control_3a */
#ifndef __TIMING_CONTROL_3A_MACRO__
#define __TIMING_CONTROL_3A_MACRO__

/* macros for field ste_thr_hi_rssi */
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__SHIFT                             0
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WIDTH                             7
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MASK                    0x0000007fU
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field use_htsig1_20_40_bw_value */
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SHIFT                   7
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WIDTH                   1
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MASK          0x00000080U
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)
#define TIMING_CONTROL_3A__TYPE                                       u_int32_t
#define TIMING_CONTROL_3A__READ                                     0x000000ffU
#define TIMING_CONTROL_3A__WRITE                                    0x000000ffU

#endif /* __TIMING_CONTROL_3A_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_timing_control_3a */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_TIMING_CONTROL_3A__NUM            1

/* macros for BlueprintGlobalNameSpace::ldpc_cntl1 */
#ifndef __LDPC_CNTL1_MACRO__
#define __LDPC_CNTL1_MACRO__

/* macros for field ldpc_llr_scaling0 */
#define LDPC_CNTL1__LDPC_LLR_SCALING0__SHIFT                                  0
#define LDPC_CNTL1__LDPC_LLR_SCALING0__WIDTH                                 32
#define LDPC_CNTL1__LDPC_LLR_SCALING0__MASK                         0xffffffffU
#define LDPC_CNTL1__LDPC_LLR_SCALING0__READ(src) (u_int32_t)(src) & 0xffffffffU
#define LDPC_CNTL1__LDPC_LLR_SCALING0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define LDPC_CNTL1__LDPC_LLR_SCALING0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define LDPC_CNTL1__TYPE                                              u_int32_t
#define LDPC_CNTL1__READ                                            0xffffffffU
#define LDPC_CNTL1__WRITE                                           0xffffffffU

#endif /* __LDPC_CNTL1_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_ldpc_cntl1 */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_LDPC_CNTL1__NUM                   1

/* macros for BlueprintGlobalNameSpace::ldpc_cntl2 */
#ifndef __LDPC_CNTL2_MACRO__
#define __LDPC_CNTL2_MACRO__

/* macros for field ldpc_llr_scaling1 */
#define LDPC_CNTL2__LDPC_LLR_SCALING1__SHIFT                                  0
#define LDPC_CNTL2__LDPC_LLR_SCALING1__WIDTH                                 16
#define LDPC_CNTL2__LDPC_LLR_SCALING1__MASK                         0x0000ffffU
#define LDPC_CNTL2__LDPC_LLR_SCALING1__READ(src) (u_int32_t)(src) & 0x0000ffffU
#define LDPC_CNTL2__LDPC_LLR_SCALING1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000ffffU)
#define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define LDPC_CNTL2__LDPC_LLR_SCALING1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field ldpc_latency */
#define LDPC_CNTL2__LDPC_LATENCY__SHIFT                                      16
#define LDPC_CNTL2__LDPC_LATENCY__WIDTH                                      11
#define LDPC_CNTL2__LDPC_LATENCY__MASK                              0x07ff0000U
#define LDPC_CNTL2__LDPC_LATENCY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define LDPC_CNTL2__LDPC_LATENCY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x07ff0000U)
#define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x07ff0000U)
#define LDPC_CNTL2__LDPC_LATENCY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x07ff0000U)))
#define LDPC_CNTL2__TYPE                                              u_int32_t
#define LDPC_CNTL2__READ                                            0x07ffffffU
#define LDPC_CNTL2__WRITE                                           0x07ffffffU

#endif /* __LDPC_CNTL2_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_ldpc_cntl2 */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_LDPC_CNTL2__NUM                   1

/* macros for BlueprintGlobalNameSpace::pilot_spur_mask */
#ifndef __PILOT_SPUR_MASK_MACRO__
#define __PILOT_SPUR_MASK_MACRO__

/* macros for field cf_pilot_mask_A */
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__SHIFT                               0
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WIDTH                               5
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MASK                      0x0000001fU
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field cf_pilot_mask_idx_A */
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__SHIFT                           5
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WIDTH                           7
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MASK                  0x00000fe0U
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fe0U) >> 5)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000fe0U)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fe0U) | (((u_int32_t)(src) <<\
                    5) & 0x00000fe0U)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000fe0U)))

/* macros for field cf_pilot_mask_B */
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__SHIFT                              12
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WIDTH                               5
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MASK                      0x0001f000U
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field cf_pilot_mask_idx_B */
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__SHIFT                          17
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WIDTH                           7
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MASK                  0x00fe0000U
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fe0000U) >> 17)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00fe0000U)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x00fe0000U)
#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00fe0000U)))
#define PILOT_SPUR_MASK__TYPE                                         u_int32_t
#define PILOT_SPUR_MASK__READ                                       0x00ffffffU
#define PILOT_SPUR_MASK__WRITE                                      0x00ffffffU

#endif /* __PILOT_SPUR_MASK_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_pilot_spur_mask */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_PILOT_SPUR_MASK__NUM              1

/* macros for BlueprintGlobalNameSpace::chan_spur_mask */
#ifndef __CHAN_SPUR_MASK_MACRO__
#define __CHAN_SPUR_MASK_MACRO__

/* macros for field cf_chan_mask_A */
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__SHIFT                                 0
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WIDTH                                 5
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MASK                        0x0000001fU
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field cf_chan_mask_idx_A */
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__SHIFT                             5
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WIDTH                             7
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MASK                    0x00000fe0U
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fe0U) >> 5)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000fe0U)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fe0U) | (((u_int32_t)(src) <<\
                    5) & 0x00000fe0U)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000fe0U)))

/* macros for field cf_chan_mask_B */
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__SHIFT                                12
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WIDTH                                 5
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MASK                        0x0001f000U
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field cf_chan_mask_idx_B */
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__SHIFT                            17
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WIDTH                             7
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MASK                    0x00fe0000U
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fe0000U) >> 17)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00fe0000U)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x00fe0000U)
#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00fe0000U)))
#define CHAN_SPUR_MASK__TYPE                                          u_int32_t
#define CHAN_SPUR_MASK__READ                                        0x00ffffffU
#define CHAN_SPUR_MASK__WRITE                                       0x00ffffffU

#endif /* __CHAN_SPUR_MASK_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_chan_spur_mask */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_CHAN_SPUR_MASK__NUM               1

/* macros for BlueprintGlobalNameSpace::short_gi_delta_slope */
#ifndef __SHORT_GI_DELTA_SLOPE_MACRO__
#define __SHORT_GI_DELTA_SLOPE_MACRO__

/* macros for field delta_slope_coef_exp_short_gi */
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__SHIFT            0
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WIDTH            4
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MASK   0x0000000fU
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field delta_slope_coef_man_short_gi */
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__SHIFT            4
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WIDTH           15
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MASK   0x0007fff0U
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0007fff0U) >> 4)
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x0007fff0U)
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0007fff0U) | (((u_int32_t)(src) <<\
                    4) & 0x0007fff0U)
#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x0007fff0U)))
#define SHORT_GI_DELTA_SLOPE__TYPE                                    u_int32_t
#define SHORT_GI_DELTA_SLOPE__READ                                  0x0007ffffU
#define SHORT_GI_DELTA_SLOPE__WRITE                                 0x0007ffffU

#endif /* __SHORT_GI_DELTA_SLOPE_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_short_gi_delta_slope */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_SHORT_GI_DELTA_SLOPE__NUM         1

/* macros for BlueprintGlobalNameSpace::ml_cntl1 */
#ifndef __ML_CNTL1_MACRO__
#define __ML_CNTL1_MACRO__

/* macros for field cf_ml_2s_weight_table */
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__SHIFT                                0
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WIDTH                               24
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MASK                       0x00ffffffU
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00ffffffU
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))

/* macros for field cf_is_flat_ch_thr_ml */
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__SHIFT                                24
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WIDTH                                 2
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MASK                        0x03000000U
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03000000U) >> 24)
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x03000000U)
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field cf_is_flat_ch_thr_zf */
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__SHIFT                                26
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WIDTH                                 2
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MASK                        0x0c000000U
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0c000000U) >> 26)
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x0c000000U)
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x0c000000U)
#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x0c000000U)))
#define ML_CNTL1__TYPE                                                u_int32_t
#define ML_CNTL1__READ                                              0x0fffffffU
#define ML_CNTL1__WRITE                                             0x0fffffffU

#endif /* __ML_CNTL1_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_ml_cntl1 */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_ML_CNTL1__NUM                     1

/* macros for BlueprintGlobalNameSpace::ml_cntl2 */
#ifndef __ML_CNTL2_MACRO__
#define __ML_CNTL2_MACRO__

/* macros for field cf_ml_3s_weight_table */
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__SHIFT                                0
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WIDTH                               24
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MASK                       0x00ffffffU
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00ffffffU
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00ffffffU)
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ffffffU) | ((u_int32_t)(src) &\
                    0x00ffffffU)
#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00ffffffU)))
#define ML_CNTL2__TYPE                                                u_int32_t
#define ML_CNTL2__READ                                              0x00ffffffU
#define ML_CNTL2__WRITE                                             0x00ffffffU

#endif /* __ML_CNTL2_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_ml_cntl2 */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_ML_CNTL2__NUM                     1

/* macros for BlueprintGlobalNameSpace::tstadc */
#ifndef __TSTADC_MACRO__
#define __TSTADC_MACRO__

/* macros for field tstadc_out_q */
#define TSTADC__TSTADC_OUT_Q__SHIFT                                           0
#define TSTADC__TSTADC_OUT_Q__WIDTH                                          10
#define TSTADC__TSTADC_OUT_Q__MASK                                  0x000003ffU
#define TSTADC__TSTADC_OUT_Q__READ(src)          (u_int32_t)(src) & 0x000003ffU

/* macros for field tstadc_out_i */
#define TSTADC__TSTADC_OUT_I__SHIFT                                          10
#define TSTADC__TSTADC_OUT_I__WIDTH                                          10
#define TSTADC__TSTADC_OUT_I__MASK                                  0x000ffc00U
#define TSTADC__TSTADC_OUT_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define TSTADC__TYPE                                                  u_int32_t
#define TSTADC__READ                                                0x000fffffU

#endif /* __TSTADC_MACRO__ */


/* macros for bb_reg_map.bb_mrc_reg_map.BB_tstadc */
#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_TSTADC__NUM                       1

/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_1 */
#ifndef __BBB_RX_CTRL_1_MACRO__
#define __BBB_RX_CTRL_1_MACRO__

/* macros for field coarse_tim_threshold_2 */
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__SHIFT                          0
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WIDTH                          3
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MASK                 0x00000007U
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field coarse_tim_threshold */
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__SHIFT                            3
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WIDTH                            5
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MASK                   0x000000f8U
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f8U) >> 3)
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000000f8U)
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000000f8U)
#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000000f8U)))

/* macros for field coarse_tim_n_sync */
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__SHIFT                               8
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WIDTH                               3
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MASK                      0x00000700U
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000700U)
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field max_bal_long */
#define BBB_RX_CTRL_1__MAX_BAL_LONG__SHIFT                                   11
#define BBB_RX_CTRL_1__MAX_BAL_LONG__WIDTH                                    5
#define BBB_RX_CTRL_1__MAX_BAL_LONG__MASK                           0x0000f800U
#define BBB_RX_CTRL_1__MAX_BAL_LONG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f800U) >> 11)
#define BBB_RX_CTRL_1__MAX_BAL_LONG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x0000f800U)
#define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f800U) | (((u_int32_t)(src) <<\
                    11) & 0x0000f800U)
#define BBB_RX_CTRL_1__MAX_BAL_LONG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x0000f800U)))

/* macros for field max_bal_short */
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__SHIFT                                  16
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WIDTH                                   5
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MASK                          0x001f0000U
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x001f0000U)
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x001f0000U)
#define BBB_RX_CTRL_1__MAX_BAL_SHORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x001f0000U)))

/* macros for field recon_lms_step */
#define BBB_RX_CTRL_1__RECON_LMS_STEP__SHIFT                                 21
#define BBB_RX_CTRL_1__RECON_LMS_STEP__WIDTH                                  3
#define BBB_RX_CTRL_1__RECON_LMS_STEP__MASK                         0x00e00000U
#define BBB_RX_CTRL_1__RECON_LMS_STEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00e00000U) >> 21)
#define BBB_RX_CTRL_1__RECON_LMS_STEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00e00000U)
#define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x00e00000U)
#define BBB_RX_CTRL_1__RECON_LMS_STEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00e00000U)))

/* macros for field sb_check_win */
#define BBB_RX_CTRL_1__SB_CHECK_WIN__SHIFT                                   24
#define BBB_RX_CTRL_1__SB_CHECK_WIN__WIDTH                                    7
#define BBB_RX_CTRL_1__SB_CHECK_WIN__MASK                           0x7f000000U
#define BBB_RX_CTRL_1__SB_CHECK_WIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7f000000U) >> 24)
#define BBB_RX_CTRL_1__SB_CHECK_WIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x7f000000U)
#define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define BBB_RX_CTRL_1__SB_CHECK_WIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))

/* macros for field en_rx_abort_cck */
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SHIFT                                31
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WIDTH                                 1
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MASK                        0x80000000U
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define BBB_RX_CTRL_1__TYPE                                           u_int32_t
#define BBB_RX_CTRL_1__READ                                         0xffffffffU
#define BBB_RX_CTRL_1__WRITE                                        0xffffffffU

#endif /* __BBB_RX_CTRL_1_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_1 */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_1__NUM                1

/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_2 */
#ifndef __BBB_RX_CTRL_2_MACRO__
#define __BBB_RX_CTRL_2_MACRO__

/* macros for field freq_est_n_avg_long */
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__SHIFT                             0
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WIDTH                             6
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MASK                    0x0000003fU
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field chan_avg_long */
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__SHIFT                                   6
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WIDTH                                   6
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MASK                          0x00000fc0U
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define BBB_RX_CTRL_2__CHAN_AVG_LONG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field coarse_tim_threshold_3 */
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__SHIFT                         12
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WIDTH                          5
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MASK                 0x0001f000U
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field freq_track_update_period */
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__SHIFT                       17
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WIDTH                        5
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MASK               0x003e0000U
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003e0000U) >> 17)
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x003e0000U)
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field freq_est_scaling_period */
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__SHIFT                        22
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WIDTH                         4
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MASK                0x03c00000U
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03c00000U) >> 22)
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x03c00000U)
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x03c00000U)
#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x03c00000U)))

/* macros for field loop_coef_dpsk_c2_data */
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__SHIFT                         26
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WIDTH                          6
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MASK                 0xfc000000U
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfc000000U) >> 26)
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0xfc000000U)
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfc000000U) | (((u_int32_t)(src) <<\
                    26) & 0xfc000000U)
#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0xfc000000U)))
#define BBB_RX_CTRL_2__TYPE                                           u_int32_t
#define BBB_RX_CTRL_2__READ                                         0xffffffffU
#define BBB_RX_CTRL_2__WRITE                                        0xffffffffU

#endif /* __BBB_RX_CTRL_2_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_2 */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_2__NUM                1

/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_3 */
#ifndef __BBB_RX_CTRL_3_MACRO__
#define __BBB_RX_CTRL_3_MACRO__

/* macros for field tim_adjust_freq_dpsk */
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__SHIFT                            0
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WIDTH                            8
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MASK                   0x000000ffU
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tim_adjust_freq_cck */
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__SHIFT                             8
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WIDTH                             8
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MASK                    0x0000ff00U
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field timer_n_sfd */
#define BBB_RX_CTRL_3__TIMER_N_SFD__SHIFT                                    16
#define BBB_RX_CTRL_3__TIMER_N_SFD__WIDTH                                     8
#define BBB_RX_CTRL_3__TIMER_N_SFD__MASK                            0x00ff0000U
#define BBB_RX_CTRL_3__TIMER_N_SFD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define BBB_RX_CTRL_3__TIMER_N_SFD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define BBB_RX_CTRL_3__TIMER_N_SFD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))
#define BBB_RX_CTRL_3__TYPE                                           u_int32_t
#define BBB_RX_CTRL_3__READ                                         0x00ffffffU
#define BBB_RX_CTRL_3__WRITE                                        0x00ffffffU

#endif /* __BBB_RX_CTRL_3_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_3 */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_3__NUM                1

/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_4 */
#ifndef __BBB_RX_CTRL_4_MACRO__
#define __BBB_RX_CTRL_4_MACRO__

/* macros for field timer_n_sync */
#define BBB_RX_CTRL_4__TIMER_N_SYNC__SHIFT                                    0
#define BBB_RX_CTRL_4__TIMER_N_SYNC__WIDTH                                    4
#define BBB_RX_CTRL_4__TIMER_N_SYNC__MASK                           0x0000000fU
#define BBB_RX_CTRL_4__TIMER_N_SYNC__READ(src)   (u_int32_t)(src) & 0x0000000fU
#define BBB_RX_CTRL_4__TIMER_N_SYNC__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define BBB_RX_CTRL_4__TIMER_N_SYNC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field tim_adjust_timer_exp */
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__SHIFT                            4
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WIDTH                           12
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MASK                   0x0000fff0U
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fff0U) >> 4)
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x0000fff0U)
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fff0U) | (((u_int32_t)(src) <<\
                    4) & 0x0000fff0U)
#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x0000fff0U)))

/* macros for field force_unlocked_clocks */
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SHIFT                          16
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WIDTH                           1
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MASK                  0x00010000U
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field dynamic_pream_sel */
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SHIFT                              17
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WIDTH                               1
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MASK                      0x00020000U
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field short_preamble */
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SHIFT                                 18
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WIDTH                                  1
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MASK                         0x00040000U
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define BBB_RX_CTRL_4__SHORT_PREAMBLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field freq_est_n_avg_short */
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__SHIFT                           19
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WIDTH                            6
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MASK                   0x01f80000U
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f80000U) >> 19)
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x01f80000U)
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f80000U) | (((u_int32_t)(src) <<\
                    19) & 0x01f80000U)
#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x01f80000U)))

/* macros for field chan_avg_short */
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__SHIFT                                 25
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WIDTH                                  6
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MASK                         0x7e000000U
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7e000000U) >> 25)
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x7e000000U)
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x7e000000U)
#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x7e000000U)))

/* macros for field use_mrc_weight */
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SHIFT                                 31
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WIDTH                                  1
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MASK                         0x80000000U
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define BBB_RX_CTRL_4__TYPE                                           u_int32_t
#define BBB_RX_CTRL_4__READ                                         0xffffffffU
#define BBB_RX_CTRL_4__WRITE                                        0xffffffffU

#endif /* __BBB_RX_CTRL_4_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_4 */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_4__NUM                1

/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_5 */
#ifndef __BBB_RX_CTRL_5_MACRO__
#define __BBB_RX_CTRL_5_MACRO__

/* macros for field loop_coef_dpsk_c1_data */
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__SHIFT                          0
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WIDTH                          5
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MASK                 0x0000001fU
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field loop_coef_dpsk_c1_head */
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__SHIFT                          5
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WIDTH                          5
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MASK                 0x000003e0U
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field loop_coef_dpsk_c2_head */
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__SHIFT                         10
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WIDTH                          6
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MASK                 0x0000fc00U
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fc00U) >> 10)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0000fc00U)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0000fc00U)
#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0000fc00U)))

/* macros for field loop_coef_cck_c1 */
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__SHIFT                               16
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WIDTH                                5
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MASK                       0x001f0000U
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x001f0000U)
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x001f0000U)
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x001f0000U)))

/* macros for field loop_coef_cck_c2 */
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__SHIFT                               21
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WIDTH                                6
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MASK                       0x07e00000U
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07e00000U) >> 21)
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x07e00000U)
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x07e00000U)
#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x07e00000U)))
#define BBB_RX_CTRL_5__TYPE                                           u_int32_t
#define BBB_RX_CTRL_5__READ                                         0x07ffffffU
#define BBB_RX_CTRL_5__WRITE                                        0x07ffffffU

#endif /* __BBB_RX_CTRL_5_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_5 */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_5__NUM                1

/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_6 */
#ifndef __BBB_RX_CTRL_6_MACRO__
#define __BBB_RX_CTRL_6_MACRO__

/* macros for field sync_start_delay */
#define BBB_RX_CTRL_6__SYNC_START_DELAY__SHIFT                                0
#define BBB_RX_CTRL_6__SYNC_START_DELAY__WIDTH                               10
#define BBB_RX_CTRL_6__SYNC_START_DELAY__MASK                       0x000003ffU
#define BBB_RX_CTRL_6__SYNC_START_DELAY__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define BBB_RX_CTRL_6__SYNC_START_DELAY__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define BBB_RX_CTRL_6__SYNC_START_DELAY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field map_1s_to_2s */
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SHIFT                                   10
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WIDTH                                    1
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MASK                           0x00000400U
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define BBB_RX_CTRL_6__MAP_1S_TO_2S__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field start_iir_delay */
#define BBB_RX_CTRL_6__START_IIR_DELAY__SHIFT                                11
#define BBB_RX_CTRL_6__START_IIR_DELAY__WIDTH                                10
#define BBB_RX_CTRL_6__START_IIR_DELAY__MASK                        0x001ff800U
#define BBB_RX_CTRL_6__START_IIR_DELAY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001ff800U) >> 11)
#define BBB_RX_CTRL_6__START_IIR_DELAY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x001ff800U)
#define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001ff800U) | (((u_int32_t)(src) <<\
                    11) & 0x001ff800U)
#define BBB_RX_CTRL_6__START_IIR_DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x001ff800U)))

/* macros for field use_mcorr_weight */
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SHIFT                               21
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WIDTH                                1
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MASK                       0x00200000U
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field use_bkpwr_for_center_index */
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SHIFT                     22
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WIDTH                      1
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MASK             0x00400000U
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field cck_sel_chain_by_eo */
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SHIFT                            23
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WIDTH                             1
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MASK                    0x00800000U
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field force_cck_sel_chain */
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SHIFT                            24
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WIDTH                             1
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MASK                    0x01000000U
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field force_center_index */
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SHIFT                             25
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WIDTH                              1
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MASK                     0x02000000U
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)
#define BBB_RX_CTRL_6__TYPE                                           u_int32_t
#define BBB_RX_CTRL_6__READ                                         0x03ffffffU
#define BBB_RX_CTRL_6__WRITE                                        0x03ffffffU

#endif /* __BBB_RX_CTRL_6_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_6 */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_6__NUM                1

/* macros for BlueprintGlobalNameSpace::force_clken_cck */
#ifndef __FORCE_CLKEN_CCK_MACRO__
#define __FORCE_CLKEN_CCK_MACRO__

/* macros for field force_rx_enable0 */
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SHIFT                              0
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WIDTH                              1
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MASK                     0x00000001U
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field force_rx_enable1 */
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SHIFT                              1
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WIDTH                              1
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MASK                     0x00000002U
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field force_rx_enable2 */
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SHIFT                              2
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WIDTH                              1
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MASK                     0x00000004U
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field force_rx_enable3 */
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SHIFT                              3
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WIDTH                              1
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MASK                     0x00000008U
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field force_rx_always */
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SHIFT                               4
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WIDTH                               1
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MASK                      0x00000010U
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field force_txsm_clken */
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SHIFT                              5
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WIDTH                              1
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MASK                     0x00000020U
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)
#define FORCE_CLKEN_CCK__TYPE                                         u_int32_t
#define FORCE_CLKEN_CCK__READ                                       0x0000003fU
#define FORCE_CLKEN_CCK__WRITE                                      0x0000003fU

#endif /* __FORCE_CLKEN_CCK_MACRO__ */


/* macros for bb_reg_map.bb_bbb_reg_map.BB_force_clken_cck */
#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_FORCE_CLKEN_CCK__NUM              1

/* macros for BlueprintGlobalNameSpace::settling_time */
#ifndef __SETTLING_TIME_MACRO__
#define __SETTLING_TIME_MACRO__

/* macros for field agc_settling */
#define SETTLING_TIME__AGC_SETTLING__SHIFT                                    0
#define SETTLING_TIME__AGC_SETTLING__WIDTH                                    7
#define SETTLING_TIME__AGC_SETTLING__MASK                           0x0000007fU
#define SETTLING_TIME__AGC_SETTLING__READ(src)   (u_int32_t)(src) & 0x0000007fU
#define SETTLING_TIME__AGC_SETTLING__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define SETTLING_TIME__AGC_SETTLING__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field switch_settling */
#define SETTLING_TIME__SWITCH_SETTLING__SHIFT                                 7
#define SETTLING_TIME__SWITCH_SETTLING__WIDTH                                 7
#define SETTLING_TIME__SWITCH_SETTLING__MASK                        0x00003f80U
#define SETTLING_TIME__SWITCH_SETTLING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f80U) >> 7)
#define SETTLING_TIME__SWITCH_SETTLING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00003f80U)
#define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00003f80U)
#define SETTLING_TIME__SWITCH_SETTLING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00003f80U)))

/* macros for field adcsat_thrl */
#define SETTLING_TIME__ADCSAT_THRL__SHIFT                                    14
#define SETTLING_TIME__ADCSAT_THRL__WIDTH                                     6
#define SETTLING_TIME__ADCSAT_THRL__MASK                            0x000fc000U
#define SETTLING_TIME__ADCSAT_THRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fc000U) >> 14)
#define SETTLING_TIME__ADCSAT_THRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x000fc000U)
#define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x000fc000U)
#define SETTLING_TIME__ADCSAT_THRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x000fc000U)))

/* macros for field adcsat_thrh */
#define SETTLING_TIME__ADCSAT_THRH__SHIFT                                    20
#define SETTLING_TIME__ADCSAT_THRH__WIDTH                                     6
#define SETTLING_TIME__ADCSAT_THRH__MASK                            0x03f00000U
#define SETTLING_TIME__ADCSAT_THRH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03f00000U) >> 20)
#define SETTLING_TIME__ADCSAT_THRH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x03f00000U)
#define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x03f00000U)
#define SETTLING_TIME__ADCSAT_THRH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x03f00000U)))

/* macros for field lbreset_advance */
#define SETTLING_TIME__LBRESET_ADVANCE__SHIFT                                26
#define SETTLING_TIME__LBRESET_ADVANCE__WIDTH                                 4
#define SETTLING_TIME__LBRESET_ADVANCE__MASK                        0x3c000000U
#define SETTLING_TIME__LBRESET_ADVANCE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3c000000U) >> 26)
#define SETTLING_TIME__LBRESET_ADVANCE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x3c000000U)
#define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x3c000000U)
#define SETTLING_TIME__LBRESET_ADVANCE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x3c000000U)))
#define SETTLING_TIME__TYPE                                           u_int32_t
#define SETTLING_TIME__READ                                         0x3fffffffU
#define SETTLING_TIME__WRITE                                        0x3fffffffU

#endif /* __SETTLING_TIME_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_settling_time */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_SETTLING_TIME__NUM                1

/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b0 */
#ifndef __GAIN_FORCE_MAX_GAINS_B0_MACRO__
#define __GAIN_FORCE_MAX_GAINS_B0_MACRO__

/* macros for field rf_gain_f_0 */
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__SHIFT                           0
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WIDTH                           8
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MASK                  0x000000ffU
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field mb_gain_f_0 */
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__SHIFT                           8
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WIDTH                           8
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MASK                  0x0000ff00U
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field xatten1_sw_f_0 */
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SHIFT                       16
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WIDTH                        1
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MASK               0x00010000U
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field xatten2_sw_f_0 */
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SHIFT                       17
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WIDTH                        1
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MASK               0x00020000U
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field xatten1_hyst_margin_0 */
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__SHIFT                18
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WIDTH                 7
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MASK        0x01fc0000U
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fc0000U) >> 18)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x01fc0000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x01fc0000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x01fc0000U)))

/* macros for field xatten2_hyst_margin_0 */
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__SHIFT                25
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WIDTH                 7
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MASK        0xfe000000U
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfe000000U) >> 25)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0xfe000000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfe000000U) | (((u_int32_t)(src) <<\
                    25) & 0xfe000000U)
#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0xfe000000U)))
#define GAIN_FORCE_MAX_GAINS_B0__TYPE                                 u_int32_t
#define GAIN_FORCE_MAX_GAINS_B0__READ                               0xffffffffU
#define GAIN_FORCE_MAX_GAINS_B0__WRITE                              0xffffffffU

#endif /* __GAIN_FORCE_MAX_GAINS_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_gain_force_max_gains_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B0__NUM      1

/* macros for BlueprintGlobalNameSpace::gains_min_offsets */
#ifndef __GAINS_MIN_OFFSETS_MACRO__
#define __GAINS_MIN_OFFSETS_MACRO__

/* macros for field offsetC1 */
#define GAINS_MIN_OFFSETS__OFFSETC1__SHIFT                                    0
#define GAINS_MIN_OFFSETS__OFFSETC1__WIDTH                                    7
#define GAINS_MIN_OFFSETS__OFFSETC1__MASK                           0x0000007fU
#define GAINS_MIN_OFFSETS__OFFSETC1__READ(src)   (u_int32_t)(src) & 0x0000007fU
#define GAINS_MIN_OFFSETS__OFFSETC1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define GAINS_MIN_OFFSETS__OFFSETC1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field offsetC2 */
#define GAINS_MIN_OFFSETS__OFFSETC2__SHIFT                                    7
#define GAINS_MIN_OFFSETS__OFFSETC2__WIDTH                                    5
#define GAINS_MIN_OFFSETS__OFFSETC2__MASK                           0x00000f80U
#define GAINS_MIN_OFFSETS__OFFSETC2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f80U) >> 7)
#define GAINS_MIN_OFFSETS__OFFSETC2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000f80U)
#define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00000f80U)
#define GAINS_MIN_OFFSETS__OFFSETC2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000f80U)))

/* macros for field offsetC3 */
#define GAINS_MIN_OFFSETS__OFFSETC3__SHIFT                                   12
#define GAINS_MIN_OFFSETS__OFFSETC3__WIDTH                                    5
#define GAINS_MIN_OFFSETS__OFFSETC3__MASK                           0x0001f000U
#define GAINS_MIN_OFFSETS__OFFSETC3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define GAINS_MIN_OFFSETS__OFFSETC3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define GAINS_MIN_OFFSETS__OFFSETC3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field gain_force */
#define GAINS_MIN_OFFSETS__GAIN_FORCE__SHIFT                                 17
#define GAINS_MIN_OFFSETS__GAIN_FORCE__WIDTH                                  1
#define GAINS_MIN_OFFSETS__GAIN_FORCE__MASK                         0x00020000U
#define GAINS_MIN_OFFSETS__GAIN_FORCE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define GAINS_MIN_OFFSETS__GAIN_FORCE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define GAINS_MIN_OFFSETS__GAIN_FORCE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define GAINS_MIN_OFFSETS__GAIN_FORCE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define GAINS_MIN_OFFSETS__GAIN_FORCE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field cf_agc_hist_enable */
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SHIFT                         18
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WIDTH                          1
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MASK                 0x00040000U
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field cf_agc_hist_gc */
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SHIFT                             19
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WIDTH                              1
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MASK                     0x00080000U
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field cf_agc_hist_voting */
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SHIFT                         20
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WIDTH                          1
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MASK                 0x00100000U
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field cf_agc_hist_phy_err */
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SHIFT                        21
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WIDTH                         1
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MASK                0x00200000U
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)
#define GAINS_MIN_OFFSETS__TYPE                                       u_int32_t
#define GAINS_MIN_OFFSETS__READ                                     0x003fffffU
#define GAINS_MIN_OFFSETS__WRITE                                    0x003fffffU

#endif /* __GAINS_MIN_OFFSETS_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_gains_min_offsets */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_GAINS_MIN_OFFSETS__NUM            1

/* macros for BlueprintGlobalNameSpace::desired_sigsize */
#ifndef __DESIRED_SIGSIZE_MACRO__
#define __DESIRED_SIGSIZE_MACRO__

/* macros for field adc_desired_size */
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__SHIFT                              0
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WIDTH                              8
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MASK                     0x000000ffU
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field total_desired */
#define DESIRED_SIGSIZE__TOTAL_DESIRED__SHIFT                                20
#define DESIRED_SIGSIZE__TOTAL_DESIRED__WIDTH                                 8
#define DESIRED_SIGSIZE__TOTAL_DESIRED__MASK                        0x0ff00000U
#define DESIRED_SIGSIZE__TOTAL_DESIRED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0ff00000U) >> 20)
#define DESIRED_SIGSIZE__TOTAL_DESIRED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x0ff00000U)
#define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0ff00000U) | (((u_int32_t)(src) <<\
                    20) & 0x0ff00000U)
#define DESIRED_SIGSIZE__TOTAL_DESIRED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x0ff00000U)))

/* macros for field init_gc_count_max */
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__SHIFT                            28
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WIDTH                             2
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MASK                    0x30000000U
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x30000000U) >> 28)
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x30000000U)
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((u_int32_t)(src) <<\
                    28) & 0x30000000U)
#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field reduce_init_gc_count */
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SHIFT                         30
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WIDTH                          1
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MASK                 0x40000000U
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field ena_init_gain */
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SHIFT                                31
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WIDTH                                 1
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MASK                        0x80000000U
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define DESIRED_SIGSIZE__ENA_INIT_GAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define DESIRED_SIGSIZE__TYPE                                         u_int32_t
#define DESIRED_SIGSIZE__READ                                       0xfff000ffU
#define DESIRED_SIGSIZE__WRITE                                      0xfff000ffU

#endif /* __DESIRED_SIGSIZE_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_desired_sigsize */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_DESIRED_SIGSIZE__NUM              1

/* macros for BlueprintGlobalNameSpace::find_signal */
#ifndef __FIND_SIGNAL_MACRO__
#define __FIND_SIGNAL_MACRO__

/* macros for field relstep */
#define FIND_SIGNAL__RELSTEP__SHIFT                                           0
#define FIND_SIGNAL__RELSTEP__WIDTH                                           6
#define FIND_SIGNAL__RELSTEP__MASK                                  0x0000003fU
#define FIND_SIGNAL__RELSTEP__READ(src)          (u_int32_t)(src) & 0x0000003fU
#define FIND_SIGNAL__RELSTEP__WRITE(src)       ((u_int32_t)(src) & 0x0000003fU)
#define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define FIND_SIGNAL__RELSTEP__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field relpwr */
#define FIND_SIGNAL__RELPWR__SHIFT                                            6
#define FIND_SIGNAL__RELPWR__WIDTH                                            6
#define FIND_SIGNAL__RELPWR__MASK                                   0x00000fc0U
#define FIND_SIGNAL__RELPWR__READ(src)  (((u_int32_t)(src) & 0x00000fc0U) >> 6)
#define FIND_SIGNAL__RELPWR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000fc0U)
#define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define FIND_SIGNAL__RELPWR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field firstep */
#define FIND_SIGNAL__FIRSTEP__SHIFT                                          12
#define FIND_SIGNAL__FIRSTEP__WIDTH                                           6
#define FIND_SIGNAL__FIRSTEP__MASK                                  0x0003f000U
#define FIND_SIGNAL__FIRSTEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define FIND_SIGNAL__FIRSTEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define FIND_SIGNAL__FIRSTEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field firpwr */
#define FIND_SIGNAL__FIRPWR__SHIFT                                           18
#define FIND_SIGNAL__FIRPWR__WIDTH                                            8
#define FIND_SIGNAL__FIRPWR__MASK                                   0x03fc0000U
#define FIND_SIGNAL__FIRPWR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18)
#define FIND_SIGNAL__FIRPWR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x03fc0000U)
#define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x03fc0000U)
#define FIND_SIGNAL__FIRPWR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x03fc0000U)))

/* macros for field m1count_max */
#define FIND_SIGNAL__M1COUNT_MAX__SHIFT                                      26
#define FIND_SIGNAL__M1COUNT_MAX__WIDTH                                       6
#define FIND_SIGNAL__M1COUNT_MAX__MASK                              0xfc000000U
#define FIND_SIGNAL__M1COUNT_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfc000000U) >> 26)
#define FIND_SIGNAL__M1COUNT_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0xfc000000U)
#define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfc000000U) | (((u_int32_t)(src) <<\
                    26) & 0xfc000000U)
#define FIND_SIGNAL__M1COUNT_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0xfc000000U)))
#define FIND_SIGNAL__TYPE                                             u_int32_t
#define FIND_SIGNAL__READ                                           0xffffffffU
#define FIND_SIGNAL__WRITE                                          0xffffffffU

#endif /* __FIND_SIGNAL_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_find_signal */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_FIND_SIGNAL__NUM                  1

/* macros for BlueprintGlobalNameSpace::agc */
#ifndef __AGC_MACRO__
#define __AGC_MACRO__

/* macros for field coarsepwr_const */
#define AGC__COARSEPWR_CONST__SHIFT                                           0
#define AGC__COARSEPWR_CONST__WIDTH                                           7
#define AGC__COARSEPWR_CONST__MASK                                  0x0000007fU
#define AGC__COARSEPWR_CONST__READ(src)          (u_int32_t)(src) & 0x0000007fU
#define AGC__COARSEPWR_CONST__WRITE(src)       ((u_int32_t)(src) & 0x0000007fU)
#define AGC__COARSEPWR_CONST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define AGC__COARSEPWR_CONST__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field coarse_low */
#define AGC__COARSE_LOW__SHIFT                                                7
#define AGC__COARSE_LOW__WIDTH                                                8
#define AGC__COARSE_LOW__MASK                                       0x00007f80U
#define AGC__COARSE_LOW__READ(src)      (((u_int32_t)(src) & 0x00007f80U) >> 7)
#define AGC__COARSE_LOW__WRITE(src)     (((u_int32_t)(src) << 7) & 0x00007f80U)
#define AGC__COARSE_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00007f80U)
#define AGC__COARSE_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00007f80U)))

/* macros for field coarse_high */
#define AGC__COARSE_HIGH__SHIFT                                              15
#define AGC__COARSE_HIGH__WIDTH                                               7
#define AGC__COARSE_HIGH__MASK                                      0x003f8000U
#define AGC__COARSE_HIGH__READ(src)    (((u_int32_t)(src) & 0x003f8000U) >> 15)
#define AGC__COARSE_HIGH__WRITE(src)   (((u_int32_t)(src) << 15) & 0x003f8000U)
#define AGC__COARSE_HIGH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x003f8000U)
#define AGC__COARSE_HIGH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x003f8000U)))

/* macros for field quick_drop */
#define AGC__QUICK_DROP__SHIFT                                               22
#define AGC__QUICK_DROP__WIDTH                                                8
#define AGC__QUICK_DROP__MASK                                       0x3fc00000U
#define AGC__QUICK_DROP__READ(src)     (((u_int32_t)(src) & 0x3fc00000U) >> 22)
#define AGC__QUICK_DROP__WRITE(src)    (((u_int32_t)(src) << 22) & 0x3fc00000U)
#define AGC__QUICK_DROP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x3fc00000U)
#define AGC__QUICK_DROP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x3fc00000U)))

/* macros for field rssi_out_select */
#define AGC__RSSI_OUT_SELECT__SHIFT                                          30
#define AGC__RSSI_OUT_SELECT__WIDTH                                           2
#define AGC__RSSI_OUT_SELECT__MASK                                  0xc0000000U
#define AGC__RSSI_OUT_SELECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define AGC__RSSI_OUT_SELECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define AGC__RSSI_OUT_SELECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define AGC__TYPE                                                     u_int32_t
#define AGC__READ                                                   0xffffffffU
#define AGC__WRITE                                                  0xffffffffU

#endif /* __AGC_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_agc */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC__NUM                          1

/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b0 */
#ifndef __EXT_ATTEN_SWITCH_CTL_B0_MACRO__
#define __EXT_ATTEN_SWITCH_CTL_B0_MACRO__

/* macros for field xatten1_db_0 */
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__SHIFT                          0
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WIDTH                          6
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MASK                 0x0000003fU
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field xatten2_db_0 */
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__SHIFT                          6
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WIDTH                          6
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MASK                 0x00000fc0U
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field xatten1_margin_0 */
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__SHIFT                     12
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WIDTH                      5
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MASK             0x0001f000U
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field xatten2_margin_0 */
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__SHIFT                     17
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WIDTH                      5
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MASK             0x003e0000U
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003e0000U) >> 17)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x003e0000U)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field xlna_gain_db_0 */
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__SHIFT                       22
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WIDTH                        5
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MASK               0x07c00000U
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))
#define EXT_ATTEN_SWITCH_CTL_B0__TYPE                                 u_int32_t
#define EXT_ATTEN_SWITCH_CTL_B0__READ                               0x07ffffffU
#define EXT_ATTEN_SWITCH_CTL_B0__WRITE                              0x07ffffffU

#endif /* __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_atten_switch_ctl_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B0__NUM      1

/* macros for BlueprintGlobalNameSpace::cca_b0 */
#ifndef __CCA_B0_MACRO__
#define __CCA_B0_MACRO__

/* macros for field cf_maxCCApwr_0 */
#define CCA_B0__CF_MAXCCAPWR_0__SHIFT                                         0
#define CCA_B0__CF_MAXCCAPWR_0__WIDTH                                         9
#define CCA_B0__CF_MAXCCAPWR_0__MASK                                0x000001ffU
#define CCA_B0__CF_MAXCCAPWR_0__READ(src)        (u_int32_t)(src) & 0x000001ffU
#define CCA_B0__CF_MAXCCAPWR_0__WRITE(src)     ((u_int32_t)(src) & 0x000001ffU)
#define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define CCA_B0__CF_MAXCCAPWR_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field cf_cca_count_maxC */
#define CCA_B0__CF_CCA_COUNT_MAXC__SHIFT                                      9
#define CCA_B0__CF_CCA_COUNT_MAXC__WIDTH                                      3
#define CCA_B0__CF_CCA_COUNT_MAXC__MASK                             0x00000e00U
#define CCA_B0__CF_CCA_COUNT_MAXC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000e00U) >> 9)
#define CCA_B0__CF_CCA_COUNT_MAXC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000e00U)
#define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define CCA_B0__CF_CCA_COUNT_MAXC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field cf_thresh62 */
#define CCA_B0__CF_THRESH62__SHIFT                                           12
#define CCA_B0__CF_THRESH62__WIDTH                                            8
#define CCA_B0__CF_THRESH62__MASK                                   0x000ff000U
#define CCA_B0__CF_THRESH62__READ(src) (((u_int32_t)(src) & 0x000ff000U) >> 12)
#define CCA_B0__CF_THRESH62__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x000ff000U)
#define CCA_B0__CF_THRESH62__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x000ff000U)
#define CCA_B0__CF_THRESH62__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x000ff000U)))

/* macros for field minCCApwr_0 */
#define CCA_B0__MINCCAPWR_0__SHIFT                                           20
#define CCA_B0__MINCCAPWR_0__WIDTH                                            9
#define CCA_B0__MINCCAPWR_0__MASK                                   0x1ff00000U
#define CCA_B0__MINCCAPWR_0__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
#define CCA_B0__TYPE                                                  u_int32_t
#define CCA_B0__READ                                                0x1fffffffU
#define CCA_B0__WRITE                                               0x1fffffffU

#endif /* __CCA_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_cca_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCA_B0__NUM                       1

/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b0 */
#ifndef __CCA_CTRL_2_B0_MACRO__
#define __CCA_CTRL_2_B0_MACRO__

/* macros for field minCCApwr_thr_0 */
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__SHIFT                                 0
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WIDTH                                 9
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MASK                        0x000001ffU
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field enable_minCCApwr_thr */
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SHIFT                            9
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WIDTH                            1
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MASK                   0x00000200U
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field NF_gain_comp_0 */
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__SHIFT                                 10
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WIDTH                                  8
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MASK                         0x0003fc00U
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fc00U) >> 10)
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0003fc00U)
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0003fc00U)
#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0003fc00U)))

/* macros for field thresh62_mode */
#define CCA_CTRL_2_B0__THRESH62_MODE__SHIFT                                  18
#define CCA_CTRL_2_B0__THRESH62_MODE__WIDTH                                   1
#define CCA_CTRL_2_B0__THRESH62_MODE__MASK                          0x00040000U
#define CCA_CTRL_2_B0__THRESH62_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define CCA_CTRL_2_B0__THRESH62_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define CCA_CTRL_2_B0__THRESH62_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define CCA_CTRL_2_B0__THRESH62_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define CCA_CTRL_2_B0__THRESH62_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)
#define CCA_CTRL_2_B0__TYPE                                           u_int32_t
#define CCA_CTRL_2_B0__READ                                         0x0007ffffU
#define CCA_CTRL_2_B0__WRITE                                        0x0007ffffU

#endif /* __CCA_CTRL_2_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_cca_ctrl_2_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCA_CTRL_2_B0__NUM                1

/* macros for BlueprintGlobalNameSpace::restart */
#ifndef __RESTART_MACRO__
#define __RESTART_MACRO__

/* macros for field enable_restart */
#define RESTART__ENABLE_RESTART__SHIFT                                        0
#define RESTART__ENABLE_RESTART__WIDTH                                        1
#define RESTART__ENABLE_RESTART__MASK                               0x00000001U
#define RESTART__ENABLE_RESTART__READ(src)       (u_int32_t)(src) & 0x00000001U
#define RESTART__ENABLE_RESTART__WRITE(src)    ((u_int32_t)(src) & 0x00000001U)
#define RESTART__ENABLE_RESTART__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RESTART__ENABLE_RESTART__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RESTART__ENABLE_RESTART__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RESTART__ENABLE_RESTART__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field restart_lgfirpwr_delta */
#define RESTART__RESTART_LGFIRPWR_DELTA__SHIFT                                1
#define RESTART__RESTART_LGFIRPWR_DELTA__WIDTH                                5
#define RESTART__RESTART_LGFIRPWR_DELTA__MASK                       0x0000003eU
#define RESTART__RESTART_LGFIRPWR_DELTA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003eU) >> 1)
#define RESTART__RESTART_LGFIRPWR_DELTA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000003eU)
#define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000003eU)
#define RESTART__RESTART_LGFIRPWR_DELTA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000003eU)))

/* macros for field enable_pwr_drop_err */
#define RESTART__ENABLE_PWR_DROP_ERR__SHIFT                                   6
#define RESTART__ENABLE_PWR_DROP_ERR__WIDTH                                   1
#define RESTART__ENABLE_PWR_DROP_ERR__MASK                          0x00000040U
#define RESTART__ENABLE_PWR_DROP_ERR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define RESTART__ENABLE_PWR_DROP_ERR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define RESTART__ENABLE_PWR_DROP_ERR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define RESTART__ENABLE_PWR_DROP_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define RESTART__ENABLE_PWR_DROP_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field pwrdrop_lgfirpwr_delta */
#define RESTART__PWRDROP_LGFIRPWR_DELTA__SHIFT                                7
#define RESTART__PWRDROP_LGFIRPWR_DELTA__WIDTH                                5
#define RESTART__PWRDROP_LGFIRPWR_DELTA__MASK                       0x00000f80U
#define RESTART__PWRDROP_LGFIRPWR_DELTA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f80U) >> 7)
#define RESTART__PWRDROP_LGFIRPWR_DELTA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000f80U)
#define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00000f80U)
#define RESTART__PWRDROP_LGFIRPWR_DELTA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000f80U)))

/* macros for field ofdm_cck_rssi_bias */
#define RESTART__OFDM_CCK_RSSI_BIAS__SHIFT                                   12
#define RESTART__OFDM_CCK_RSSI_BIAS__WIDTH                                    6
#define RESTART__OFDM_CCK_RSSI_BIAS__MASK                           0x0003f000U
#define RESTART__OFDM_CCK_RSSI_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define RESTART__OFDM_CCK_RSSI_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define RESTART__OFDM_CCK_RSSI_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field ant_fast_div_gc_limit */
#define RESTART__ANT_FAST_DIV_GC_LIMIT__SHIFT                                18
#define RESTART__ANT_FAST_DIV_GC_LIMIT__WIDTH                                 3
#define RESTART__ANT_FAST_DIV_GC_LIMIT__MASK                        0x001c0000U
#define RESTART__ANT_FAST_DIV_GC_LIMIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001c0000U) >> 18)
#define RESTART__ANT_FAST_DIV_GC_LIMIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x001c0000U)
#define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x001c0000U)
#define RESTART__ANT_FAST_DIV_GC_LIMIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x001c0000U)))

/* macros for field enable_ant_fast_div_m2flag */
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SHIFT                           21
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WIDTH                            1
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MASK                   0x00200000U
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field weak_rssi_vote_thr */
#define RESTART__WEAK_RSSI_VOTE_THR__SHIFT                                   22
#define RESTART__WEAK_RSSI_VOTE_THR__WIDTH                                    7
#define RESTART__WEAK_RSSI_VOTE_THR__MASK                           0x1fc00000U
#define RESTART__WEAK_RSSI_VOTE_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1fc00000U) >> 22)
#define RESTART__WEAK_RSSI_VOTE_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x1fc00000U)
#define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x1fc00000U)
#define RESTART__WEAK_RSSI_VOTE_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x1fc00000U)))

/* macros for field enable_pwr_drop_err_cck */
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SHIFT                              29
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WIDTH                               1
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MASK                      0x20000000U
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define RESTART__ENABLE_PWR_DROP_ERR_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field disable_dc_restart */
#define RESTART__DISABLE_DC_RESTART__SHIFT                                   30
#define RESTART__DISABLE_DC_RESTART__WIDTH                                    1
#define RESTART__DISABLE_DC_RESTART__MASK                           0x40000000U
#define RESTART__DISABLE_DC_RESTART__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define RESTART__DISABLE_DC_RESTART__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define RESTART__DISABLE_DC_RESTART__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define RESTART__DISABLE_DC_RESTART__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define RESTART__DISABLE_DC_RESTART__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field restart_mode_bw40 */
#define RESTART__RESTART_MODE_BW40__SHIFT                                    31
#define RESTART__RESTART_MODE_BW40__WIDTH                                     1
#define RESTART__RESTART_MODE_BW40__MASK                            0x80000000U
#define RESTART__RESTART_MODE_BW40__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define RESTART__RESTART_MODE_BW40__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RESTART__RESTART_MODE_BW40__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RESTART__RESTART_MODE_BW40__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RESTART__RESTART_MODE_BW40__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RESTART__TYPE                                                 u_int32_t
#define RESTART__READ                                               0xffffffffU
#define RESTART__WRITE                                              0xffffffffU

#endif /* __RESTART_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_restart */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RESTART__NUM                      1

/* macros for BlueprintGlobalNameSpace::multichain_gain_ctrl */
#ifndef __MULTICHAIN_GAIN_CTRL_MACRO__
#define __MULTICHAIN_GAIN_CTRL_MACRO__

/* macros for field quickdrop_low */
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__SHIFT                            0
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WIDTH                            8
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MASK                   0x000000ffU
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field enable_check_strong_ant */
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SHIFT                  8
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WIDTH                  1
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MASK         0x00000100U
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field ant_fast_div_bias */
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__SHIFT                        9
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WIDTH                        6
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK               0x00007e00U
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007e00U) >> 9)
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00007e00U)
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00007e00U)
#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00007e00U)))

/* macros for field cap_gain_ratio_SNR */
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__SHIFT                      15
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WIDTH                       6
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MASK              0x001f8000U
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f8000U) >> 15)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x001f8000U)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x001f8000U)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x001f8000U)))

/* macros for field cap_gain_ratio_ena */
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SHIFT                      21
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WIDTH                       1
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MASK              0x00200000U
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field cap_gain_ratio_mode */
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SHIFT                     22
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WIDTH                      1
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MASK             0x00400000U
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field enable_ant_sw_rx_prot */
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT                   23
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WIDTH                    1
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MASK           0x00800000U
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field enable_ant_div_lnadiv */
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SHIFT                   24
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WIDTH                    1
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MASK           0x01000000U
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field ant_div_alt_lnaconf */
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT                     25
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WIDTH                      2
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK             0x06000000U
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x06000000U) >> 25)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x06000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x06000000U) | (((u_int32_t)(src) <<\
                    25) & 0x06000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x06000000U)))

/* macros for field ant_div_main_lnaconf */
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT                    27
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WIDTH                     2
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK            0x18000000U
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x18000000U) >> 27)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x18000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x18000000U) | (((u_int32_t)(src) <<\
                    27) & 0x18000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x18000000U)))

/* macros for field ant_div_alt_gaintb */
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SHIFT                      29
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WIDTH                       1
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK              0x20000000U
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field ant_div_main_gaintb */
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SHIFT                     30
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WIDTH                      1
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK             0x40000000U
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field ant_div_sw_com_lock */
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SHIFT                     31
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WIDTH                      1
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MASK             0x80000000U
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define MULTICHAIN_GAIN_CTRL__TYPE                                    u_int32_t
#define MULTICHAIN_GAIN_CTRL__READ                                  0xffffffffU
#define MULTICHAIN_GAIN_CTRL__WRITE                                 0xffffffffU

#endif /* __MULTICHAIN_GAIN_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_multichain_gain_ctrl */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_MULTICHAIN_GAIN_CTRL__NUM         1

/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_1 */
#ifndef __EXT_CHAN_PWR_THR_1_MACRO__
#define __EXT_CHAN_PWR_THR_1_MACRO__

/* macros for field thresh62_ext */
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__SHIFT                               0
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WIDTH                               8
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MASK                      0x000000ffU
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field ant_div_alt_ant_minGainIdx */
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__SHIFT                 8
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WIDTH                 8
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MASK        0x0000ff00U
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field ant_div_alt_ant_deltaGainIdx */
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__SHIFT              16
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WIDTH               5
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MASK      0x001f0000U
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x001f0000U)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x001f0000U)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x001f0000U)))

/* macros for field ant_div_alt_ant_deltaNF */
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__SHIFT                   21
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WIDTH                    6
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MASK           0x07e00000U
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07e00000U) >> 21)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x07e00000U)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x07e00000U)
#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x07e00000U)))
#define EXT_CHAN_PWR_THR_1__TYPE                                      u_int32_t
#define EXT_CHAN_PWR_THR_1__READ                                    0x07ffffffU
#define EXT_CHAN_PWR_THR_1__WRITE                                   0x07ffffffU

#endif /* __EXT_CHAN_PWR_THR_1_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_chan_pwr_thr_1 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_CHAN_PWR_THR_1__NUM           1

/* macros for BlueprintGlobalNameSpace::ext_chan_detect_win */
#ifndef __EXT_CHAN_DETECT_WIN_MACRO__
#define __EXT_CHAN_DETECT_WIN_MACRO__

/* macros for field det_diff_win_weak */
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__SHIFT                         0
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WIDTH                         4
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MASK                0x0000000fU
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field det_diff_win_weak_low */
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__SHIFT                     4
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WIDTH                     4
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MASK            0x000000f0U
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field det_diff_win_weak_cck */
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__SHIFT                     8
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WIDTH                     5
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MASK            0x00001f00U
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00001f00U)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00001f00U)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00001f00U)))

/* macros for field det_20h_count */
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__SHIFT                            13
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WIDTH                             3
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MASK                    0x0000e000U
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000e000U) >> 13)
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0000e000U)
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0000e000U)
#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0000e000U)))

/* macros for field det_ext_blk_count */
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__SHIFT                        16
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WIDTH                         3
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MASK                0x00070000U
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00070000U) >> 16)
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00070000U)
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((u_int32_t)(src) <<\
                    16) & 0x00070000U)
#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field weak_sig_thr_cck_ext */
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__SHIFT                     19
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WIDTH                      6
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MASK             0x01f80000U
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f80000U) >> 19)
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x01f80000U)
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f80000U) | (((u_int32_t)(src) <<\
                    19) & 0x01f80000U)
#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x01f80000U)))

/* macros for field det_diff_win_thresh */
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__SHIFT                      25
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WIDTH                       4
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MASK              0x1e000000U
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1e000000U) >> 25)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x1e000000U)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x1e000000U)
#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x1e000000U)))
#define EXT_CHAN_DETECT_WIN__TYPE                                     u_int32_t
#define EXT_CHAN_DETECT_WIN__READ                                   0x1fffffffU
#define EXT_CHAN_DETECT_WIN__WRITE                                  0x1fffffffU

#endif /* __EXT_CHAN_DETECT_WIN_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_chan_detect_win */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_CHAN_DETECT_WIN__NUM          1

/* macros for BlueprintGlobalNameSpace::pwr_thr_20_40_det */
#ifndef __PWR_THR_20_40_DET_MACRO__
#define __PWR_THR_20_40_DET_MACRO__

/* macros for field pwrdiff40_thrstr */
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__SHIFT                            0
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WIDTH                            5
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MASK                   0x0000001fU
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field blocker40_max */
#define PWR_THR_20_40_DET__BLOCKER40_MAX__SHIFT                               5
#define PWR_THR_20_40_DET__BLOCKER40_MAX__WIDTH                               6
#define PWR_THR_20_40_DET__BLOCKER40_MAX__MASK                      0x000007e0U
#define PWR_THR_20_40_DET__BLOCKER40_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000007e0U) >> 5)
#define PWR_THR_20_40_DET__BLOCKER40_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000007e0U)
#define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000007e0U)
#define PWR_THR_20_40_DET__BLOCKER40_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000007e0U)))

/* macros for field det40_pwrstep_max */
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__SHIFT                          11
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WIDTH                           5
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MASK                  0x0000f800U
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f800U) >> 11)
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x0000f800U)
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f800U) | (((u_int32_t)(src) <<\
                    11) & 0x0000f800U)
#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x0000f800U)))

/* macros for field det40_thr_snr */
#define PWR_THR_20_40_DET__DET40_THR_SNR__SHIFT                              16
#define PWR_THR_20_40_DET__DET40_THR_SNR__WIDTH                               8
#define PWR_THR_20_40_DET__DET40_THR_SNR__MASK                      0x00ff0000U
#define PWR_THR_20_40_DET__DET40_THR_SNR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define PWR_THR_20_40_DET__DET40_THR_SNR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define PWR_THR_20_40_DET__DET40_THR_SNR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field det40_pri_bias */
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__SHIFT                             24
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WIDTH                              5
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MASK                     0x1f000000U
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f000000U) >> 24)
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x1f000000U)
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x1f000000U)
#define PWR_THR_20_40_DET__DET40_PRI_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x1f000000U)))

/* macros for field pwrstep40_ena */
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SHIFT                              29
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WIDTH                               1
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MASK                      0x20000000U
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define PWR_THR_20_40_DET__PWRSTEP40_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field lowsnr40_ena */
#define PWR_THR_20_40_DET__LOWSNR40_ENA__SHIFT                               30
#define PWR_THR_20_40_DET__LOWSNR40_ENA__WIDTH                                1
#define PWR_THR_20_40_DET__LOWSNR40_ENA__MASK                       0x40000000U
#define PWR_THR_20_40_DET__LOWSNR40_ENA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define PWR_THR_20_40_DET__LOWSNR40_ENA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define PWR_THR_20_40_DET__LOWSNR40_ENA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define PWR_THR_20_40_DET__LOWSNR40_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define PWR_THR_20_40_DET__LOWSNR40_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)
#define PWR_THR_20_40_DET__TYPE                                       u_int32_t
#define PWR_THR_20_40_DET__READ                                     0x7fffffffU
#define PWR_THR_20_40_DET__WRITE                                    0x7fffffffU

#endif /* __PWR_THR_20_40_DET_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_pwr_thr_20_40_det */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PWR_THR_20_40_DET__NUM            1

/* macros for BlueprintGlobalNameSpace::rifs_srch */
#ifndef __RIFS_SRCH_MACRO__
#define __RIFS_SRCH_MACRO__

/* macros for field init_gain_dB_offset */
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__SHIFT                                 8
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WIDTH                                 8
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MASK                        0x0000ff00U
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field rifs_init_delay */
#define RIFS_SRCH__RIFS_INIT_DELAY__SHIFT                                    16
#define RIFS_SRCH__RIFS_INIT_DELAY__WIDTH                                    10
#define RIFS_SRCH__RIFS_INIT_DELAY__MASK                            0x03ff0000U
#define RIFS_SRCH__RIFS_INIT_DELAY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03ff0000U) >> 16)
#define RIFS_SRCH__RIFS_INIT_DELAY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x03ff0000U)
#define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x03ff0000U)
#define RIFS_SRCH__RIFS_INIT_DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x03ff0000U)))

/* macros for field rifs_disable_pwrlow_gc */
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SHIFT                             26
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WIDTH                              1
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MASK                     0x04000000U
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field rifs_disable_cck_det */
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SHIFT                               27
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WIDTH                                1
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MASK                       0x08000000U
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)
#define RIFS_SRCH__TYPE                                               u_int32_t
#define RIFS_SRCH__READ                                             0x0fffff00U
#define RIFS_SRCH__WRITE                                            0x0fffff00U

#endif /* __RIFS_SRCH_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_rifs_srch */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RIFS_SRCH__NUM                    1

/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_1 */
#ifndef __PEAK_DET_CTRL_1_MACRO__
#define __PEAK_DET_CTRL_1_MACRO__

/* macros for field use_oc_gain_table */
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SHIFT                             0
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WIDTH                             1
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MASK                    0x00000001U
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field use_peak_det */
#define PEAK_DET_CTRL_1__USE_PEAK_DET__SHIFT                                  1
#define PEAK_DET_CTRL_1__USE_PEAK_DET__WIDTH                                  1
#define PEAK_DET_CTRL_1__USE_PEAK_DET__MASK                         0x00000002U
#define PEAK_DET_CTRL_1__USE_PEAK_DET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PEAK_DET_CTRL_1__USE_PEAK_DET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PEAK_DET_CTRL_1__USE_PEAK_DET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PEAK_DET_CTRL_1__USE_PEAK_DET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PEAK_DET_CTRL_1__USE_PEAK_DET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field peak_det_win_len */
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__SHIFT                              2
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WIDTH                              6
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MASK                     0x000000fcU
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000fcU) >> 2)
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x000000fcU)
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000fcU) | (((u_int32_t)(src) <<\
                    2) & 0x000000fcU)
#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x000000fcU)))

/* macros for field peak_det_tally_thr_low_0 */
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__SHIFT                      8
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WIDTH                      5
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MASK             0x00001f00U
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00001f00U)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00001f00U)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00001f00U)))

/* macros for field peak_det_tally_thr_med_0 */
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__SHIFT                     13
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WIDTH                      5
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MASK             0x0003e000U
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003e000U) >> 13)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0003e000U)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0003e000U)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0003e000U)))

/* macros for field peak_det_tally_thr_high_0 */
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__SHIFT                    18
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WIDTH                     5
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MASK            0x007c0000U
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007c0000U) >> 18)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x007c0000U)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x007c0000U)
#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x007c0000U)))

/* macros for field peak_det_settling */
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__SHIFT                            23
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WIDTH                             7
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MASK                    0x3f800000U
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f800000U) >> 23)
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x3f800000U)
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))

/* macros for field pwd_pkdet_during_cal */
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SHIFT                         30
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WIDTH                          1
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MASK                 0x40000000U
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field pwd_pkdet_during_rx */
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SHIFT                          31
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WIDTH                           1
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MASK                  0x80000000U
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define PEAK_DET_CTRL_1__TYPE                                         u_int32_t
#define PEAK_DET_CTRL_1__READ                                       0xffffffffU
#define PEAK_DET_CTRL_1__WRITE                                      0xffffffffU

#endif /* __PEAK_DET_CTRL_1_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_ctrl_1 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_1__NUM              1

/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_2 */
#ifndef __PEAK_DET_CTRL_2_MACRO__
#define __PEAK_DET_CTRL_2_MACRO__

/* macros for field rfsat_2_add_rfgain_del */
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__SHIFT                        0
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WIDTH                       10
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MASK               0x000003ffU
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field rf_gain_drop_db_low_0 */
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__SHIFT                        10
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WIDTH                         5
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MASK                0x00007c00U
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field rf_gain_drop_db_med_0 */
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__SHIFT                        15
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WIDTH                         5
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MASK                0x000f8000U
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field rf_gain_drop_db_high_0 */
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__SHIFT                       20
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WIDTH                        5
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MASK               0x01f00000U
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field rf_gain_drop_db_non_0 */
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__SHIFT                        25
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WIDTH                         5
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MASK                0x3e000000U
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))

/* macros for field enable_rfsat_restart */
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SHIFT                         30
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WIDTH                          1
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MASK                 0x40000000U
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)
#define PEAK_DET_CTRL_2__TYPE                                         u_int32_t
#define PEAK_DET_CTRL_2__READ                                       0x7fffffffU
#define PEAK_DET_CTRL_2__WRITE                                      0x7fffffffU

#endif /* __PEAK_DET_CTRL_2_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_ctrl_2 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_2__NUM              1

/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_1 */
#ifndef __RX_GAIN_BOUNDS_1_MACRO__
#define __RX_GAIN_BOUNDS_1_MACRO__

/* macros for field rx_max_mb_gain */
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__SHIFT                               0
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WIDTH                               8
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MASK                      0x000000ffU
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field rx_max_rf_gain_ref */
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__SHIFT                           8
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WIDTH                           8
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MASK                  0x0000ff00U
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field rx_max_rf_gain */
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__SHIFT                              16
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WIDTH                               8
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MASK                      0x00ff0000U
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field rx_ocgain_sel_2G */
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SHIFT                            24
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WIDTH                             1
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MASK                    0x01000000U
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field rx_ocgain_sel_5G */
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SHIFT                            25
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WIDTH                             1
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MASK                    0x02000000U
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field rf_mb_gain_delta_max_db */
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__SHIFT                     26
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WIDTH                      6
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MASK             0xfc000000U
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfc000000U) >> 26)
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0xfc000000U)
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfc000000U) | (((u_int32_t)(src) <<\
                    26) & 0xfc000000U)
#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0xfc000000U)))
#define RX_GAIN_BOUNDS_1__TYPE                                        u_int32_t
#define RX_GAIN_BOUNDS_1__READ                                      0xffffffffU
#define RX_GAIN_BOUNDS_1__WRITE                                     0xffffffffU

#endif /* __RX_GAIN_BOUNDS_1_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_gain_bounds_1 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_1__NUM             1

/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_2 */
#ifndef __RX_GAIN_BOUNDS_2_MACRO__
#define __RX_GAIN_BOUNDS_2_MACRO__

/* macros for field gc_rssi_low_db */
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__SHIFT                               0
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WIDTH                               8
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MASK                      0x000000ffU
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field rf_gain_ref_base_addr */
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__SHIFT                        8
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WIDTH                        8
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MASK               0x0000ff00U
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field rf_gain_base_addr */
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__SHIFT                           16
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WIDTH                            8
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MASK                   0x00ff0000U
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field rf_gain_div_base_addr */
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__SHIFT                       24
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WIDTH                        8
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MASK               0xff000000U
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define RX_GAIN_BOUNDS_2__TYPE                                        u_int32_t
#define RX_GAIN_BOUNDS_2__READ                                      0xffffffffU
#define RX_GAIN_BOUNDS_2__WRITE                                     0xffffffffU

#endif /* __RX_GAIN_BOUNDS_2_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_gain_bounds_2 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_2__NUM             1

/* macros for BlueprintGlobalNameSpace::peak_det_cal_ctrl */
#ifndef __PEAK_DET_CAL_CTRL_MACRO__
#define __PEAK_DET_CAL_CTRL_MACRO__

/* macros for field pkdet_cal_win_thr */
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__SHIFT                           0
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WIDTH                           6
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MASK                  0x0000003fU
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field pkdet_cal_bias */
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__SHIFT                              6
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WIDTH                              6
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MASK                     0x00000fc0U
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field pkdet_cal_meas_time_sel */
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__SHIFT                    12
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WIDTH                     2
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MASK            0x00003000U
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003000U) >> 12)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00003000U)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((u_int32_t)(src) <<\
                    12) & 0x00003000U)
#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00003000U)))
#define PEAK_DET_CAL_CTRL__TYPE                                       u_int32_t
#define PEAK_DET_CAL_CTRL__READ                                     0x00003fffU
#define PEAK_DET_CAL_CTRL__WRITE                                    0x00003fffU

#endif /* __PEAK_DET_CAL_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_cal_ctrl */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CAL_CTRL__NUM            1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_ctrl */
#ifndef __AGC_DIG_DC_CTRL_MACRO__
#define __AGC_DIG_DC_CTRL_MACRO__

/* macros for field use_dig_dc */
#define AGC_DIG_DC_CTRL__USE_DIG_DC__SHIFT                                    0
#define AGC_DIG_DC_CTRL__USE_DIG_DC__WIDTH                                    1
#define AGC_DIG_DC_CTRL__USE_DIG_DC__MASK                           0x00000001U
#define AGC_DIG_DC_CTRL__USE_DIG_DC__READ(src)   (u_int32_t)(src) & 0x00000001U
#define AGC_DIG_DC_CTRL__USE_DIG_DC__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define AGC_DIG_DC_CTRL__USE_DIG_DC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define AGC_DIG_DC_CTRL__USE_DIG_DC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define AGC_DIG_DC_CTRL__USE_DIG_DC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field dig_dc_scale_bias */
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__SHIFT                             1
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WIDTH                             3
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MASK                    0x0000000eU
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000eU) >> 1)
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000000eU)
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field dig_dc_correct_cap */
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__SHIFT                            4
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WIDTH                            6
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MASK                   0x000003f0U
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field dig_dc_switch_cck */
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SHIFT                            10
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WIDTH                             1
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MASK                    0x00000400U
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field dig_dc_mixer_sel_mask */
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__SHIFT                        16
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WIDTH                        16
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MASK                0xffff0000U
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define AGC_DIG_DC_CTRL__TYPE                                         u_int32_t
#define AGC_DIG_DC_CTRL__READ                                       0xffff07ffU
#define AGC_DIG_DC_CTRL__WRITE                                      0xffff07ffU

#endif /* __AGC_DIG_DC_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_ctrl */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_CTRL__NUM              1

/* macros for BlueprintGlobalNameSpace::bt_coex_1 */
#ifndef __BT_COEX_1_MACRO__
#define __BT_COEX_1_MACRO__

/* macros for field peak_det_tally_thr_low_1 */
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__SHIFT                            0
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WIDTH                            5
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MASK                   0x0000001fU
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field peak_det_tally_thr_med_1 */
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__SHIFT                            5
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WIDTH                            5
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MASK                   0x000003e0U
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field peak_det_tally_thr_high_1 */
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__SHIFT                          10
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WIDTH                           5
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MASK                  0x00007c00U
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field rf_gain_drop_db_low_1 */
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__SHIFT                              15
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WIDTH                               5
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MASK                      0x000f8000U
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field rf_gain_drop_db_med_1 */
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__SHIFT                              20
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WIDTH                               5
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MASK                      0x01f00000U
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field rf_gain_drop_db_high_1 */
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__SHIFT                             25
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WIDTH                              5
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MASK                     0x3e000000U
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))

/* macros for field bt_tx_disable_NF_cal */
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SHIFT                               30
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WIDTH                                1
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MASK                       0x40000000U
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field bt_rx_disable_NF_cal */
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__SHIFT                               31
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WIDTH                                1
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MASK                       0x80000000U
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define BT_COEX_1__TYPE                                               u_int32_t
#define BT_COEX_1__READ                                             0xffffffffU
#define BT_COEX_1__WRITE                                            0xffffffffU

#endif /* __BT_COEX_1_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_1 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_1__NUM                    1

/* macros for BlueprintGlobalNameSpace::bt_coex_2 */
#ifndef __BT_COEX_2_MACRO__
#define __BT_COEX_2_MACRO__

/* macros for field peak_det_tally_thr_low_2 */
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__SHIFT                            0
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WIDTH                            5
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MASK                   0x0000001fU
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field peak_det_tally_thr_med_2 */
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__SHIFT                            5
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WIDTH                            5
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MASK                   0x000003e0U
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field peak_det_tally_thr_high_2 */
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__SHIFT                          10
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WIDTH                           5
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MASK                  0x00007c00U
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field rf_gain_drop_db_low_2 */
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__SHIFT                              15
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WIDTH                               5
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MASK                      0x000f8000U
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field rf_gain_drop_db_med_2 */
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__SHIFT                              20
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WIDTH                               5
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MASK                      0x01f00000U
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field rf_gain_drop_db_high_2 */
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__SHIFT                             25
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WIDTH                              5
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MASK                     0x3e000000U
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))

/* macros for field rfsat_rx_rx */
#define BT_COEX_2__RFSAT_RX_RX__SHIFT                                        30
#define BT_COEX_2__RFSAT_RX_RX__WIDTH                                         2
#define BT_COEX_2__RFSAT_RX_RX__MASK                                0xc0000000U
#define BT_COEX_2__RFSAT_RX_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define BT_COEX_2__RFSAT_RX_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define BT_COEX_2__RFSAT_RX_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define BT_COEX_2__TYPE                                               u_int32_t
#define BT_COEX_2__READ                                             0xffffffffU
#define BT_COEX_2__WRITE                                            0xffffffffU

#endif /* __BT_COEX_2_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_2 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_2__NUM                    1

/* macros for BlueprintGlobalNameSpace::bt_coex_3 */
#ifndef __BT_COEX_3_MACRO__
#define __BT_COEX_3_MACRO__

/* macros for field rfsat_bt_srch_srch */
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__SHIFT                                  0
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WIDTH                                  2
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MASK                         0x00000003U
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__READ(src) (u_int32_t)(src) & 0x00000003U
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field rfsat_bt_rx_srch */
#define BT_COEX_3__RFSAT_BT_RX_SRCH__SHIFT                                    2
#define BT_COEX_3__RFSAT_BT_RX_SRCH__WIDTH                                    2
#define BT_COEX_3__RFSAT_BT_RX_SRCH__MASK                           0x0000000cU
#define BT_COEX_3__RFSAT_BT_RX_SRCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define BT_COEX_3__RFSAT_BT_RX_SRCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define BT_COEX_3__RFSAT_BT_RX_SRCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field rfsat_bt_srch_rx */
#define BT_COEX_3__RFSAT_BT_SRCH_RX__SHIFT                                    4
#define BT_COEX_3__RFSAT_BT_SRCH_RX__WIDTH                                    2
#define BT_COEX_3__RFSAT_BT_SRCH_RX__MASK                           0x00000030U
#define BT_COEX_3__RFSAT_BT_SRCH_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define BT_COEX_3__RFSAT_BT_SRCH_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define BT_COEX_3__RFSAT_BT_SRCH_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field rfsat_wlan_srch_srch */
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__SHIFT                                6
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WIDTH                                2
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MASK                       0x000000c0U
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field rfsat_wlan_rx_srch */
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__SHIFT                                  8
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WIDTH                                  2
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MASK                         0x00000300U
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field rfsat_wlan_srch_rx */
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__SHIFT                                 10
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WIDTH                                  2
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MASK                         0x00000c00U
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))

/* macros for field rfsat_eq_srch_srch */
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__SHIFT                                 12
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WIDTH                                  2
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MASK                         0x00003000U
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003000U) >> 12)
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00003000U)
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((u_int32_t)(src) <<\
                    12) & 0x00003000U)
#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field rfsat_eq_rx_srch */
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__SHIFT                                   14
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WIDTH                                    2
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MASK                           0x0000c000U
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000c000U) >> 14)
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0000c000U)
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0000c000U)
#define BT_COEX_3__RFSAT_EQ_RX_SRCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field rfsat_eq_srch_rx */
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__SHIFT                                   16
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WIDTH                                    2
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MASK                           0x00030000U
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00030000U) >> 16)
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00030000U)
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00030000U) | (((u_int32_t)(src) <<\
                    16) & 0x00030000U)
#define BT_COEX_3__RFSAT_EQ_SRCH_RX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00030000U)))

/* macros for field rf_gain_drop_db_non_1 */
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__SHIFT                              18
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WIDTH                               5
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MASK                      0x007c0000U
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007c0000U) >> 18)
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x007c0000U)
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x007c0000U)
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x007c0000U)))

/* macros for field rf_gain_drop_db_non_2 */
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__SHIFT                              23
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WIDTH                               5
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MASK                      0x0f800000U
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f800000U) >> 23)
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x0f800000U)
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x0f800000U)
#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x0f800000U)))

/* macros for field bt_rx_firpwr_incr */
#define BT_COEX_3__BT_RX_FIRPWR_INCR__SHIFT                                  28
#define BT_COEX_3__BT_RX_FIRPWR_INCR__WIDTH                                   4
#define BT_COEX_3__BT_RX_FIRPWR_INCR__MASK                          0xf0000000U
#define BT_COEX_3__BT_RX_FIRPWR_INCR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf0000000U) >> 28)
#define BT_COEX_3__BT_RX_FIRPWR_INCR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0xf0000000U)
#define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((u_int32_t)(src) <<\
                    28) & 0xf0000000U)
#define BT_COEX_3__BT_RX_FIRPWR_INCR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define BT_COEX_3__TYPE                                               u_int32_t
#define BT_COEX_3__READ                                             0xffffffffU
#define BT_COEX_3__WRITE                                            0xffffffffU

#endif /* __BT_COEX_3_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_3 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_3__NUM                    1

/* macros for BlueprintGlobalNameSpace::bt_coex_4 */
#ifndef __BT_COEX_4_MACRO__
#define __BT_COEX_4_MACRO__

/* macros for field rfgain_eqv_lna_0 */
#define BT_COEX_4__RFGAIN_EQV_LNA_0__SHIFT                                    0
#define BT_COEX_4__RFGAIN_EQV_LNA_0__WIDTH                                    8
#define BT_COEX_4__RFGAIN_EQV_LNA_0__MASK                           0x000000ffU
#define BT_COEX_4__RFGAIN_EQV_LNA_0__READ(src)   (u_int32_t)(src) & 0x000000ffU
#define BT_COEX_4__RFGAIN_EQV_LNA_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define BT_COEX_4__RFGAIN_EQV_LNA_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field rfgain_eqv_lna_1 */
#define BT_COEX_4__RFGAIN_EQV_LNA_1__SHIFT                                    8
#define BT_COEX_4__RFGAIN_EQV_LNA_1__WIDTH                                    8
#define BT_COEX_4__RFGAIN_EQV_LNA_1__MASK                           0x0000ff00U
#define BT_COEX_4__RFGAIN_EQV_LNA_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define BT_COEX_4__RFGAIN_EQV_LNA_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define BT_COEX_4__RFGAIN_EQV_LNA_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field rfgain_eqv_lna_2 */
#define BT_COEX_4__RFGAIN_EQV_LNA_2__SHIFT                                   16
#define BT_COEX_4__RFGAIN_EQV_LNA_2__WIDTH                                    8
#define BT_COEX_4__RFGAIN_EQV_LNA_2__MASK                           0x00ff0000U
#define BT_COEX_4__RFGAIN_EQV_LNA_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define BT_COEX_4__RFGAIN_EQV_LNA_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define BT_COEX_4__RFGAIN_EQV_LNA_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field rfgain_eqv_lna_3 */
#define BT_COEX_4__RFGAIN_EQV_LNA_3__SHIFT                                   24
#define BT_COEX_4__RFGAIN_EQV_LNA_3__WIDTH                                    8
#define BT_COEX_4__RFGAIN_EQV_LNA_3__MASK                           0xff000000U
#define BT_COEX_4__RFGAIN_EQV_LNA_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define BT_COEX_4__RFGAIN_EQV_LNA_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define BT_COEX_4__RFGAIN_EQV_LNA_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define BT_COEX_4__TYPE                                               u_int32_t
#define BT_COEX_4__READ                                             0xffffffffU
#define BT_COEX_4__WRITE                                            0xffffffffU

#endif /* __BT_COEX_4_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_4 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_4__NUM                    1

/* macros for BlueprintGlobalNameSpace::bt_coex_5 */
#ifndef __BT_COEX_5_MACRO__
#define __BT_COEX_5_MACRO__

/* macros for field rfgain_eqv_lna_4 */
#define BT_COEX_5__RFGAIN_EQV_LNA_4__SHIFT                                    0
#define BT_COEX_5__RFGAIN_EQV_LNA_4__WIDTH                                    8
#define BT_COEX_5__RFGAIN_EQV_LNA_4__MASK                           0x000000ffU
#define BT_COEX_5__RFGAIN_EQV_LNA_4__READ(src)   (u_int32_t)(src) & 0x000000ffU
#define BT_COEX_5__RFGAIN_EQV_LNA_4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define BT_COEX_5__RFGAIN_EQV_LNA_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field rfgain_eqv_lna_5 */
#define BT_COEX_5__RFGAIN_EQV_LNA_5__SHIFT                                    8
#define BT_COEX_5__RFGAIN_EQV_LNA_5__WIDTH                                    8
#define BT_COEX_5__RFGAIN_EQV_LNA_5__MASK                           0x0000ff00U
#define BT_COEX_5__RFGAIN_EQV_LNA_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define BT_COEX_5__RFGAIN_EQV_LNA_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define BT_COEX_5__RFGAIN_EQV_LNA_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field rfgain_eqv_lna_6 */
#define BT_COEX_5__RFGAIN_EQV_LNA_6__SHIFT                                   16
#define BT_COEX_5__RFGAIN_EQV_LNA_6__WIDTH                                    8
#define BT_COEX_5__RFGAIN_EQV_LNA_6__MASK                           0x00ff0000U
#define BT_COEX_5__RFGAIN_EQV_LNA_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define BT_COEX_5__RFGAIN_EQV_LNA_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define BT_COEX_5__RFGAIN_EQV_LNA_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field rfgain_eqv_lna_7 */
#define BT_COEX_5__RFGAIN_EQV_LNA_7__SHIFT                                   24
#define BT_COEX_5__RFGAIN_EQV_LNA_7__WIDTH                                    8
#define BT_COEX_5__RFGAIN_EQV_LNA_7__MASK                           0xff000000U
#define BT_COEX_5__RFGAIN_EQV_LNA_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define BT_COEX_5__RFGAIN_EQV_LNA_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define BT_COEX_5__RFGAIN_EQV_LNA_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define BT_COEX_5__TYPE                                               u_int32_t
#define BT_COEX_5__READ                                             0xffffffffU
#define BT_COEX_5__WRITE                                            0xffffffffU

#endif /* __BT_COEX_5_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_5 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_5__NUM                    1

/* macros for BlueprintGlobalNameSpace::redpwr_ctrl_1 */
#ifndef __REDPWR_CTRL_1_MACRO__
#define __REDPWR_CTRL_1_MACRO__

/* macros for field redpwr_mode */
#define REDPWR_CTRL_1__REDPWR_MODE__SHIFT                                     0
#define REDPWR_CTRL_1__REDPWR_MODE__WIDTH                                     2
#define REDPWR_CTRL_1__REDPWR_MODE__MASK                            0x00000003U
#define REDPWR_CTRL_1__REDPWR_MODE__READ(src)    (u_int32_t)(src) & 0x00000003U
#define REDPWR_CTRL_1__REDPWR_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
#define REDPWR_CTRL_1__REDPWR_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define REDPWR_CTRL_1__REDPWR_MODE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field redpwr_mode_clr */
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__SHIFT                                 2
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__WIDTH                                 1
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__MASK                        0x00000004U
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define REDPWR_CTRL_1__REDPWR_MODE_CLR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field redpwr_mode_set */
#define REDPWR_CTRL_1__REDPWR_MODE_SET__SHIFT                                 3
#define REDPWR_CTRL_1__REDPWR_MODE_SET__WIDTH                                 1
#define REDPWR_CTRL_1__REDPWR_MODE_SET__MASK                        0x00000008U
#define REDPWR_CTRL_1__REDPWR_MODE_SET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define REDPWR_CTRL_1__REDPWR_MODE_SET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define REDPWR_CTRL_1__REDPWR_MODE_SET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define REDPWR_CTRL_1__REDPWR_MODE_SET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define REDPWR_CTRL_1__REDPWR_MODE_SET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define REDPWR_CTRL_1__REDPWR_MODE_SET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field gain_corr_db2 */
#define REDPWR_CTRL_1__GAIN_CORR_DB2__SHIFT                                   4
#define REDPWR_CTRL_1__GAIN_CORR_DB2__WIDTH                                   5
#define REDPWR_CTRL_1__GAIN_CORR_DB2__MASK                          0x000001f0U
#define REDPWR_CTRL_1__GAIN_CORR_DB2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001f0U) >> 4)
#define REDPWR_CTRL_1__GAIN_CORR_DB2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000001f0U)
#define REDPWR_CTRL_1__GAIN_CORR_DB2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000001f0U)
#define REDPWR_CTRL_1__GAIN_CORR_DB2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000001f0U)))

/* macros for field scfir_adj_gain */
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__SHIFT                                  9
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WIDTH                                  4
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MASK                         0x00001e00U
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001e00U) >> 9)
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00001e00U)
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00001e00U)
#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00001e00U)))

/* macros for field quickdrop_rf */
#define REDPWR_CTRL_1__QUICKDROP_RF__SHIFT                                   13
#define REDPWR_CTRL_1__QUICKDROP_RF__WIDTH                                    5
#define REDPWR_CTRL_1__QUICKDROP_RF__MASK                           0x0003e000U
#define REDPWR_CTRL_1__QUICKDROP_RF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003e000U) >> 13)
#define REDPWR_CTRL_1__QUICKDROP_RF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0003e000U)
#define REDPWR_CTRL_1__QUICKDROP_RF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0003e000U)
#define REDPWR_CTRL_1__QUICKDROP_RF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0003e000U)))

/* macros for field bypass_fir_f */
#define REDPWR_CTRL_1__BYPASS_FIR_F__SHIFT                                   18
#define REDPWR_CTRL_1__BYPASS_FIR_F__WIDTH                                    1
#define REDPWR_CTRL_1__BYPASS_FIR_F__MASK                           0x00040000U
#define REDPWR_CTRL_1__BYPASS_FIR_F__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define REDPWR_CTRL_1__BYPASS_FIR_F__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define REDPWR_CTRL_1__BYPASS_FIR_F__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define REDPWR_CTRL_1__BYPASS_FIR_F__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define REDPWR_CTRL_1__BYPASS_FIR_F__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define REDPWR_CTRL_1__BYPASS_FIR_F__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field adc_half_ref_f */
#define REDPWR_CTRL_1__ADC_HALF_REF_F__SHIFT                                 19
#define REDPWR_CTRL_1__ADC_HALF_REF_F__WIDTH                                  1
#define REDPWR_CTRL_1__ADC_HALF_REF_F__MASK                         0x00080000U
#define REDPWR_CTRL_1__ADC_HALF_REF_F__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define REDPWR_CTRL_1__ADC_HALF_REF_F__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define REDPWR_CTRL_1__ADC_HALF_REF_F__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define REDPWR_CTRL_1__ADC_HALF_REF_F__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define REDPWR_CTRL_1__ADC_HALF_REF_F__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define REDPWR_CTRL_1__ADC_HALF_REF_F__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)
#define REDPWR_CTRL_1__TYPE                                           u_int32_t
#define REDPWR_CTRL_1__READ                                         0x000fffffU
#define REDPWR_CTRL_1__WRITE                                        0x000fffffU

#endif /* __REDPWR_CTRL_1_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_redpwr_ctrl_1 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_REDPWR_CTRL_1__NUM                1

/* macros for BlueprintGlobalNameSpace::redpwr_ctrl_2 */
#ifndef __REDPWR_CTRL_2_MACRO__
#define __REDPWR_CTRL_2_MACRO__

/* macros for field sc01_sw_index */
#define REDPWR_CTRL_2__SC01_SW_INDEX__SHIFT                                   0
#define REDPWR_CTRL_2__SC01_SW_INDEX__WIDTH                                   7
#define REDPWR_CTRL_2__SC01_SW_INDEX__MASK                          0x0000007fU
#define REDPWR_CTRL_2__SC01_SW_INDEX__READ(src)  (u_int32_t)(src) & 0x0000007fU
#define REDPWR_CTRL_2__SC01_SW_INDEX__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define REDPWR_CTRL_2__SC01_SW_INDEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define REDPWR_CTRL_2__SC01_SW_INDEX__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field sc10_sw_index */
#define REDPWR_CTRL_2__SC10_SW_INDEX__SHIFT                                   7
#define REDPWR_CTRL_2__SC10_SW_INDEX__WIDTH                                   7
#define REDPWR_CTRL_2__SC10_SW_INDEX__MASK                          0x00003f80U
#define REDPWR_CTRL_2__SC10_SW_INDEX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f80U) >> 7)
#define REDPWR_CTRL_2__SC10_SW_INDEX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00003f80U)
#define REDPWR_CTRL_2__SC10_SW_INDEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00003f80U)
#define REDPWR_CTRL_2__SC10_SW_INDEX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00003f80U)))

/* macros for field last_sc0_index */
#define REDPWR_CTRL_2__LAST_SC0_INDEX__SHIFT                                 14
#define REDPWR_CTRL_2__LAST_SC0_INDEX__WIDTH                                  7
#define REDPWR_CTRL_2__LAST_SC0_INDEX__MASK                         0x001fc000U
#define REDPWR_CTRL_2__LAST_SC0_INDEX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001fc000U) >> 14)
#define REDPWR_CTRL_2__LAST_SC0_INDEX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x001fc000U)
#define REDPWR_CTRL_2__LAST_SC0_INDEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x001fc000U)
#define REDPWR_CTRL_2__LAST_SC0_INDEX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x001fc000U)))
#define REDPWR_CTRL_2__TYPE                                           u_int32_t
#define REDPWR_CTRL_2__READ                                         0x001fffffU
#define REDPWR_CTRL_2__WRITE                                        0x001fffffU

#endif /* __REDPWR_CTRL_2_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_redpwr_ctrl_2 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_REDPWR_CTRL_2__NUM                1

/* macros for BlueprintGlobalNameSpace::rssi_b0 */
#ifndef __RSSI_B0_MACRO__
#define __RSSI_B0_MACRO__

/* macros for field rssi_0 */
#define RSSI_B0__RSSI_0__SHIFT                                                0
#define RSSI_B0__RSSI_0__WIDTH                                                8
#define RSSI_B0__RSSI_0__MASK                                       0x000000ffU
#define RSSI_B0__RSSI_0__READ(src)               (u_int32_t)(src) & 0x000000ffU

/* macros for field rssi_ext_0 */
#define RSSI_B0__RSSI_EXT_0__SHIFT                                            8
#define RSSI_B0__RSSI_EXT_0__WIDTH                                            8
#define RSSI_B0__RSSI_EXT_0__MASK                                   0x0000ff00U
#define RSSI_B0__RSSI_EXT_0__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define RSSI_B0__TYPE                                                 u_int32_t
#define RSSI_B0__READ                                               0x0000ffffU

#endif /* __RSSI_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_rssi_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RSSI_B0__NUM                      1

/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b0 */
#ifndef __SPUR_EST_CCK_REPORT_B0_MACRO__
#define __SPUR_EST_CCK_REPORT_B0_MACRO__

/* macros for field spur_est_sd_i_0_cck */
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__SHIFT                    0
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__WIDTH                    8
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__MASK           0x000000ffU
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU

/* macros for field spur_est_sd_q_0_cck */
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__SHIFT                    8
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__WIDTH                    8
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__MASK           0x0000ff00U
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field spur_est_i_0_cck */
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__SHIFT                      16
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__WIDTH                       8
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__MASK              0x00ff0000U
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field spur_est_q_0_cck */
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__SHIFT                      24
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__WIDTH                       8
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__MASK              0xff000000U
#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define SPUR_EST_CCK_REPORT_B0__TYPE                                  u_int32_t
#define SPUR_EST_CCK_REPORT_B0__READ                                0xffffffffU

#endif /* __SPUR_EST_CCK_REPORT_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_spur_est_cck_report_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_SPUR_EST_CCK_REPORT_B0__NUM       1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b0 */
#ifndef __AGC_DIG_DC_STATUS_I_B0_MACRO__
#define __AGC_DIG_DC_STATUS_I_B0_MACRO__

/* macros for field dig_dc_C1_res_i_0 */
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__SHIFT                      0
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__MASK             0x000001ffU
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU

/* macros for field dig_dc_C2_res_i_0 */
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__SHIFT                      9
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__MASK             0x0003fe00U
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fe00U) >> 9)

/* macros for field dig_dc_C3_res_i_0 */
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__SHIFT                     18
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__MASK             0x07fc0000U
#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fc0000U) >> 18)
#define AGC_DIG_DC_STATUS_I_B0__TYPE                                  u_int32_t
#define AGC_DIG_DC_STATUS_I_B0__READ                                0x07ffffffU

#endif /* __AGC_DIG_DC_STATUS_I_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_status_i_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B0__NUM       1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b0 */
#ifndef __AGC_DIG_DC_STATUS_Q_B0_MACRO__
#define __AGC_DIG_DC_STATUS_Q_B0_MACRO__

/* macros for field dig_dc_C1_res_q_0 */
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__SHIFT                      0
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__MASK             0x000001ffU
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU

/* macros for field dig_dc_C2_res_q_0 */
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__SHIFT                      9
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__MASK             0x0003fe00U
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fe00U) >> 9)

/* macros for field dig_dc_C3_res_q_0 */
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__SHIFT                     18
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__MASK             0x07fc0000U
#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fc0000U) >> 18)
#define AGC_DIG_DC_STATUS_Q_B0__TYPE                                  u_int32_t
#define AGC_DIG_DC_STATUS_Q_B0__READ                                0x07ffffffU

#endif /* __AGC_DIG_DC_STATUS_Q_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_status_q_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B0__NUM       1

/* macros for BlueprintGlobalNameSpace::dc_cal_status_b0 */
#ifndef __DC_CAL_STATUS_B0_MACRO__
#define __DC_CAL_STATUS_B0_MACRO__

/* macros for field offsetC1I_0 */
#define DC_CAL_STATUS_B0__OFFSETC1I_0__SHIFT                                  0
#define DC_CAL_STATUS_B0__OFFSETC1I_0__WIDTH                                  5
#define DC_CAL_STATUS_B0__OFFSETC1I_0__MASK                         0x0000001fU
#define DC_CAL_STATUS_B0__OFFSETC1I_0__READ(src) (u_int32_t)(src) & 0x0000001fU

/* macros for field offsetC1Q_0 */
#define DC_CAL_STATUS_B0__OFFSETC1Q_0__SHIFT                                  5
#define DC_CAL_STATUS_B0__OFFSETC1Q_0__WIDTH                                  5
#define DC_CAL_STATUS_B0__OFFSETC1Q_0__MASK                         0x000003e0U
#define DC_CAL_STATUS_B0__OFFSETC1Q_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)

/* macros for field offsetC2I_0 */
#define DC_CAL_STATUS_B0__OFFSETC2I_0__SHIFT                                 10
#define DC_CAL_STATUS_B0__OFFSETC2I_0__WIDTH                                  5
#define DC_CAL_STATUS_B0__OFFSETC2I_0__MASK                         0x00007c00U
#define DC_CAL_STATUS_B0__OFFSETC2I_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)

/* macros for field offsetC2Q_0 */
#define DC_CAL_STATUS_B0__OFFSETC2Q_0__SHIFT                                 15
#define DC_CAL_STATUS_B0__OFFSETC2Q_0__WIDTH                                  5
#define DC_CAL_STATUS_B0__OFFSETC2Q_0__MASK                         0x000f8000U
#define DC_CAL_STATUS_B0__OFFSETC2Q_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)

/* macros for field offsetC3I_0 */
#define DC_CAL_STATUS_B0__OFFSETC3I_0__SHIFT                                 20
#define DC_CAL_STATUS_B0__OFFSETC3I_0__WIDTH                                  5
#define DC_CAL_STATUS_B0__OFFSETC3I_0__MASK                         0x01f00000U
#define DC_CAL_STATUS_B0__OFFSETC3I_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)

/* macros for field offsetC3Q_0 */
#define DC_CAL_STATUS_B0__OFFSETC3Q_0__SHIFT                                 25
#define DC_CAL_STATUS_B0__OFFSETC3Q_0__WIDTH                                  5
#define DC_CAL_STATUS_B0__OFFSETC3Q_0__MASK                         0x3e000000U
#define DC_CAL_STATUS_B0__OFFSETC3Q_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define DC_CAL_STATUS_B0__TYPE                                        u_int32_t
#define DC_CAL_STATUS_B0__READ                                      0x3fffffffU

#endif /* __DC_CAL_STATUS_B0_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_dc_cal_status_b0 */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_DC_CAL_STATUS_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::bbb_sig_detect */
#ifndef __BBB_SIG_DETECT_MACRO__
#define __BBB_SIG_DETECT_MACRO__

/* macros for field weak_sig_thr_cck */
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__SHIFT                               0
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WIDTH                               6
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MASK                      0x0000003fU
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field ant_switch_time */
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__SHIFT                                6
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WIDTH                                7
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MASK                       0x00001fc0U
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001fc0U) >> 6)
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00001fc0U)
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00001fc0U)
#define BBB_SIG_DETECT__ANT_SWITCH_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00001fc0U)))

/* macros for field enable_ant_fast_div */
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT                           13
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WIDTH                            1
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK                   0x00002000U
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field lb_alpha_128_cck */
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SHIFT                              14
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WIDTH                               1
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MASK                      0x00004000U
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field lb_rx_enable_cck */
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SHIFT                              15
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WIDTH                               1
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MASK                      0x00008000U
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field cyc32_coarse_dc_est_cck */
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SHIFT                       16
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WIDTH                        1
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MASK               0x00010000U
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field cyc64_coarse_dc_est_cck */
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SHIFT                       17
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WIDTH                        1
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MASK               0x00020000U
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field enable_coarse_dc_cck */
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SHIFT                          18
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WIDTH                           1
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MASK                  0x00040000U
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field cyc256_fine_dc_est_cck */
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SHIFT                        19
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WIDTH                         1
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MASK                0x00080000U
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field enable_fine_dc_cck */
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SHIFT                            20
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WIDTH                             1
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MASK                    0x00100000U
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field delay_start_sync_cck */
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SHIFT                          21
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WIDTH                           1
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MASK                  0x00200000U
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field use_dc_est_during_srch */
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SHIFT                        22
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WIDTH                         1
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MASK                0x00400000U
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field bbb_mrc_off_no_swap */
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SHIFT                           23
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WIDTH                            1
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MASK                   0x00800000U
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field swap_default_chain_cck */
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SHIFT                        24
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WIDTH                         1
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MASK                0x01000000U
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field enable_barker_two_phase */
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SHIFT                       31
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WIDTH                        1
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MASK               0x80000000U
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define BBB_SIG_DETECT__TYPE                                          u_int32_t
#define BBB_SIG_DETECT__READ                                        0x81ffffffU
#define BBB_SIG_DETECT__WRITE                                       0x81ffffffU

#endif /* __BBB_SIG_DETECT_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bbb_sig_detect */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BBB_SIG_DETECT__NUM               1

/* macros for BlueprintGlobalNameSpace::bbb_dagc_ctrl */
#ifndef __BBB_DAGC_CTRL_MACRO__
#define __BBB_DAGC_CTRL_MACRO__

/* macros for field enable_dagc_cck */
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SHIFT                                 0
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WIDTH                                 1
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MASK                        0x00000001U
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field dagc_target_pwr_cck */
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__SHIFT                             1
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WIDTH                             8
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MASK                    0x000001feU
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000001feU)
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001feU) | (((u_int32_t)(src) <<\
                    1) & 0x000001feU)
#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000001feU)))

/* macros for field enable_barker_rssi_thr */
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SHIFT                          9
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WIDTH                          1
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MASK                 0x00000200U
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field barker_rssi_thr */
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__SHIFT                                10
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WIDTH                                 7
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MASK                        0x0001fc00U
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fc00U) >> 10)
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0001fc00U)
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0001fc00U)
#define BBB_DAGC_CTRL__BARKER_RSSI_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0001fc00U)))

/* macros for field enable_firstep_sel */
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SHIFT                             17
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WIDTH                              1
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MASK                     0x00020000U
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field firstep_2 */
#define BBB_DAGC_CTRL__FIRSTEP_2__SHIFT                                      18
#define BBB_DAGC_CTRL__FIRSTEP_2__WIDTH                                       6
#define BBB_DAGC_CTRL__FIRSTEP_2__MASK                              0x00fc0000U
#define BBB_DAGC_CTRL__FIRSTEP_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define BBB_DAGC_CTRL__FIRSTEP_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00fc0000U)
#define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define BBB_DAGC_CTRL__FIRSTEP_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field firstep_count_lgmax */
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__SHIFT                            24
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WIDTH                             4
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MASK                    0x0f000000U
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f000000U) >> 24)
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x0f000000U)
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x0f000000U)
#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field force_rx_chain_cck_0 */
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__SHIFT                           28
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WIDTH                            2
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MASK                   0x30000000U
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x30000000U) >> 28)
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x30000000U)
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((u_int32_t)(src) <<\
                    28) & 0x30000000U)
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field force_rx_chain_cck_1 */
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__SHIFT                           30
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WIDTH                            2
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MASK                   0xc0000000U
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define BBB_DAGC_CTRL__TYPE                                           u_int32_t
#define BBB_DAGC_CTRL__READ                                         0xffffffffU
#define BBB_DAGC_CTRL__WRITE                                        0xffffffffU

#endif /* __BBB_DAGC_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_bbb_dagc_ctrl */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BBB_DAGC_CTRL__NUM                1

/* macros for BlueprintGlobalNameSpace::iqcorr_ctrl_cck */
#ifndef __IQCORR_CTRL_CCK_MACRO__
#define __IQCORR_CTRL_CCK_MACRO__

/* macros for field iqcorr_q_q_coff_cck */
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__SHIFT                           0
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WIDTH                           5
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MASK                  0x0000001fU
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field iqcorr_q_i_coff_cck */
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__SHIFT                           5
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WIDTH                           6
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MASK                  0x000007e0U
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000007e0U) >> 5)
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000007e0U)
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000007e0U)
#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000007e0U)))

/* macros for field enable_iqcorr_cck */
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SHIFT                            11
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WIDTH                             1
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MASK                    0x00000800U
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field rxcal_meas_time_sel */
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__SHIFT                          12
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WIDTH                           2
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MASK                  0x00003000U
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003000U) >> 12)
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00003000U)
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((u_int32_t)(src) <<\
                    12) & 0x00003000U)
#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field clcal_meas_time_sel */
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__SHIFT                          14
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WIDTH                           2
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MASK                  0x0000c000U
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000c000U) >> 14)
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0000c000U)
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0000c000U)
#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field cf_clc_init_rfgain */
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__SHIFT                           16
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WIDTH                            5
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MASK                   0x001f0000U
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x001f0000U)
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x001f0000U)
#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x001f0000U)))
#define IQCORR_CTRL_CCK__TYPE                                         u_int32_t
#define IQCORR_CTRL_CCK__READ                                       0x001fffffU
#define IQCORR_CTRL_CCK__WRITE                                      0x001fffffU

#endif /* __IQCORR_CTRL_CCK_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_iqcorr_ctrl_cck */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_IQCORR_CTRL_CCK__NUM              1

/* macros for BlueprintGlobalNameSpace::cck_spur_mit */
#ifndef __CCK_SPUR_MIT_MACRO__
#define __CCK_SPUR_MIT_MACRO__

/* macros for field use_cck_spur_mit */
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SHIFT                                 0
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WIDTH                                 1
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MASK                        0x00000001U
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field spur_rssi_thr */
#define CCK_SPUR_MIT__SPUR_RSSI_THR__SHIFT                                    1
#define CCK_SPUR_MIT__SPUR_RSSI_THR__WIDTH                                    8
#define CCK_SPUR_MIT__SPUR_RSSI_THR__MASK                           0x000001feU
#define CCK_SPUR_MIT__SPUR_RSSI_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)
#define CCK_SPUR_MIT__SPUR_RSSI_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000001feU)
#define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001feU) | (((u_int32_t)(src) <<\
                    1) & 0x000001feU)
#define CCK_SPUR_MIT__SPUR_RSSI_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000001feU)))

/* macros for field cck_spur_freq */
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__SHIFT                                    9
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WIDTH                                   20
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MASK                           0x1ffffe00U
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1ffffe00U) >> 9)
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x1ffffe00U)
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1ffffe00U) | (((u_int32_t)(src) <<\
                    9) & 0x1ffffe00U)
#define CCK_SPUR_MIT__CCK_SPUR_FREQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x1ffffe00U)))

/* macros for field spur_filter_type */
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__SHIFT                                29
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WIDTH                                 2
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MASK                        0x60000000U
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x60000000U) >> 29)
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x60000000U)
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x60000000U) | (((u_int32_t)(src) <<\
                    29) & 0x60000000U)
#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x60000000U)))
#define CCK_SPUR_MIT__TYPE                                            u_int32_t
#define CCK_SPUR_MIT__READ                                          0x7fffffffU
#define CCK_SPUR_MIT__WRITE                                         0x7fffffffU

#endif /* __CCK_SPUR_MIT_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_cck_spur_mit */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCK_SPUR_MIT__NUM                 1

/* macros for BlueprintGlobalNameSpace::mrc_cck_ctrl */
#ifndef __MRC_CCK_CTRL_MACRO__
#define __MRC_CCK_CTRL_MACRO__

/* macros for field bbb_mrc_en */
#define MRC_CCK_CTRL__BBB_MRC_EN__SHIFT                                       0
#define MRC_CCK_CTRL__BBB_MRC_EN__WIDTH                                       1
#define MRC_CCK_CTRL__BBB_MRC_EN__MASK                              0x00000001U
#define MRC_CCK_CTRL__BBB_MRC_EN__READ(src)      (u_int32_t)(src) & 0x00000001U
#define MRC_CCK_CTRL__BBB_MRC_EN__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
#define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MRC_CCK_CTRL__BBB_MRC_EN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MRC_CCK_CTRL__BBB_MRC_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MRC_CCK_CTRL__BBB_MRC_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field agcdp_cck_mrc_mux_reg */
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SHIFT                            1
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WIDTH                            1
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MASK                   0x00000002U
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field agcdp_cck_pd_accu_thr_hi */
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__SHIFT                         2
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WIDTH                         3
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MASK                0x0000001cU
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))

/* macros for field agcdp_cck_pd_accu_thr_low */
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__SHIFT                        5
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WIDTH                        3
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MASK               0x000000e0U
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000e0U) >> 5)
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000000e0U)
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))

/* macros for field agcdp_cck_barker_rssi_thr */
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__SHIFT                        8
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WIDTH                        4
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MASK               0x00000f00U
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field agcdp_cck_mrc_bk_thr_hi */
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__SHIFT                         12
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WIDTH                          5
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MASK                 0x0001f000U
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field agcdp_cck_mrc_bk_thr_low */
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__SHIFT                        17
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WIDTH                         5
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MASK                0x003e0000U
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003e0000U) >> 17)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x003e0000U)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field agcdp_cck_min_value */
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__SHIFT                             22
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WIDTH                              6
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MASK                     0x0fc00000U
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fc00000U) >> 22)
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x0fc00000U)
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x0fc00000U)
#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x0fc00000U)))
#define MRC_CCK_CTRL__TYPE                                            u_int32_t
#define MRC_CCK_CTRL__READ                                          0x0fffffffU
#define MRC_CCK_CTRL__WRITE                                         0x0fffffffU

#endif /* __MRC_CCK_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_mrc_cck_ctrl */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_MRC_CCK_CTRL__NUM                 1

/* macros for BlueprintGlobalNameSpace::cck_blocker_det */
#ifndef __CCK_BLOCKER_DET_MACRO__
#define __CCK_BLOCKER_DET_MACRO__

/* macros for field cck_freq_shift_blocker_detection */
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SHIFT              0
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WIDTH              1
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MASK     0x00000001U
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cck_blocker_det_restart_weak_sig */
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SHIFT              1
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WIDTH              1
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MASK     0x00000002U
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field cck_blocker_det_bksum_num */
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__SHIFT                     2
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WIDTH                     4
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MASK            0x0000003cU
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003cU) >> 2)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000003cU)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000003cU)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000003cU)))

/* macros for field bk_valid_delay */
#define CCK_BLOCKER_DET__BK_VALID_DELAY__SHIFT                                6
#define CCK_BLOCKER_DET__BK_VALID_DELAY__WIDTH                                3
#define CCK_BLOCKER_DET__BK_VALID_DELAY__MASK                       0x000001c0U
#define CCK_BLOCKER_DET__BK_VALID_DELAY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001c0U) >> 6)
#define CCK_BLOCKER_DET__BK_VALID_DELAY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000001c0U)
#define CCK_BLOCKER_DET__BK_VALID_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000001c0U)
#define CCK_BLOCKER_DET__BK_VALID_DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000001c0U)))

/* macros for field cck_blocker_det_thr */
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__SHIFT                           9
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WIDTH                           5
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MASK                  0x00003e00U
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003e00U) >> 9)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00003e00U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00003e00U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00003e00U)))

/* macros for field cck_blocker_det_delay_thr */
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__SHIFT                    14
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WIDTH                     6
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MASK            0x000fc000U
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fc000U) >> 14)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x000fc000U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000fc000U) | (((u_int32_t)(src) <<\
                    14) & 0x000fc000U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x000fc000U)))

/* macros for field cck_blocker_monitor_time */
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__SHIFT                     20
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WIDTH                      6
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MASK             0x03f00000U
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03f00000U) >> 20)
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x03f00000U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x03f00000U)
#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x03f00000U)))

/* macros for field skip_ramp_enable */
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SHIFT                             26
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WIDTH                              1
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MASK                     0x04000000U
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field cck_det_ramp_thr */
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__SHIFT                             27
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WIDTH                              5
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MASK                     0xf8000000U
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf8000000U) >> 27)
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0xf8000000U)
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define CCK_BLOCKER_DET__TYPE                                         u_int32_t
#define CCK_BLOCKER_DET__READ                                       0xffffffffU
#define CCK_BLOCKER_DET__WRITE                                      0xffffffffU

#endif /* __CCK_BLOCKER_DET_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_cck_blocker_det */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCK_BLOCKER_DET__NUM              1

/* macros for BlueprintGlobalNameSpace::rx_ocgain */
#ifndef __RX_OCGAIN_MACRO__
#define __RX_OCGAIN_MACRO__

/* macros for field gain_entry */
#define RX_OCGAIN__GAIN_ENTRY__SHIFT                                          0
#define RX_OCGAIN__GAIN_ENTRY__WIDTH                                         32
#define RX_OCGAIN__GAIN_ENTRY__MASK                                 0xffffffffU
#define RX_OCGAIN__GAIN_ENTRY__READ(src)         (u_int32_t)(src) & 0xffffffffU
#define RX_OCGAIN__GAIN_ENTRY__WRITE(src)      ((u_int32_t)(src) & 0xffffffffU)
#define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define RX_OCGAIN__GAIN_ENTRY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define RX_OCGAIN__TYPE                                               u_int32_t
#define RX_OCGAIN__READ                                             0xffffffffU
#define RX_OCGAIN__WRITE                                            0xffffffffU

#endif /* __RX_OCGAIN_MACRO__ */


/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_ocgain */
#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_OCGAIN__NUM                  128

/* macros for BlueprintGlobalNameSpace::D2_chip_id */
#ifndef __D2_CHIP_ID_MACRO__
#define __D2_CHIP_ID_MACRO__

/* macros for field old_id */
#define D2_CHIP_ID__OLD_ID__SHIFT                                             0
#define D2_CHIP_ID__OLD_ID__WIDTH                                             8
#define D2_CHIP_ID__OLD_ID__MASK                                    0x000000ffU
#define D2_CHIP_ID__OLD_ID__READ(src)            (u_int32_t)(src) & 0x000000ffU

/* macros for field id */
#define D2_CHIP_ID__ID__SHIFT                                                 8
#define D2_CHIP_ID__ID__WIDTH                                                24
#define D2_CHIP_ID__ID__MASK                                        0xffffff00U
#define D2_CHIP_ID__ID__READ(src)       (((u_int32_t)(src) & 0xffffff00U) >> 8)
#define D2_CHIP_ID__TYPE                                              u_int32_t
#define D2_CHIP_ID__READ                                            0xffffffffU

#endif /* __D2_CHIP_ID_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_D2_chip_id */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_D2_CHIP_ID__NUM                    1

/* macros for BlueprintGlobalNameSpace::gen_controls */
#ifndef __GEN_CONTROLS_MACRO__
#define __GEN_CONTROLS_MACRO__

/* macros for field turbo */
#define GEN_CONTROLS__TURBO__SHIFT                                            0
#define GEN_CONTROLS__TURBO__WIDTH                                            1
#define GEN_CONTROLS__TURBO__MASK                                   0x00000001U
#define GEN_CONTROLS__TURBO__READ(src)           (u_int32_t)(src) & 0x00000001U
#define GEN_CONTROLS__TURBO__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
#define GEN_CONTROLS__TURBO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define GEN_CONTROLS__TURBO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
#define GEN_CONTROLS__TURBO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define GEN_CONTROLS__TURBO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cf_short20 */
#define GEN_CONTROLS__CF_SHORT20__SHIFT                                       1
#define GEN_CONTROLS__CF_SHORT20__WIDTH                                       1
#define GEN_CONTROLS__CF_SHORT20__MASK                              0x00000002U
#define GEN_CONTROLS__CF_SHORT20__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define GEN_CONTROLS__CF_SHORT20__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define GEN_CONTROLS__CF_SHORT20__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define GEN_CONTROLS__CF_SHORT20__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define GEN_CONTROLS__CF_SHORT20__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field dyn_20_40 */
#define GEN_CONTROLS__DYN_20_40__SHIFT                                        2
#define GEN_CONTROLS__DYN_20_40__WIDTH                                        1
#define GEN_CONTROLS__DYN_20_40__MASK                               0x00000004U
#define GEN_CONTROLS__DYN_20_40__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define GEN_CONTROLS__DYN_20_40__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define GEN_CONTROLS__DYN_20_40__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define GEN_CONTROLS__DYN_20_40__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define GEN_CONTROLS__DYN_20_40__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field dyn_20_40_pri_only */
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SHIFT                               3
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WIDTH                               1
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MASK                      0x00000008U
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field dyn_20_40_pri_chn */
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SHIFT                                4
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WIDTH                                1
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MASK                       0x00000010U
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define GEN_CONTROLS__DYN_20_40_PRI_CHN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field dyn_20_40_ext_chn */
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SHIFT                                5
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WIDTH                                1
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MASK                       0x00000020U
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define GEN_CONTROLS__DYN_20_40_EXT_CHN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field ht_enable */
#define GEN_CONTROLS__HT_ENABLE__SHIFT                                        6
#define GEN_CONTROLS__HT_ENABLE__WIDTH                                        1
#define GEN_CONTROLS__HT_ENABLE__MASK                               0x00000040U
#define GEN_CONTROLS__HT_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define GEN_CONTROLS__HT_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define GEN_CONTROLS__HT_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define GEN_CONTROLS__HT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define GEN_CONTROLS__HT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field allow_short_gi */
#define GEN_CONTROLS__ALLOW_SHORT_GI__SHIFT                                   7
#define GEN_CONTROLS__ALLOW_SHORT_GI__WIDTH                                   1
#define GEN_CONTROLS__ALLOW_SHORT_GI__MASK                          0x00000080U
#define GEN_CONTROLS__ALLOW_SHORT_GI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define GEN_CONTROLS__ALLOW_SHORT_GI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define GEN_CONTROLS__ALLOW_SHORT_GI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define GEN_CONTROLS__ALLOW_SHORT_GI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define GEN_CONTROLS__ALLOW_SHORT_GI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field cf_2_chains_use_walsh */
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SHIFT                            8
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WIDTH                            1
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MASK                   0x00000100U
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field cf_3_chains_use_walsh */
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SHIFT                            9
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WIDTH                            1
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MASK                   0x00000200U
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field gf_enable */
#define GEN_CONTROLS__GF_ENABLE__SHIFT                                       10
#define GEN_CONTROLS__GF_ENABLE__WIDTH                                        1
#define GEN_CONTROLS__GF_ENABLE__MASK                               0x00000400U
#define GEN_CONTROLS__GF_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define GEN_CONTROLS__GF_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define GEN_CONTROLS__GF_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define GEN_CONTROLS__GF_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define GEN_CONTROLS__GF_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field enable_dac_async_fifo */
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SHIFT                           11
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WIDTH                            1
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MASK                   0x00000800U
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field bond_opt_chain_sel */
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SHIFT                              14
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WIDTH                               1
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MASK                      0x00004000U
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field static20_mode_ht40_packet_handling */
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SHIFT              15
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WIDTH               1
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MASK      0x00008000U
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field static20_mode_ht40_packet_error_rpt */
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SHIFT             16
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WIDTH              1
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MASK     0x00010000U
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field enable_csd_phase_dithering */
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SHIFT                      17
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WIDTH                       1
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MASK              0x00020000U
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field unsupp_ht_rate_threshold */
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__SHIFT                        18
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WIDTH                         7
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MASK                0x01fc0000U
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fc0000U) >> 18)
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x01fc0000U)
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x01fc0000U)
#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x01fc0000U)))

/* macros for field en_err_tx_chain_mask_zero */
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SHIFT                       25
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WIDTH                        1
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MASK               0x02000000U
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)
#define GEN_CONTROLS__TYPE                                            u_int32_t
#define GEN_CONTROLS__READ                                          0x03ffcfffU
#define GEN_CONTROLS__WRITE                                         0x03ffcfffU

#endif /* __GEN_CONTROLS_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_gen_controls */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_GEN_CONTROLS__NUM                  1

/* macros for BlueprintGlobalNameSpace::modes_select */
#ifndef __MODES_SELECT_MACRO__
#define __MODES_SELECT_MACRO__

/* macros for field cck_mode */
#define MODES_SELECT__CCK_MODE__SHIFT                                         0
#define MODES_SELECT__CCK_MODE__WIDTH                                         1
#define MODES_SELECT__CCK_MODE__MASK                                0x00000001U
#define MODES_SELECT__CCK_MODE__READ(src)        (u_int32_t)(src) & 0x00000001U
#define MODES_SELECT__CCK_MODE__WRITE(src)     ((u_int32_t)(src) & 0x00000001U)
#define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MODES_SELECT__CCK_MODE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MODES_SELECT__CCK_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MODES_SELECT__CCK_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field dyn_ofdm_cck_mode */
#define MODES_SELECT__DYN_OFDM_CCK_MODE__SHIFT                                2
#define MODES_SELECT__DYN_OFDM_CCK_MODE__WIDTH                                1
#define MODES_SELECT__DYN_OFDM_CCK_MODE__MASK                       0x00000004U
#define MODES_SELECT__DYN_OFDM_CCK_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MODES_SELECT__DYN_OFDM_CCK_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MODES_SELECT__DYN_OFDM_CCK_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MODES_SELECT__DYN_OFDM_CCK_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MODES_SELECT__DYN_OFDM_CCK_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field half_rate_mode */
#define MODES_SELECT__HALF_RATE_MODE__SHIFT                                   5
#define MODES_SELECT__HALF_RATE_MODE__WIDTH                                   1
#define MODES_SELECT__HALF_RATE_MODE__MASK                          0x00000020U
#define MODES_SELECT__HALF_RATE_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define MODES_SELECT__HALF_RATE_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define MODES_SELECT__HALF_RATE_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define MODES_SELECT__HALF_RATE_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define MODES_SELECT__HALF_RATE_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field quarter_rate_mode */
#define MODES_SELECT__QUARTER_RATE_MODE__SHIFT                                6
#define MODES_SELECT__QUARTER_RATE_MODE__WIDTH                                1
#define MODES_SELECT__QUARTER_RATE_MODE__MASK                       0x00000040U
#define MODES_SELECT__QUARTER_RATE_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define MODES_SELECT__QUARTER_RATE_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define MODES_SELECT__QUARTER_RATE_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define MODES_SELECT__QUARTER_RATE_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define MODES_SELECT__QUARTER_RATE_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field mac_clk_mode */
#define MODES_SELECT__MAC_CLK_MODE__SHIFT                                     7
#define MODES_SELECT__MAC_CLK_MODE__WIDTH                                     1
#define MODES_SELECT__MAC_CLK_MODE__MASK                            0x00000080U
#define MODES_SELECT__MAC_CLK_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define MODES_SELECT__MAC_CLK_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define MODES_SELECT__MAC_CLK_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define MODES_SELECT__MAC_CLK_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define MODES_SELECT__MAC_CLK_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field disable_dyn_cck_det */
#define MODES_SELECT__DISABLE_DYN_CCK_DET__SHIFT                              8
#define MODES_SELECT__DISABLE_DYN_CCK_DET__WIDTH                              1
#define MODES_SELECT__DISABLE_DYN_CCK_DET__MASK                     0x00000100U
#define MODES_SELECT__DISABLE_DYN_CCK_DET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define MODES_SELECT__DISABLE_DYN_CCK_DET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define MODES_SELECT__DISABLE_DYN_CCK_DET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define MODES_SELECT__DISABLE_DYN_CCK_DET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define MODES_SELECT__DISABLE_DYN_CCK_DET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field svd_half_rate_mode */
#define MODES_SELECT__SVD_HALF_RATE_MODE__SHIFT                               9
#define MODES_SELECT__SVD_HALF_RATE_MODE__WIDTH                               1
#define MODES_SELECT__SVD_HALF_RATE_MODE__MASK                      0x00000200U
#define MODES_SELECT__SVD_HALF_RATE_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define MODES_SELECT__SVD_HALF_RATE_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define MODES_SELECT__SVD_HALF_RATE_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define MODES_SELECT__SVD_HALF_RATE_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define MODES_SELECT__SVD_HALF_RATE_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)
#define MODES_SELECT__TYPE                                            u_int32_t
#define MODES_SELECT__READ                                          0x000003e5U
#define MODES_SELECT__WRITE                                         0x000003e5U

#endif /* __MODES_SELECT_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_modes_select */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MODES_SELECT__NUM                  1

/* macros for BlueprintGlobalNameSpace::active */
#ifndef __ACTIVE_MACRO__
#define __ACTIVE_MACRO__

/* macros for field cf_active */
#define ACTIVE__CF_ACTIVE__SHIFT                                              0
#define ACTIVE__CF_ACTIVE__WIDTH                                              1
#define ACTIVE__CF_ACTIVE__MASK                                     0x00000001U
#define ACTIVE__CF_ACTIVE__READ(src)             (u_int32_t)(src) & 0x00000001U
#define ACTIVE__CF_ACTIVE__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
#define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define ACTIVE__CF_ACTIVE__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
#define ACTIVE__CF_ACTIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define ACTIVE__CF_ACTIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define ACTIVE__TYPE                                                  u_int32_t
#define ACTIVE__READ                                                0x00000001U
#define ACTIVE__WRITE                                               0x00000001U

#endif /* __ACTIVE_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_active */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ACTIVE__NUM                        1

/* macros for BlueprintGlobalNameSpace::vit_spur_mask_A */
#ifndef __VIT_SPUR_MASK_A_MACRO__
#define __VIT_SPUR_MASK_A_MACRO__

/* macros for field cf_punc_mask_A */
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__SHIFT                                0
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WIDTH                               10
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MASK                       0x000003ffU
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field cf_punc_mask_idx_A */
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__SHIFT                           10
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WIDTH                            7
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MASK                   0x0001fc00U
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fc00U) >> 10)
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0001fc00U)
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0001fc00U)
#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0001fc00U)))
#define VIT_SPUR_MASK_A__TYPE                                         u_int32_t
#define VIT_SPUR_MASK_A__READ                                       0x0001ffffU
#define VIT_SPUR_MASK_A__WRITE                                      0x0001ffffU

#endif /* __VIT_SPUR_MASK_A_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_vit_spur_mask_A */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_A__NUM               1

/* macros for BlueprintGlobalNameSpace::vit_spur_mask_B */
#ifndef __VIT_SPUR_MASK_B_MACRO__
#define __VIT_SPUR_MASK_B_MACRO__

/* macros for field cf_punc_mask_B */
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__SHIFT                                0
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WIDTH                               10
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MASK                       0x000003ffU
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field cf_punc_mask_idx_B */
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__SHIFT                           10
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WIDTH                            7
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MASK                   0x0001fc00U
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fc00U) >> 10)
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0001fc00U)
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0001fc00U)
#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0001fc00U)))
#define VIT_SPUR_MASK_B__TYPE                                         u_int32_t
#define VIT_SPUR_MASK_B__READ                                       0x0001ffffU
#define VIT_SPUR_MASK_B__WRITE                                      0x0001ffffU

#endif /* __VIT_SPUR_MASK_B_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_vit_spur_mask_B */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_B__NUM               1

/* macros for BlueprintGlobalNameSpace::spectral_scan */
#ifndef __SPECTRAL_SCAN_MACRO__
#define __SPECTRAL_SCAN_MACRO__

/* macros for field spectral_scan_ena */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SHIFT                               0
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WIDTH                               1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MASK                      0x00000001U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field spectral_scan_active */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SHIFT                            1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WIDTH                            1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MASK                   0x00000002U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field disable_radar_tctl_rst */
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SHIFT                          2
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WIDTH                          1
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MASK                 0x00000004U
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field disable_pulse_coarse_low */
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SHIFT                        3
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WIDTH                        1
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MASK               0x00000008U
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field spectral_scan_fft_period */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__SHIFT                        4
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WIDTH                        4
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MASK               0x000000f0U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field spectral_scan_period */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__SHIFT                            8
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WIDTH                            8
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MASK                   0x0000ff00U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field spectral_scan_count */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__SHIFT                            16
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WIDTH                            12
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MASK                    0x0fff0000U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fff0000U) >> 16)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x0fff0000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x0fff0000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x0fff0000U)))

/* macros for field spectral_scan_short_rpt */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SHIFT                        28
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WIDTH                         1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MASK                0x10000000U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field spectral_scan_priority */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SHIFT                         29
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WIDTH                          1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MASK                 0x20000000U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field spectral_scan_use_err5 */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SHIFT                         30
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WIDTH                          1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MASK                 0x40000000U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field spectral_scan_compressed_rpt */
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SHIFT                   31
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WIDTH                    1
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MASK           0x80000000U
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SPECTRAL_SCAN__TYPE                                           u_int32_t
#define SPECTRAL_SCAN__READ                                         0xffffffffU
#define SPECTRAL_SCAN__WRITE                                        0xffffffffU

#endif /* __SPECTRAL_SCAN_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_spectral_scan */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SPECTRAL_SCAN__NUM                 1

/* macros for BlueprintGlobalNameSpace::radar_bw_filter */
#ifndef __RADAR_BW_FILTER_MACRO__
#define __RADAR_BW_FILTER_MACRO__

/* macros for field radar_avg_bw_check */
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SHIFT                            0
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WIDTH                            1
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MASK                   0x00000001U
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field radar_dc_src_sel */
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SHIFT                              1
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WIDTH                              1
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MASK                     0x00000002U
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field radar_firpwr_sel */
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__SHIFT                              2
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WIDTH                              2
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MASK                     0x0000000cU
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field radar_pulse_width_sel */
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__SHIFT                         4
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WIDTH                         2
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MASK                0x00000030U
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field radar_dc_firpwr_thresh */
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__SHIFT                        8
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WIDTH                        7
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MASK               0x00007f00U
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007f00U) >> 8)
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00007f00U)
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00007f00U)
#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00007f00U)))

/* macros for field radar_dc_pwr_bias */
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__SHIFT                            15
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WIDTH                             6
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MASK                    0x001f8000U
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f8000U) >> 15)
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x001f8000U)
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x001f8000U)
#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x001f8000U)))

/* macros for field radar_bin_max_bw */
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__SHIFT                             21
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WIDTH                              6
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MASK                     0x07e00000U
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07e00000U) >> 21)
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x07e00000U)
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x07e00000U)
#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x07e00000U)))
#define RADAR_BW_FILTER__TYPE                                         u_int32_t
#define RADAR_BW_FILTER__READ                                       0x07ffff3fU
#define RADAR_BW_FILTER__WRITE                                      0x07ffff3fU

#endif /* __RADAR_BW_FILTER_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_radar_bw_filter */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RADAR_BW_FILTER__NUM               1

/* macros for BlueprintGlobalNameSpace::search_start_delay */
#ifndef __SEARCH_START_DELAY_MACRO__
#define __SEARCH_START_DELAY_MACRO__

/* macros for field search_start_delay */
#define SEARCH_START_DELAY__SEARCH_START_DELAY__SHIFT                         0
#define SEARCH_START_DELAY__SEARCH_START_DELAY__WIDTH                        12
#define SEARCH_START_DELAY__SEARCH_START_DELAY__MASK                0x00000fffU
#define SEARCH_START_DELAY__SEARCH_START_DELAY__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU
#define SEARCH_START_DELAY__SEARCH_START_DELAY__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000fffU)
#define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define SEARCH_START_DELAY__SEARCH_START_DELAY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field enable_flt_svd */
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SHIFT                            12
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WIDTH                             1
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MASK                    0x00001000U
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define SEARCH_START_DELAY__ENABLE_FLT_SVD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field enable_send_chan */
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SHIFT                          13
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WIDTH                           1
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MASK                  0x00002000U
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field rx_sounding_enable */
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SHIFT                        14
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WIDTH                         1
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MASK                0x00004000U
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field rm_hcsd4svd */
#define SEARCH_START_DELAY__RM_HCSD4SVD__SHIFT                               15
#define SEARCH_START_DELAY__RM_HCSD4SVD__WIDTH                                1
#define SEARCH_START_DELAY__RM_HCSD4SVD__MASK                       0x00008000U
#define SEARCH_START_DELAY__RM_HCSD4SVD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define SEARCH_START_DELAY__RM_HCSD4SVD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define SEARCH_START_DELAY__RM_HCSD4SVD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define SEARCH_START_DELAY__RM_HCSD4SVD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define SEARCH_START_DELAY__RM_HCSD4SVD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)
#define SEARCH_START_DELAY__TYPE                                      u_int32_t
#define SEARCH_START_DELAY__READ                                    0x0000ffffU
#define SEARCH_START_DELAY__WRITE                                   0x0000ffffU

#endif /* __SEARCH_START_DELAY_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_search_start_delay */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SEARCH_START_DELAY__NUM            1

/* macros for BlueprintGlobalNameSpace::max_rx_length */
#ifndef __MAX_RX_LENGTH_MACRO__
#define __MAX_RX_LENGTH_MACRO__

/* macros for field max_rx_length */
#define MAX_RX_LENGTH__MAX_RX_LENGTH__SHIFT                                   0
#define MAX_RX_LENGTH__MAX_RX_LENGTH__WIDTH                                  12
#define MAX_RX_LENGTH__MAX_RX_LENGTH__MASK                          0x00000fffU
#define MAX_RX_LENGTH__MAX_RX_LENGTH__READ(src)  (u_int32_t)(src) & 0x00000fffU
#define MAX_RX_LENGTH__MAX_RX_LENGTH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000fffU)
#define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define MAX_RX_LENGTH__MAX_RX_LENGTH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field max_ht_length */
#define MAX_RX_LENGTH__MAX_HT_LENGTH__SHIFT                                  12
#define MAX_RX_LENGTH__MAX_HT_LENGTH__WIDTH                                  18
#define MAX_RX_LENGTH__MAX_HT_LENGTH__MASK                          0x3ffff000U
#define MAX_RX_LENGTH__MAX_HT_LENGTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3ffff000U) >> 12)
#define MAX_RX_LENGTH__MAX_HT_LENGTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x3ffff000U)
#define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3ffff000U) | (((u_int32_t)(src) <<\
                    12) & 0x3ffff000U)
#define MAX_RX_LENGTH__MAX_HT_LENGTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x3ffff000U)))
#define MAX_RX_LENGTH__TYPE                                           u_int32_t
#define MAX_RX_LENGTH__READ                                         0x3fffffffU
#define MAX_RX_LENGTH__WRITE                                        0x3fffffffU

#endif /* __MAX_RX_LENGTH_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_max_rx_length */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MAX_RX_LENGTH__NUM                 1

/* macros for BlueprintGlobalNameSpace::frame_control */
#ifndef __FRAME_CONTROL_MACRO__
#define __FRAME_CONTROL_MACRO__

/* macros for field cf_overlap_window */
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__SHIFT                               0
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WIDTH                               2
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MASK                      0x00000003U
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define FRAME_CONTROL__CF_OVERLAP_WINDOW__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field cf_scale_short */
#define FRAME_CONTROL__CF_SCALE_SHORT__SHIFT                                  2
#define FRAME_CONTROL__CF_SCALE_SHORT__WIDTH                                  1
#define FRAME_CONTROL__CF_SCALE_SHORT__MASK                         0x00000004U
#define FRAME_CONTROL__CF_SCALE_SHORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define FRAME_CONTROL__CF_SCALE_SHORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define FRAME_CONTROL__CF_SCALE_SHORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define FRAME_CONTROL__CF_SCALE_SHORT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define FRAME_CONTROL__CF_SCALE_SHORT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field cf_tx_clip */
#define FRAME_CONTROL__CF_TX_CLIP__SHIFT                                      3
#define FRAME_CONTROL__CF_TX_CLIP__WIDTH                                      3
#define FRAME_CONTROL__CF_TX_CLIP__MASK                             0x00000038U
#define FRAME_CONTROL__CF_TX_CLIP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000038U) >> 3)
#define FRAME_CONTROL__CF_TX_CLIP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000038U)
#define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000038U) | (((u_int32_t)(src) <<\
                    3) & 0x00000038U)
#define FRAME_CONTROL__CF_TX_CLIP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000038U)))

/* macros for field cf_tx_doublesamp_dac */
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__SHIFT                            6
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WIDTH                            2
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MASK                   0x000000c0U
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field tx_end_adjust */
#define FRAME_CONTROL__TX_END_ADJUST__SHIFT                                   8
#define FRAME_CONTROL__TX_END_ADJUST__WIDTH                                   8
#define FRAME_CONTROL__TX_END_ADJUST__MASK                          0x0000ff00U
#define FRAME_CONTROL__TX_END_ADJUST__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define FRAME_CONTROL__TX_END_ADJUST__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define FRAME_CONTROL__TX_END_ADJUST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field prepend_chan_info */
#define FRAME_CONTROL__PREPEND_CHAN_INFO__SHIFT                              16
#define FRAME_CONTROL__PREPEND_CHAN_INFO__WIDTH                               1
#define FRAME_CONTROL__PREPEND_CHAN_INFO__MASK                      0x00010000U
#define FRAME_CONTROL__PREPEND_CHAN_INFO__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define FRAME_CONTROL__PREPEND_CHAN_INFO__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define FRAME_CONTROL__PREPEND_CHAN_INFO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define FRAME_CONTROL__PREPEND_CHAN_INFO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define FRAME_CONTROL__PREPEND_CHAN_INFO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field short_high_par_norm */
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SHIFT                            17
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WIDTH                             1
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MASK                    0x00020000U
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field en_err_green_field */
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SHIFT                             18
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WIDTH                              1
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MASK                     0x00040000U
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field en_err_static20_mode_ht40_packet */
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SHIFT               19
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WIDTH                1
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MASK       0x00080000U
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field en_err_ofdm_xcorr */
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SHIFT                              20
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WIDTH                               1
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MASK                      0x00100000U
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field en_err_long_sc_thr */
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SHIFT                             21
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WIDTH                              1
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MASK                     0x00200000U
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field en_err_tim_long1 */
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SHIFT                               22
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WIDTH                                1
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MASK                       0x00400000U
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define FRAME_CONTROL__EN_ERR_TIM_LONG1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field en_err_tim_early_trig */
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SHIFT                          23
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WIDTH                           1
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MASK                  0x00800000U
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field en_err_tim_timeout */
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SHIFT                             24
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WIDTH                              1
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MASK                     0x01000000U
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field en_err_signal_parity */
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SHIFT                           25
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WIDTH                            1
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MASK                   0x02000000U
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field en_err_rate_illegal */
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SHIFT                            26
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WIDTH                             1
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MASK                    0x04000000U
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field en_err_length_illegal */
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SHIFT                          27
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WIDTH                           1
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MASK                  0x08000000U
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field no_6mbps_service_err */
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SHIFT                           28
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WIDTH                            1
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MASK                   0x10000000U
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field en_err_service */
#define FRAME_CONTROL__EN_ERR_SERVICE__SHIFT                                 29
#define FRAME_CONTROL__EN_ERR_SERVICE__WIDTH                                  1
#define FRAME_CONTROL__EN_ERR_SERVICE__MASK                         0x20000000U
#define FRAME_CONTROL__EN_ERR_SERVICE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define FRAME_CONTROL__EN_ERR_SERVICE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define FRAME_CONTROL__EN_ERR_SERVICE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define FRAME_CONTROL__EN_ERR_SERVICE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define FRAME_CONTROL__EN_ERR_SERVICE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field en_err_tx_underrun */
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SHIFT                             30
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WIDTH                              1
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MASK                     0x40000000U
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field en_err_rx_abort */
#define FRAME_CONTROL__EN_ERR_RX_ABORT__SHIFT                                31
#define FRAME_CONTROL__EN_ERR_RX_ABORT__WIDTH                                 1
#define FRAME_CONTROL__EN_ERR_RX_ABORT__MASK                        0x80000000U
#define FRAME_CONTROL__EN_ERR_RX_ABORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define FRAME_CONTROL__EN_ERR_RX_ABORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define FRAME_CONTROL__EN_ERR_RX_ABORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define FRAME_CONTROL__EN_ERR_RX_ABORT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define FRAME_CONTROL__EN_ERR_RX_ABORT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define FRAME_CONTROL__TYPE                                           u_int32_t
#define FRAME_CONTROL__READ                                         0xffffffffU
#define FRAME_CONTROL__WRITE                                        0xffffffffU

#endif /* __FRAME_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_frame_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FRAME_CONTROL__NUM                 1

/* macros for BlueprintGlobalNameSpace::rfbus_request */
#ifndef __RFBUS_REQUEST_MACRO__
#define __RFBUS_REQUEST_MACRO__

/* macros for field rfbus_request */
#define RFBUS_REQUEST__RFBUS_REQUEST__SHIFT                                   0
#define RFBUS_REQUEST__RFBUS_REQUEST__WIDTH                                   1
#define RFBUS_REQUEST__RFBUS_REQUEST__MASK                          0x00000001U
#define RFBUS_REQUEST__RFBUS_REQUEST__READ(src)  (u_int32_t)(src) & 0x00000001U
#define RFBUS_REQUEST__RFBUS_REQUEST__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RFBUS_REQUEST__RFBUS_REQUEST__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RFBUS_REQUEST__RFBUS_REQUEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RFBUS_REQUEST__RFBUS_REQUEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define RFBUS_REQUEST__TYPE                                           u_int32_t
#define RFBUS_REQUEST__READ                                         0x00000001U
#define RFBUS_REQUEST__WRITE                                        0x00000001U

#endif /* __RFBUS_REQUEST_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rfbus_request */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RFBUS_REQUEST__NUM                 1

/* macros for BlueprintGlobalNameSpace::rfbus_grant */
#ifndef __RFBUS_GRANT_MACRO__
#define __RFBUS_GRANT_MACRO__

/* macros for field rfbus_grant */
#define RFBUS_GRANT__RFBUS_GRANT__SHIFT                                       0
#define RFBUS_GRANT__RFBUS_GRANT__WIDTH                                       1
#define RFBUS_GRANT__RFBUS_GRANT__MASK                              0x00000001U
#define RFBUS_GRANT__RFBUS_GRANT__READ(src)      (u_int32_t)(src) & 0x00000001U
#define RFBUS_GRANT__RFBUS_GRANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RFBUS_GRANT__RFBUS_GRANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field bt_ant */
#define RFBUS_GRANT__BT_ANT__SHIFT                                            1
#define RFBUS_GRANT__BT_ANT__WIDTH                                            1
#define RFBUS_GRANT__BT_ANT__MASK                                   0x00000002U
#define RFBUS_GRANT__BT_ANT__READ(src)  (((u_int32_t)(src) & 0x00000002U) >> 1)
#define RFBUS_GRANT__BT_ANT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RFBUS_GRANT__BT_ANT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define RFBUS_GRANT__TYPE                                             u_int32_t
#define RFBUS_GRANT__READ                                           0x00000003U

#endif /* __RFBUS_GRANT_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rfbus_grant */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RFBUS_GRANT__NUM                   1

/* macros for BlueprintGlobalNameSpace::rifs */
#ifndef __RIFS_MACRO__
#define __RIFS_MACRO__

/* macros for field disable_fcc_fix */
#define RIFS__DISABLE_FCC_FIX__SHIFT                                         25
#define RIFS__DISABLE_FCC_FIX__WIDTH                                          1
#define RIFS__DISABLE_FCC_FIX__MASK                                 0x02000000U
#define RIFS__DISABLE_FCC_FIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define RIFS__DISABLE_FCC_FIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define RIFS__DISABLE_FCC_FIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define RIFS__DISABLE_FCC_FIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define RIFS__DISABLE_FCC_FIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field enable_reset_tdomain */
#define RIFS__ENABLE_RESET_TDOMAIN__SHIFT                                    26
#define RIFS__ENABLE_RESET_TDOMAIN__WIDTH                                     1
#define RIFS__ENABLE_RESET_TDOMAIN__MASK                            0x04000000U
#define RIFS__ENABLE_RESET_TDOMAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define RIFS__ENABLE_RESET_TDOMAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define RIFS__ENABLE_RESET_TDOMAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define RIFS__ENABLE_RESET_TDOMAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define RIFS__ENABLE_RESET_TDOMAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field disable_fcc_fix2 */
#define RIFS__DISABLE_FCC_FIX2__SHIFT                                        27
#define RIFS__DISABLE_FCC_FIX2__WIDTH                                         1
#define RIFS__DISABLE_FCC_FIX2__MASK                                0x08000000U
#define RIFS__DISABLE_FCC_FIX2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define RIFS__DISABLE_FCC_FIX2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define RIFS__DISABLE_FCC_FIX2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define RIFS__DISABLE_FCC_FIX2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define RIFS__DISABLE_FCC_FIX2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field disable_rifs_cck_fix */
#define RIFS__DISABLE_RIFS_CCK_FIX__SHIFT                                    28
#define RIFS__DISABLE_RIFS_CCK_FIX__WIDTH                                     1
#define RIFS__DISABLE_RIFS_CCK_FIX__MASK                            0x10000000U
#define RIFS__DISABLE_RIFS_CCK_FIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define RIFS__DISABLE_RIFS_CCK_FIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define RIFS__DISABLE_RIFS_CCK_FIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define RIFS__DISABLE_RIFS_CCK_FIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define RIFS__DISABLE_RIFS_CCK_FIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field disable_error_reset_fix */
#define RIFS__DISABLE_ERROR_RESET_FIX__SHIFT                                 29
#define RIFS__DISABLE_ERROR_RESET_FIX__WIDTH                                  1
#define RIFS__DISABLE_ERROR_RESET_FIX__MASK                         0x20000000U
#define RIFS__DISABLE_ERROR_RESET_FIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define RIFS__DISABLE_ERROR_RESET_FIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define RIFS__DISABLE_ERROR_RESET_FIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define RIFS__DISABLE_ERROR_RESET_FIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define RIFS__DISABLE_ERROR_RESET_FIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field radar_use_fdomain_reset */
#define RIFS__RADAR_USE_FDOMAIN_RESET__SHIFT                                 30
#define RIFS__RADAR_USE_FDOMAIN_RESET__WIDTH                                  1
#define RIFS__RADAR_USE_FDOMAIN_RESET__MASK                         0x40000000U
#define RIFS__RADAR_USE_FDOMAIN_RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define RIFS__RADAR_USE_FDOMAIN_RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define RIFS__RADAR_USE_FDOMAIN_RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define RIFS__RADAR_USE_FDOMAIN_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define RIFS__RADAR_USE_FDOMAIN_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)
#define RIFS__TYPE                                                    u_int32_t
#define RIFS__READ                                                  0x7e000000U
#define RIFS__WRITE                                                 0x7e000000U

#endif /* __RIFS_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rifs */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RIFS__NUM                          1

/* macros for BlueprintGlobalNameSpace::spectral_scan_2 */
#ifndef __SPECTRAL_SCAN_2_MACRO__
#define __SPECTRAL_SCAN_2_MACRO__

/* macros for field spectral_scan_rpt_mode */
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__SHIFT                        0
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WIDTH                        1
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MASK               0x00000001U
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field spectral_scan_noise_floor_ref */
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__SHIFT                 1
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WIDTH                 8
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MASK        0x000001feU
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000001feU)
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001feU) | (((u_int32_t)(src) <<\
                    1) & 0x000001feU)
#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000001feU)))
#define SPECTRAL_SCAN_2__TYPE                                         u_int32_t
#define SPECTRAL_SCAN_2__READ                                       0x000001ffU
#define SPECTRAL_SCAN_2__WRITE                                      0x000001ffU

#endif /* __SPECTRAL_SCAN_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_spectral_scan_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SPECTRAL_SCAN_2__NUM               1

/* macros for BlueprintGlobalNameSpace::rx_clear_delay */
#ifndef __RX_CLEAR_DELAY_MACRO__
#define __RX_CLEAR_DELAY_MACRO__

/* macros for field ofdm_xr_rx_clear_delay */
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__SHIFT                         0
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WIDTH                        10
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MASK                0x000003ffU
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))
#define RX_CLEAR_DELAY__TYPE                                          u_int32_t
#define RX_CLEAR_DELAY__READ                                        0x000003ffU
#define RX_CLEAR_DELAY__WRITE                                       0x000003ffU

#endif /* __RX_CLEAR_DELAY_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rx_clear_delay */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RX_CLEAR_DELAY__NUM                1

/* macros for BlueprintGlobalNameSpace::analog_power_on_time */
#ifndef __ANALOG_POWER_ON_TIME_MACRO__
#define __ANALOG_POWER_ON_TIME_MACRO__

/* macros for field active_to_receive */
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__SHIFT                        0
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WIDTH                       14
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MASK               0x00003fffU
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))
#define ANALOG_POWER_ON_TIME__TYPE                                    u_int32_t
#define ANALOG_POWER_ON_TIME__READ                                  0x00003fffU
#define ANALOG_POWER_ON_TIME__WRITE                                 0x00003fffU

#endif /* __ANALOG_POWER_ON_TIME_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_analog_power_on_time */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ANALOG_POWER_ON_TIME__NUM          1

/* macros for BlueprintGlobalNameSpace::tx_timing_1 */
#ifndef __TX_TIMING_1_MACRO__
#define __TX_TIMING_1_MACRO__

/* macros for field tx_frame_to_adc_off */
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__SHIFT                               0
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WIDTH                               8
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MASK                      0x000000ffU
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tx_frame_to_a2_rx_off */
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__SHIFT                             8
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WIDTH                             8
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MASK                    0x0000ff00U
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field tx_frame_to_dac_on */
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__SHIFT                               16
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WIDTH                                8
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MASK                       0x00ff0000U
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field tx_frame_to_a2_tx_on */
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__SHIFT                             24
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WIDTH                              8
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MASK                     0xff000000U
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define TX_TIMING_1__TYPE                                             u_int32_t
#define TX_TIMING_1__READ                                           0xffffffffU
#define TX_TIMING_1__WRITE                                          0xffffffffU

#endif /* __TX_TIMING_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_1__NUM                   1

/* macros for BlueprintGlobalNameSpace::tx_timing_2 */
#ifndef __TX_TIMING_2_MACRO__
#define __TX_TIMING_2_MACRO__

/* macros for field tx_frame_to_tx_d_start */
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__SHIFT                            0
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WIDTH                            8
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MASK                   0x000000ffU
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tx_frame_to_pa_on */
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__SHIFT                                 8
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WIDTH                                 8
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MASK                        0x0000ff00U
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TX_TIMING_2__TX_FRAME_TO_PA_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field tx_end_to_pa_off */
#define TX_TIMING_2__TX_END_TO_PA_OFF__SHIFT                                 16
#define TX_TIMING_2__TX_END_TO_PA_OFF__WIDTH                                  8
#define TX_TIMING_2__TX_END_TO_PA_OFF__MASK                         0x00ff0000U
#define TX_TIMING_2__TX_END_TO_PA_OFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TX_TIMING_2__TX_END_TO_PA_OFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TX_TIMING_2__TX_END_TO_PA_OFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field tx_end_to_a2_tx_off */
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__SHIFT                              24
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WIDTH                               8
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MASK                      0xff000000U
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define TX_TIMING_2__TYPE                                             u_int32_t
#define TX_TIMING_2__READ                                           0xffffffffU
#define TX_TIMING_2__WRITE                                          0xffffffffU

#endif /* __TX_TIMING_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_2__NUM                   1

/* macros for BlueprintGlobalNameSpace::tx_timing_3 */
#ifndef __TX_TIMING_3_MACRO__
#define __TX_TIMING_3_MACRO__

/* macros for field tx_end_to_dac_off */
#define TX_TIMING_3__TX_END_TO_DAC_OFF__SHIFT                                 0
#define TX_TIMING_3__TX_END_TO_DAC_OFF__WIDTH                                 8
#define TX_TIMING_3__TX_END_TO_DAC_OFF__MASK                        0x000000ffU
#define TX_TIMING_3__TX_END_TO_DAC_OFF__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define TX_TIMING_3__TX_END_TO_DAC_OFF__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TX_TIMING_3__TX_END_TO_DAC_OFF__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tx_frame_to_therm_chain_on */
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__SHIFT                        8
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WIDTH                        8
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MASK               0x0000ff00U
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field tx_end_to_a2_rx_on */
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__SHIFT                               16
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WIDTH                                8
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MASK                       0x00ff0000U
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TX_TIMING_3__TX_END_TO_A2_RX_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field tx_end_to_adc_on */
#define TX_TIMING_3__TX_END_TO_ADC_ON__SHIFT                                 24
#define TX_TIMING_3__TX_END_TO_ADC_ON__WIDTH                                  8
#define TX_TIMING_3__TX_END_TO_ADC_ON__MASK                         0xff000000U
#define TX_TIMING_3__TX_END_TO_ADC_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define TX_TIMING_3__TX_END_TO_ADC_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define TX_TIMING_3__TX_END_TO_ADC_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define TX_TIMING_3__TYPE                                             u_int32_t
#define TX_TIMING_3__READ                                           0xffffffffU
#define TX_TIMING_3__WRITE                                          0xffffffffU

#endif /* __TX_TIMING_3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_3__NUM                   1

/* macros for BlueprintGlobalNameSpace::xpa_timing_control */
#ifndef __XPA_TIMING_CONTROL_MACRO__
#define __XPA_TIMING_CONTROL_MACRO__

/* macros for field tx_frame_to_xpaa_on */
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__SHIFT                        0
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WIDTH                        8
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MASK               0x000000ffU
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tx_frame_to_xpab_on */
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__SHIFT                        8
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WIDTH                        8
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MASK               0x0000ff00U
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field tx_end_to_xpaa_off */
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__SHIFT                        16
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WIDTH                         8
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MASK                0x00ff0000U
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field tx_end_to_xpab_off */
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__SHIFT                        24
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WIDTH                         8
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MASK                0xff000000U
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define XPA_TIMING_CONTROL__TYPE                                      u_int32_t
#define XPA_TIMING_CONTROL__READ                                    0xffffffffU
#define XPA_TIMING_CONTROL__WRITE                                   0xffffffffU

#endif /* __XPA_TIMING_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_xpa_timing_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_XPA_TIMING_CONTROL__NUM            1

/* macros for BlueprintGlobalNameSpace::misc_pa_control */
#ifndef __MISC_PA_CONTROL_MACRO__
#define __MISC_PA_CONTROL_MACRO__

/* macros for field xpaa_active_high */
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SHIFT                              0
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WIDTH                              1
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MASK                     0x00000001U
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field xpab_active_high */
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SHIFT                              1
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WIDTH                              1
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MASK                     0x00000002U
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field enable_xpaa */
#define MISC_PA_CONTROL__ENABLE_XPAA__SHIFT                                   2
#define MISC_PA_CONTROL__ENABLE_XPAA__WIDTH                                   1
#define MISC_PA_CONTROL__ENABLE_XPAA__MASK                          0x00000004U
#define MISC_PA_CONTROL__ENABLE_XPAA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define MISC_PA_CONTROL__ENABLE_XPAA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define MISC_PA_CONTROL__ENABLE_XPAA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define MISC_PA_CONTROL__ENABLE_XPAA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define MISC_PA_CONTROL__ENABLE_XPAA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field enable_xpab */
#define MISC_PA_CONTROL__ENABLE_XPAB__SHIFT                                   3
#define MISC_PA_CONTROL__ENABLE_XPAB__WIDTH                                   1
#define MISC_PA_CONTROL__ENABLE_XPAB__MASK                          0x00000008U
#define MISC_PA_CONTROL__ENABLE_XPAB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define MISC_PA_CONTROL__ENABLE_XPAB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define MISC_PA_CONTROL__ENABLE_XPAB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define MISC_PA_CONTROL__ENABLE_XPAB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define MISC_PA_CONTROL__ENABLE_XPAB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)
#define MISC_PA_CONTROL__TYPE                                         u_int32_t
#define MISC_PA_CONTROL__READ                                       0x0000000fU
#define MISC_PA_CONTROL__WRITE                                      0x0000000fU

#endif /* __MISC_PA_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_misc_pa_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MISC_PA_CONTROL__NUM               1

/* macros for BlueprintGlobalNameSpace::switch_table_chn_b0 */
#ifndef __SWITCH_TABLE_CHN_B0_MACRO__
#define __SWITCH_TABLE_CHN_B0_MACRO__

/* macros for field switch_table_idle_0 */
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__SHIFT                       0
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WIDTH                       2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MASK              0x00000003U
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field switch_table_t_0 */
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__SHIFT                          2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WIDTH                          2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MASK                 0x0000000cU
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field switch_table_r_0 */
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__SHIFT                          4
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WIDTH                          2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MASK                 0x00000030U
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field switch_table_rx1_0 */
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__SHIFT                        6
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WIDTH                        2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MASK               0x000000c0U
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field switch_table_rx12_0 */
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__SHIFT                       8
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WIDTH                       2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MASK              0x00000300U
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field switch_table_b_0 */
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__SHIFT                         10
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WIDTH                          2
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MASK                 0x00000c00U
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))
#define SWITCH_TABLE_CHN_B0__TYPE                                     u_int32_t
#define SWITCH_TABLE_CHN_B0__READ                                   0x00000fffU
#define SWITCH_TABLE_CHN_B0__WRITE                                  0x00000fffU

#endif /* __SWITCH_TABLE_CHN_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_chn_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_CHN_B0__NUM           1

/* macros for BlueprintGlobalNameSpace::switch_table_com1 */
#ifndef __SWITCH_TABLE_COM1_MACRO__
#define __SWITCH_TABLE_COM1_MACRO__

/* macros for field switch_table_com_idle */
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__SHIFT                       0
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WIDTH                       4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MASK              0x0000000fU
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field switch_table_com_t1 */
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__SHIFT                         4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WIDTH                         4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MASK                0x000000f0U
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field switch_table_com_t2 */
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__SHIFT                         8
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WIDTH                         4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MASK                0x00000f00U
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field switch_table_com_b */
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__SHIFT                         12
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WIDTH                          4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MASK                 0x0000f000U
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field switch_table_com_idle_alt */
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__SHIFT                  16
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WIDTH                   4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MASK          0x000f0000U
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field switch_table_com_tx_1chn */
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__SHIFT                   20
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WIDTH                    4
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MASK           0x00f00000U
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00f00000U) >> 20)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00f00000U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x00f00000U)
#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00f00000U)))
#define SWITCH_TABLE_COM1__TYPE                                       u_int32_t
#define SWITCH_TABLE_COM1__READ                                     0x00ffffffU
#define SWITCH_TABLE_COM1__WRITE                                    0x00ffffffU

#endif /* __SWITCH_TABLE_COM1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_com1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM1__NUM             1

/* macros for BlueprintGlobalNameSpace::switch_table_com2 */
#ifndef __SWITCH_TABLE_COM2_MACRO__
#define __SWITCH_TABLE_COM2_MACRO__

/* macros for field switch_table_com_ra1l1 */
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__SHIFT                      0
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WIDTH                      4
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MASK             0x0000000fU
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field switch_table_com_ra2l1 */
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__SHIFT                      4
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WIDTH                      4
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MASK             0x000000f0U
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field switch_table_com_ra1l2 */
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__SHIFT                      8
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WIDTH                      4
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MASK             0x00000f00U
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field switch_table_com_ra2l2 */
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__SHIFT                     12
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WIDTH                      4
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MASK             0x0000f000U
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field switch_table_com_ra12 */
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__SHIFT                      16
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WIDTH                       4
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MASK              0x000f0000U
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))
#define SWITCH_TABLE_COM2__TYPE                                       u_int32_t
#define SWITCH_TABLE_COM2__READ                                     0x000fffffU
#define SWITCH_TABLE_COM2__WRITE                                    0x000fffffU

#endif /* __SWITCH_TABLE_COM2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_com2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM2__NUM             1

/* macros for BlueprintGlobalNameSpace::multichain_enable */
#ifndef __MULTICHAIN_ENABLE_MACRO__
#define __MULTICHAIN_ENABLE_MACRO__

/* macros for field rx_chain_mask */
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__SHIFT                               0
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WIDTH                               3
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MASK                      0x00000007U
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))
#define MULTICHAIN_ENABLE__TYPE                                       u_int32_t
#define MULTICHAIN_ENABLE__READ                                     0x00000007U
#define MULTICHAIN_ENABLE__WRITE                                    0x00000007U

#endif /* __MULTICHAIN_ENABLE_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_multichain_enable */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MULTICHAIN_ENABLE__NUM             1

/* macros for BlueprintGlobalNameSpace::cal_chain_mask */
#ifndef __CAL_CHAIN_MASK_MACRO__
#define __CAL_CHAIN_MASK_MACRO__

/* macros for field cal_chain_mask */
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__SHIFT                                 0
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WIDTH                                 3
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MASK                        0x00000007U
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))
#define CAL_CHAIN_MASK__TYPE                                          u_int32_t
#define CAL_CHAIN_MASK__READ                                        0x00000007U
#define CAL_CHAIN_MASK__WRITE                                       0x00000007U

#endif /* __CAL_CHAIN_MASK_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_chain_mask */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_CHAIN_MASK__NUM                1

/* macros for BlueprintGlobalNameSpace::agc_control */
#ifndef __AGC_CONTROL_MACRO__
#define __AGC_CONTROL_MACRO__

/* macros for field do_calibrate */
#define AGC_CONTROL__DO_CALIBRATE__SHIFT                                      0
#define AGC_CONTROL__DO_CALIBRATE__WIDTH                                      1
#define AGC_CONTROL__DO_CALIBRATE__MASK                             0x00000001U
#define AGC_CONTROL__DO_CALIBRATE__READ(src)     (u_int32_t)(src) & 0x00000001U
#define AGC_CONTROL__DO_CALIBRATE__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
#define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define AGC_CONTROL__DO_CALIBRATE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define AGC_CONTROL__DO_CALIBRATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define AGC_CONTROL__DO_CALIBRATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field do_noisefloor */
#define AGC_CONTROL__DO_NOISEFLOOR__SHIFT                                     1
#define AGC_CONTROL__DO_NOISEFLOOR__WIDTH                                     1
#define AGC_CONTROL__DO_NOISEFLOOR__MASK                            0x00000002U
#define AGC_CONTROL__DO_NOISEFLOOR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define AGC_CONTROL__DO_NOISEFLOOR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define AGC_CONTROL__DO_NOISEFLOOR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define AGC_CONTROL__DO_NOISEFLOOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define AGC_CONTROL__DO_NOISEFLOOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field min_num_gain_change */
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__SHIFT                               3
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WIDTH                               3
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MASK                      0x00000038U
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000038U) >> 3)
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000038U)
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000038U) | (((u_int32_t)(src) <<\
                    3) & 0x00000038U)
#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000038U)))

/* macros for field ycok_max */
#define AGC_CONTROL__YCOK_MAX__SHIFT                                          6
#define AGC_CONTROL__YCOK_MAX__WIDTH                                          4
#define AGC_CONTROL__YCOK_MAX__MASK                                 0x000003c0U
#define AGC_CONTROL__YCOK_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003c0U) >> 6)
#define AGC_CONTROL__YCOK_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000003c0U)
#define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000003c0U)
#define AGC_CONTROL__YCOK_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000003c0U)))

/* macros for field leaky_bucket_enable */
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SHIFT                              10
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WIDTH                               1
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MASK                      0x00000400U
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field CAL_enable */
#define AGC_CONTROL__CAL_ENABLE__SHIFT                                       11
#define AGC_CONTROL__CAL_ENABLE__WIDTH                                        1
#define AGC_CONTROL__CAL_ENABLE__MASK                               0x00000800U
#define AGC_CONTROL__CAL_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define AGC_CONTROL__CAL_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define AGC_CONTROL__CAL_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define AGC_CONTROL__CAL_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define AGC_CONTROL__CAL_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field use_table_seed */
#define AGC_CONTROL__USE_TABLE_SEED__SHIFT                                   12
#define AGC_CONTROL__USE_TABLE_SEED__WIDTH                                    1
#define AGC_CONTROL__USE_TABLE_SEED__MASK                           0x00001000U
#define AGC_CONTROL__USE_TABLE_SEED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define AGC_CONTROL__USE_TABLE_SEED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define AGC_CONTROL__USE_TABLE_SEED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define AGC_CONTROL__USE_TABLE_SEED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define AGC_CONTROL__USE_TABLE_SEED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field agc_update_table_seed */
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SHIFT                            13
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WIDTH                             1
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MASK                    0x00002000U
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field enable_noisefloor */
#define AGC_CONTROL__ENABLE_NOISEFLOOR__SHIFT                                15
#define AGC_CONTROL__ENABLE_NOISEFLOOR__WIDTH                                 1
#define AGC_CONTROL__ENABLE_NOISEFLOOR__MASK                        0x00008000U
#define AGC_CONTROL__ENABLE_NOISEFLOOR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define AGC_CONTROL__ENABLE_NOISEFLOOR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define AGC_CONTROL__ENABLE_NOISEFLOOR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define AGC_CONTROL__ENABLE_NOISEFLOOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define AGC_CONTROL__ENABLE_NOISEFLOOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field enable_fltr_cal */
#define AGC_CONTROL__ENABLE_FLTR_CAL__SHIFT                                  16
#define AGC_CONTROL__ENABLE_FLTR_CAL__WIDTH                                   1
#define AGC_CONTROL__ENABLE_FLTR_CAL__MASK                          0x00010000U
#define AGC_CONTROL__ENABLE_FLTR_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define AGC_CONTROL__ENABLE_FLTR_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define AGC_CONTROL__ENABLE_FLTR_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define AGC_CONTROL__ENABLE_FLTR_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define AGC_CONTROL__ENABLE_FLTR_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field no_update_noisefloor */
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SHIFT                             17
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WIDTH                              1
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MASK                     0x00020000U
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field extend_NF_pwr_meas */
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SHIFT                               18
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WIDTH                                1
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MASK                       0x00040000U
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field clc_success */
#define AGC_CONTROL__CLC_SUCCESS__SHIFT                                      19
#define AGC_CONTROL__CLC_SUCCESS__WIDTH                                       1
#define AGC_CONTROL__CLC_SUCCESS__MASK                              0x00080000U
#define AGC_CONTROL__CLC_SUCCESS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define AGC_CONTROL__CLC_SUCCESS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define AGC_CONTROL__CLC_SUCCESS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field enable_pkdet_cal */
#define AGC_CONTROL__ENABLE_PKDET_CAL__SHIFT                                 20
#define AGC_CONTROL__ENABLE_PKDET_CAL__WIDTH                                  1
#define AGC_CONTROL__ENABLE_PKDET_CAL__MASK                         0x00100000U
#define AGC_CONTROL__ENABLE_PKDET_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define AGC_CONTROL__ENABLE_PKDET_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define AGC_CONTROL__ENABLE_PKDET_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define AGC_CONTROL__ENABLE_PKDET_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define AGC_CONTROL__ENABLE_PKDET_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)
#define AGC_CONTROL__TYPE                                             u_int32_t
#define AGC_CONTROL__READ                                           0x001fbffbU
#define AGC_CONTROL__WRITE                                          0x001fbffbU

#endif /* __AGC_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_agc_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_AGC_CONTROL__NUM                   1

/* macros for BlueprintGlobalNameSpace::iq_adc_cal_mode */
#ifndef __IQ_ADC_CAL_MODE_MACRO__
#define __IQ_ADC_CAL_MODE_MACRO__

/* macros for field gain_dc_iq_cal_mode */
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__SHIFT                           0
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WIDTH                           2
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MASK                  0x00000003U
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field test_caladcoff */
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SHIFT                                2
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WIDTH                                1
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MASK                       0x00000004U
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)
#define IQ_ADC_CAL_MODE__TYPE                                         u_int32_t
#define IQ_ADC_CAL_MODE__READ                                       0x00000007U
#define IQ_ADC_CAL_MODE__WRITE                                      0x00000007U

#endif /* __IQ_ADC_CAL_MODE_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_iq_adc_cal_mode */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_IQ_ADC_CAL_MODE__NUM               1

/* macros for BlueprintGlobalNameSpace::fcal_1 */
#ifndef __FCAL_1_MACRO__
#define __FCAL_1_MACRO__

/* macros for field flc_pb_fstep */
#define FCAL_1__FLC_PB_FSTEP__SHIFT                                           0
#define FCAL_1__FLC_PB_FSTEP__WIDTH                                          10
#define FCAL_1__FLC_PB_FSTEP__MASK                                  0x000003ffU
#define FCAL_1__FLC_PB_FSTEP__READ(src)          (u_int32_t)(src) & 0x000003ffU
#define FCAL_1__FLC_PB_FSTEP__WRITE(src)       ((u_int32_t)(src) & 0x000003ffU)
#define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define FCAL_1__FLC_PB_FSTEP__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field flc_sb_fstep */
#define FCAL_1__FLC_SB_FSTEP__SHIFT                                          10
#define FCAL_1__FLC_SB_FSTEP__WIDTH                                          10
#define FCAL_1__FLC_SB_FSTEP__MASK                                  0x000ffc00U
#define FCAL_1__FLC_SB_FSTEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define FCAL_1__FLC_SB_FSTEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define FCAL_1__FLC_SB_FSTEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field flc_pb_atten */
#define FCAL_1__FLC_PB_ATTEN__SHIFT                                          20
#define FCAL_1__FLC_PB_ATTEN__WIDTH                                           5
#define FCAL_1__FLC_PB_ATTEN__MASK                                  0x01f00000U
#define FCAL_1__FLC_PB_ATTEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define FCAL_1__FLC_PB_ATTEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define FCAL_1__FLC_PB_ATTEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field flc_sb_atten */
#define FCAL_1__FLC_SB_ATTEN__SHIFT                                          25
#define FCAL_1__FLC_SB_ATTEN__WIDTH                                           5
#define FCAL_1__FLC_SB_ATTEN__MASK                                  0x3e000000U
#define FCAL_1__FLC_SB_ATTEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define FCAL_1__FLC_SB_ATTEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define FCAL_1__FLC_SB_ATTEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))
#define FCAL_1__TYPE                                                  u_int32_t
#define FCAL_1__READ                                                0x3fffffffU
#define FCAL_1__WRITE                                               0x3fffffffU

#endif /* __FCAL_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_fcal_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FCAL_1__NUM                        1

/* macros for BlueprintGlobalNameSpace::fcal_2_b0 */
#ifndef __FCAL_2_B0_MACRO__
#define __FCAL_2_B0_MACRO__

/* macros for field flc_pwr_thresh */
#define FCAL_2_B0__FLC_PWR_THRESH__SHIFT                                      0
#define FCAL_2_B0__FLC_PWR_THRESH__WIDTH                                      3
#define FCAL_2_B0__FLC_PWR_THRESH__MASK                             0x00000007U
#define FCAL_2_B0__FLC_PWR_THRESH__READ(src)     (u_int32_t)(src) & 0x00000007U
#define FCAL_2_B0__FLC_PWR_THRESH__WRITE(src)  ((u_int32_t)(src) & 0x00000007U)
#define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define FCAL_2_B0__FLC_PWR_THRESH__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field flc_sw_cap_val_0 */
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__SHIFT                                    3
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WIDTH                                    5
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MASK                           0x000000f8U
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f8U) >> 3)
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000000f8U)
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000000f8U)
#define FCAL_2_B0__FLC_SW_CAP_VAL_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000000f8U)))

/* macros for field flc_bbmiscgain */
#define FCAL_2_B0__FLC_BBMISCGAIN__SHIFT                                      8
#define FCAL_2_B0__FLC_BBMISCGAIN__WIDTH                                      2
#define FCAL_2_B0__FLC_BBMISCGAIN__MASK                             0x00000300U
#define FCAL_2_B0__FLC_BBMISCGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define FCAL_2_B0__FLC_BBMISCGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define FCAL_2_B0__FLC_BBMISCGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field flc_bb1dbgain */
#define FCAL_2_B0__FLC_BB1DBGAIN__SHIFT                                      10
#define FCAL_2_B0__FLC_BB1DBGAIN__WIDTH                                       3
#define FCAL_2_B0__FLC_BB1DBGAIN__MASK                              0x00001c00U
#define FCAL_2_B0__FLC_BB1DBGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001c00U) >> 10)
#define FCAL_2_B0__FLC_BB1DBGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00001c00U)
#define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00001c00U)
#define FCAL_2_B0__FLC_BB1DBGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00001c00U)))

/* macros for field flc_bb6dbgain */
#define FCAL_2_B0__FLC_BB6DBGAIN__SHIFT                                      13
#define FCAL_2_B0__FLC_BB6DBGAIN__WIDTH                                       2
#define FCAL_2_B0__FLC_BB6DBGAIN__MASK                              0x00006000U
#define FCAL_2_B0__FLC_BB6DBGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00006000U) >> 13)
#define FCAL_2_B0__FLC_BB6DBGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00006000U)
#define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00006000U) | (((u_int32_t)(src) <<\
                    13) & 0x00006000U)
#define FCAL_2_B0__FLC_BB6DBGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00006000U)))

/* macros for field flc_sw_cap_set */
#define FCAL_2_B0__FLC_SW_CAP_SET__SHIFT                                     15
#define FCAL_2_B0__FLC_SW_CAP_SET__WIDTH                                      1
#define FCAL_2_B0__FLC_SW_CAP_SET__MASK                             0x00008000U
#define FCAL_2_B0__FLC_SW_CAP_SET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define FCAL_2_B0__FLC_SW_CAP_SET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define FCAL_2_B0__FLC_SW_CAP_SET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define FCAL_2_B0__FLC_SW_CAP_SET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define FCAL_2_B0__FLC_SW_CAP_SET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field flc_meas_win */
#define FCAL_2_B0__FLC_MEAS_WIN__SHIFT                                       16
#define FCAL_2_B0__FLC_MEAS_WIN__WIDTH                                        3
#define FCAL_2_B0__FLC_MEAS_WIN__MASK                               0x00070000U
#define FCAL_2_B0__FLC_MEAS_WIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00070000U) >> 16)
#define FCAL_2_B0__FLC_MEAS_WIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00070000U)
#define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((u_int32_t)(src) <<\
                    16) & 0x00070000U)
#define FCAL_2_B0__FLC_MEAS_WIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field flc_cap_val_status_0 */
#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__SHIFT                               20
#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__WIDTH                                5
#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__MASK                       0x01f00000U
#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define FCAL_2_B0__TYPE                                               u_int32_t
#define FCAL_2_B0__READ                                             0x01f7ffffU
#define FCAL_2_B0__WRITE                                            0x01f7ffffU

#endif /* __FCAL_2_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_fcal_2_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FCAL_2_B0__NUM                     1

/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b0 */
#ifndef __DFT_TONE_CTRL_B0_MACRO__
#define __DFT_TONE_CTRL_B0_MACRO__

/* macros for field dft_tone_en_0 */
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SHIFT                                0
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WIDTH                                1
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MASK                       0x00000001U
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field dft_tone_amp_sel_0 */
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__SHIFT                           2
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WIDTH                           2
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MASK                  0x0000000cU
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field dft_tone_freq_ang_0 */
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__SHIFT                          4
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WIDTH                          9
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MASK                 0x00001ff0U
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001ff0U) >> 4)
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00001ff0U)
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001ff0U) | (((u_int32_t)(src) <<\
                    4) & 0x00001ff0U)
#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00001ff0U)))
#define DFT_TONE_CTRL_B0__TYPE                                        u_int32_t
#define DFT_TONE_CTRL_B0__READ                                      0x00001ffdU
#define DFT_TONE_CTRL_B0__WRITE                                     0x00001ffdU

#endif /* __DFT_TONE_CTRL_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_dft_tone_ctrl_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_DFT_TONE_CTRL_B0__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_cal_ctrl */
#ifndef __CL_CAL_CTRL_MACRO__
#define __CL_CAL_CTRL_MACRO__

/* macros for field enable_parallel_cal */
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SHIFT                               0
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WIDTH                               1
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MASK                      0x00000001U
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field enable_cl_calibrate */
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SHIFT                               1
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WIDTH                               1
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MASK                      0x00000002U
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field cf_clc_test_point */
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__SHIFT                                 2
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WIDTH                                 2
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MASK                        0x0000000cU
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define CL_CAL_CTRL__CF_CLC_TEST_POINT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field cf_clc_forced_pagain */
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__SHIFT                              4
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WIDTH                              4
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MASK                     0x000000f0U
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field carr_leak_max_offset */
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__SHIFT                              8
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WIDTH                              8
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MASK                     0x0000ff00U
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field cf_clc_init_bbgain */
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__SHIFT                               16
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WIDTH                                6
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MASK                       0x003f0000U
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field cf_adc_bound */
#define CL_CAL_CTRL__CF_ADC_BOUND__SHIFT                                     22
#define CL_CAL_CTRL__CF_ADC_BOUND__WIDTH                                      8
#define CL_CAL_CTRL__CF_ADC_BOUND__MASK                             0x3fc00000U
#define CL_CAL_CTRL__CF_ADC_BOUND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3fc00000U) >> 22)
#define CL_CAL_CTRL__CF_ADC_BOUND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x3fc00000U)
#define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x3fc00000U)
#define CL_CAL_CTRL__CF_ADC_BOUND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x3fc00000U)))

/* macros for field use_dac_cl_correction */
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SHIFT                            30
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WIDTH                             1
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MASK                    0x40000000U
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field cl_map_hw_gen */
#define CL_CAL_CTRL__CL_MAP_HW_GEN__SHIFT                                    31
#define CL_CAL_CTRL__CL_MAP_HW_GEN__WIDTH                                     1
#define CL_CAL_CTRL__CL_MAP_HW_GEN__MASK                            0x80000000U
#define CL_CAL_CTRL__CL_MAP_HW_GEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define CL_CAL_CTRL__CL_MAP_HW_GEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define CL_CAL_CTRL__CL_MAP_HW_GEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define CL_CAL_CTRL__CL_MAP_HW_GEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define CL_CAL_CTRL__CL_MAP_HW_GEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define CL_CAL_CTRL__TYPE                                             u_int32_t
#define CL_CAL_CTRL__READ                                           0xffffffffU
#define CL_CAL_CTRL__WRITE                                          0xffffffffU

#endif /* __CL_CAL_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_cal_ctrl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_CAL_CTRL__NUM                   1

/* macros for BlueprintGlobalNameSpace::cl_map_0 */
#ifndef __CL_MAP_0_MACRO__
#define __CL_MAP_0_MACRO__

/* macros for field cl_map_0 */
#define CL_MAP_0__CL_MAP_0__SHIFT                                             0
#define CL_MAP_0__CL_MAP_0__WIDTH                                            32
#define CL_MAP_0__CL_MAP_0__MASK                                    0xffffffffU
#define CL_MAP_0__CL_MAP_0__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_0__CL_MAP_0__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_0__CL_MAP_0__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_0__TYPE                                                u_int32_t
#define CL_MAP_0__READ                                              0xffffffffU
#define CL_MAP_0__WRITE                                             0xffffffffU

#endif /* __CL_MAP_0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_0_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_0_B0__NUM                   1

/* macros for BlueprintGlobalNameSpace::cl_map_1 */
#ifndef __CL_MAP_1_MACRO__
#define __CL_MAP_1_MACRO__

/* macros for field cl_map_1 */
#define CL_MAP_1__CL_MAP_1__SHIFT                                             0
#define CL_MAP_1__CL_MAP_1__WIDTH                                            32
#define CL_MAP_1__CL_MAP_1__MASK                                    0xffffffffU
#define CL_MAP_1__CL_MAP_1__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_1__CL_MAP_1__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_1__CL_MAP_1__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_1__TYPE                                                u_int32_t
#define CL_MAP_1__READ                                              0xffffffffU
#define CL_MAP_1__WRITE                                             0xffffffffU

#endif /* __CL_MAP_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_1_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_1_B0__NUM                   1

/* macros for BlueprintGlobalNameSpace::cl_map_2 */
#ifndef __CL_MAP_2_MACRO__
#define __CL_MAP_2_MACRO__

/* macros for field cl_map_2 */
#define CL_MAP_2__CL_MAP_2__SHIFT                                             0
#define CL_MAP_2__CL_MAP_2__WIDTH                                            32
#define CL_MAP_2__CL_MAP_2__MASK                                    0xffffffffU
#define CL_MAP_2__CL_MAP_2__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_2__CL_MAP_2__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_2__CL_MAP_2__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_2__TYPE                                                u_int32_t
#define CL_MAP_2__READ                                              0xffffffffU
#define CL_MAP_2__WRITE                                             0xffffffffU

#endif /* __CL_MAP_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_2_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_2_B0__NUM                   1

/* macros for BlueprintGlobalNameSpace::cl_map_3 */
#ifndef __CL_MAP_3_MACRO__
#define __CL_MAP_3_MACRO__

/* macros for field cl_map_3 */
#define CL_MAP_3__CL_MAP_3__SHIFT                                             0
#define CL_MAP_3__CL_MAP_3__WIDTH                                            32
#define CL_MAP_3__CL_MAP_3__MASK                                    0xffffffffU
#define CL_MAP_3__CL_MAP_3__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_3__CL_MAP_3__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_3__CL_MAP_3__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_3__TYPE                                                u_int32_t
#define CL_MAP_3__READ                                              0xffffffffU
#define CL_MAP_3__WRITE                                             0xffffffffU

#endif /* __CL_MAP_3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_3_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_3_B0__NUM                   1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */
#ifndef __CL_MAP_PAL_0_MACRO__
#define __CL_MAP_PAL_0_MACRO__

/* macros for field cl_map_0 */
#define CL_MAP_PAL_0__CL_MAP_0__SHIFT                                         0
#define CL_MAP_PAL_0__CL_MAP_0__WIDTH                                        32
#define CL_MAP_PAL_0__CL_MAP_0__MASK                                0xffffffffU
#define CL_MAP_PAL_0__CL_MAP_0__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_0__TYPE                                            u_int32_t
#define CL_MAP_PAL_0__READ                                          0xffffffffU
#define CL_MAP_PAL_0__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_0_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_0_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */
#ifndef __CL_MAP_PAL_1_MACRO__
#define __CL_MAP_PAL_1_MACRO__

/* macros for field cl_map_1 */
#define CL_MAP_PAL_1__CL_MAP_1__SHIFT                                         0
#define CL_MAP_PAL_1__CL_MAP_1__WIDTH                                        32
#define CL_MAP_PAL_1__CL_MAP_1__MASK                                0xffffffffU
#define CL_MAP_PAL_1__CL_MAP_1__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_1__TYPE                                            u_int32_t
#define CL_MAP_PAL_1__READ                                          0xffffffffU
#define CL_MAP_PAL_1__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_1_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_1_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */
#ifndef __CL_MAP_PAL_2_MACRO__
#define __CL_MAP_PAL_2_MACRO__

/* macros for field cl_map_2 */
#define CL_MAP_PAL_2__CL_MAP_2__SHIFT                                         0
#define CL_MAP_PAL_2__CL_MAP_2__WIDTH                                        32
#define CL_MAP_PAL_2__CL_MAP_2__MASK                                0xffffffffU
#define CL_MAP_PAL_2__CL_MAP_2__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_2__TYPE                                            u_int32_t
#define CL_MAP_PAL_2__READ                                          0xffffffffU
#define CL_MAP_PAL_2__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_2_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_2_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */
#ifndef __CL_MAP_PAL_3_MACRO__
#define __CL_MAP_PAL_3_MACRO__

/* macros for field cl_map_3 */
#define CL_MAP_PAL_3__CL_MAP_3__SHIFT                                         0
#define CL_MAP_PAL_3__CL_MAP_3__WIDTH                                        32
#define CL_MAP_PAL_3__CL_MAP_3__MASK                                0xffffffffU
#define CL_MAP_PAL_3__CL_MAP_3__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_3__TYPE                                            u_int32_t
#define CL_MAP_PAL_3__READ                                          0xffffffffU
#define CL_MAP_PAL_3__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_3_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_3_B0__NUM               1

/* macros for BlueprintGlobalNameSpace::cl_tab */
#ifndef __CL_TAB_MACRO__
#define __CL_TAB_MACRO__

/* macros for field cl_gain_mod */
#define CL_TAB__CL_GAIN_MOD__SHIFT                                            0
#define CL_TAB__CL_GAIN_MOD__WIDTH                                            5
#define CL_TAB__CL_GAIN_MOD__MASK                                   0x0000001fU
#define CL_TAB__CL_GAIN_MOD__READ(src)           (u_int32_t)(src) & 0x0000001fU
#define CL_TAB__CL_GAIN_MOD__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))

/* macros for field carr_lk_dc_add_Q */
#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT                                       5
#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH                                      11
#define CL_TAB__CARR_LK_DC_ADD_Q__MASK                              0x0000ffe0U
#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ffe0U) >> 5)
#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x0000ffe0U)
#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffe0U) | (((u_int32_t)(src) <<\
                    5) & 0x0000ffe0U)
#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x0000ffe0U)))

/* macros for field carr_lk_dc_add_I */
#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT                                      16
#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH                                      11
#define CL_TAB__CARR_LK_DC_ADD_I__MASK                              0x07ff0000U
#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x07ff0000U)
#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x07ff0000U)
#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x07ff0000U)))

/* macros for field bb_gain */
#define CL_TAB__BB_GAIN__SHIFT                                               27
#define CL_TAB__BB_GAIN__WIDTH                                                4
#define CL_TAB__BB_GAIN__MASK                                       0x78000000U
#define CL_TAB__BB_GAIN__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
#define CL_TAB__BB_GAIN__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
#define CL_TAB__BB_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define CL_TAB__BB_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))
#define CL_TAB__TYPE                                                  u_int32_t
#define CL_TAB__READ                                                0x7fffffffU
#define CL_TAB__WRITE                                               0x7fffffffU

#endif /* __CL_TAB_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_tab_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_TAB_B0__NUM                    16

/* macros for BlueprintGlobalNameSpace::synth_control */
#ifndef __SYNTH_CONTROL_MACRO__
#define __SYNTH_CONTROL_MACRO__

/* macros for field rfchanFrac */
#define SYNTH_CONTROL__RFCHANFRAC__SHIFT                                      0
#define SYNTH_CONTROL__RFCHANFRAC__WIDTH                                     17
#define SYNTH_CONTROL__RFCHANFRAC__MASK                             0x0001ffffU
#define SYNTH_CONTROL__RFCHANFRAC__READ(src)     (u_int32_t)(src) & 0x0001ffffU
#define SYNTH_CONTROL__RFCHANFRAC__WRITE(src)  ((u_int32_t)(src) & 0x0001ffffU)
#define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((u_int32_t)(src) &\
                    0x0001ffffU)
#define SYNTH_CONTROL__RFCHANFRAC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field rfchannel */
#define SYNTH_CONTROL__RFCHANNEL__SHIFT                                      17
#define SYNTH_CONTROL__RFCHANNEL__WIDTH                                       9
#define SYNTH_CONTROL__RFCHANNEL__MASK                              0x03fe0000U
#define SYNTH_CONTROL__RFCHANNEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03fe0000U) >> 17)
#define SYNTH_CONTROL__RFCHANNEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x03fe0000U)
#define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x03fe0000U)
#define SYNTH_CONTROL__RFCHANNEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x03fe0000U)))

/* macros for field rfAmodeRefSel */
#define SYNTH_CONTROL__RFAMODEREFSEL__SHIFT                                  26
#define SYNTH_CONTROL__RFAMODEREFSEL__WIDTH                                   2
#define SYNTH_CONTROL__RFAMODEREFSEL__MASK                          0x0c000000U
#define SYNTH_CONTROL__RFAMODEREFSEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0c000000U) >> 26)
#define SYNTH_CONTROL__RFAMODEREFSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x0c000000U)
#define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x0c000000U)
#define SYNTH_CONTROL__RFAMODEREFSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x0c000000U)))

/* macros for field rfFracmode */
#define SYNTH_CONTROL__RFFRACMODE__SHIFT                                     28
#define SYNTH_CONTROL__RFFRACMODE__WIDTH                                      1
#define SYNTH_CONTROL__RFFRACMODE__MASK                             0x10000000U
#define SYNTH_CONTROL__RFFRACMODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define SYNTH_CONTROL__RFFRACMODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define SYNTH_CONTROL__RFFRACMODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define SYNTH_CONTROL__RFFRACMODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define SYNTH_CONTROL__RFFRACMODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field rfbmode */
#define SYNTH_CONTROL__RFBMODE__SHIFT                                        29
#define SYNTH_CONTROL__RFBMODE__WIDTH                                         1
#define SYNTH_CONTROL__RFBMODE__MASK                                0x20000000U
#define SYNTH_CONTROL__RFBMODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define SYNTH_CONTROL__RFBMODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define SYNTH_CONTROL__RFBMODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define SYNTH_CONTROL__RFBMODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define SYNTH_CONTROL__RFBMODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field rfsynth_ctrl_sshift */
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SHIFT                            30
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WIDTH                             1
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MASK                    0x40000000U
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)
#define SYNTH_CONTROL__TYPE                                           u_int32_t
#define SYNTH_CONTROL__READ                                         0x7fffffffU
#define SYNTH_CONTROL__WRITE                                        0x7fffffffU

#endif /* __SYNTH_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_synth_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SYNTH_CONTROL__NUM                 1

/* macros for BlueprintGlobalNameSpace::addac_clk_select */
#ifndef __ADDAC_CLK_SELECT_MACRO__
#define __ADDAC_CLK_SELECT_MACRO__

/* macros for field bb_dac_clk_select */
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__SHIFT                            1
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WIDTH                            3
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MASK                   0x0000000eU
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000eU) >> 1)
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000000eU)
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field bb_adc_clk_select */
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__SHIFT                            4
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WIDTH                            4
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MASK                   0x000000f0U
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))
#define ADDAC_CLK_SELECT__TYPE                                        u_int32_t
#define ADDAC_CLK_SELECT__READ                                      0x000000feU
#define ADDAC_CLK_SELECT__WRITE                                     0x000000feU

#endif /* __ADDAC_CLK_SELECT_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_addac_clk_select */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ADDAC_CLK_SELECT__NUM              1

/* macros for BlueprintGlobalNameSpace::pll_cntl */
#ifndef __PLL_CNTL_MACRO__
#define __PLL_CNTL_MACRO__

/* macros for field bb_pll_div */
#define PLL_CNTL__BB_PLL_DIV__SHIFT                                           0
#define PLL_CNTL__BB_PLL_DIV__WIDTH                                          10
#define PLL_CNTL__BB_PLL_DIV__MASK                                  0x000003ffU
#define PLL_CNTL__BB_PLL_DIV__READ(src)          (u_int32_t)(src) & 0x000003ffU
#define PLL_CNTL__BB_PLL_DIV__WRITE(src)       ((u_int32_t)(src) & 0x000003ffU)
#define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PLL_CNTL__BB_PLL_DIV__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field bb_pll_refdiv */
#define PLL_CNTL__BB_PLL_REFDIV__SHIFT                                       10
#define PLL_CNTL__BB_PLL_REFDIV__WIDTH                                        4
#define PLL_CNTL__BB_PLL_REFDIV__MASK                               0x00003c00U
#define PLL_CNTL__BB_PLL_REFDIV__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003c00U) >> 10)
#define PLL_CNTL__BB_PLL_REFDIV__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00003c00U)
#define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00003c00U)
#define PLL_CNTL__BB_PLL_REFDIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00003c00U)))

/* macros for field bb_pll_clk_sel */
#define PLL_CNTL__BB_PLL_CLK_SEL__SHIFT                                      14
#define PLL_CNTL__BB_PLL_CLK_SEL__WIDTH                                       2
#define PLL_CNTL__BB_PLL_CLK_SEL__MASK                              0x0000c000U
#define PLL_CNTL__BB_PLL_CLK_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000c000U) >> 14)
#define PLL_CNTL__BB_PLL_CLK_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0000c000U)
#define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0000c000U)
#define PLL_CNTL__BB_PLL_CLK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field bb_pllbypass */
#define PLL_CNTL__BB_PLLBYPASS__SHIFT                                        16
#define PLL_CNTL__BB_PLLBYPASS__WIDTH                                         1
#define PLL_CNTL__BB_PLLBYPASS__MASK                                0x00010000U
#define PLL_CNTL__BB_PLLBYPASS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define PLL_CNTL__BB_PLLBYPASS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define PLL_CNTL__BB_PLLBYPASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define PLL_CNTL__BB_PLLBYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define PLL_CNTL__BB_PLLBYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field bb_pll_settle_time */
#define PLL_CNTL__BB_PLL_SETTLE_TIME__SHIFT                                  17
#define PLL_CNTL__BB_PLL_SETTLE_TIME__WIDTH                                  11
#define PLL_CNTL__BB_PLL_SETTLE_TIME__MASK                          0x0ffe0000U
#define PLL_CNTL__BB_PLL_SETTLE_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0ffe0000U) >> 17)
#define PLL_CNTL__BB_PLL_SETTLE_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x0ffe0000U)
#define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0ffe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x0ffe0000U)
#define PLL_CNTL__BB_PLL_SETTLE_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x0ffe0000U)))
#define PLL_CNTL__TYPE                                                u_int32_t
#define PLL_CNTL__READ                                              0x0fffffffU
#define PLL_CNTL__WRITE                                             0x0fffffffU

#endif /* __PLL_CNTL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_pll_cntl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PLL_CNTL__NUM                      1

/* macros for BlueprintGlobalNameSpace::analog_swap */
#ifndef __ANALOG_SWAP_MACRO__
#define __ANALOG_SWAP_MACRO__

/* macros for field analog_rx_swap_cntl */
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__SHIFT                               0
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WIDTH                               3
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MASK                      0x00000007U
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field analog_tx_swap_cntl */
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__SHIFT                               3
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WIDTH                               3
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MASK                      0x00000038U
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000038U) >> 3)
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000038U)
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000038U) | (((u_int32_t)(src) <<\
                    3) & 0x00000038U)
#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000038U)))

/* macros for field swap_alt_chn */
#define ANALOG_SWAP__SWAP_ALT_CHN__SHIFT                                      6
#define ANALOG_SWAP__SWAP_ALT_CHN__WIDTH                                      1
#define ANALOG_SWAP__SWAP_ALT_CHN__MASK                             0x00000040U
#define ANALOG_SWAP__SWAP_ALT_CHN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define ANALOG_SWAP__SWAP_ALT_CHN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define ANALOG_SWAP__SWAP_ALT_CHN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define ANALOG_SWAP__SWAP_ALT_CHN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define ANALOG_SWAP__SWAP_ALT_CHN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field analog_dc_dac_polarity */
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SHIFT                            7
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WIDTH                            1
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MASK                   0x00000080U
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field analog_pkdet_dac_polarity */
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SHIFT                         8
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WIDTH                         1
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MASK                0x00000100U
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)
#define ANALOG_SWAP__TYPE                                             u_int32_t
#define ANALOG_SWAP__READ                                           0x000001ffU
#define ANALOG_SWAP__WRITE                                          0x000001ffU

#endif /* __ANALOG_SWAP_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_analog_swap */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ANALOG_SWAP__NUM                   1

/* macros for BlueprintGlobalNameSpace::addac_parallel_control */
#ifndef __ADDAC_PARALLEL_CONTROL_MACRO__
#define __ADDAC_PARALLEL_CONTROL_MACRO__

/* macros for field off_daclpmode */
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SHIFT                         12
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WIDTH                          1
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MASK                 0x00001000U
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field off_pwdDac */
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SHIFT                            13
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WIDTH                             1
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MASK                    0x00002000U
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field off_pwdAdc */
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SHIFT                            15
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WIDTH                             1
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MASK                    0x00008000U
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field on_daclpmode */
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SHIFT                          28
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WIDTH                           1
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MASK                  0x10000000U
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field on_pwdDac */
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SHIFT                             29
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WIDTH                              1
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MASK                     0x20000000U
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field on_pwdAdc */
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SHIFT                             31
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WIDTH                              1
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MASK                     0x80000000U
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define ADDAC_PARALLEL_CONTROL__TYPE                                  u_int32_t
#define ADDAC_PARALLEL_CONTROL__READ                                0xb000b000U
#define ADDAC_PARALLEL_CONTROL__WRITE                               0xb000b000U

#endif /* __ADDAC_PARALLEL_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_addac_parallel_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ADDAC_PARALLEL_CONTROL__NUM        1

/* macros for BlueprintGlobalNameSpace::force_analog */
#ifndef __FORCE_ANALOG_MACRO__
#define __FORCE_ANALOG_MACRO__

/* macros for field force_xpaon */
#define FORCE_ANALOG__FORCE_XPAON__SHIFT                                      0
#define FORCE_ANALOG__FORCE_XPAON__WIDTH                                      1
#define FORCE_ANALOG__FORCE_XPAON__MASK                             0x00000001U
#define FORCE_ANALOG__FORCE_XPAON__READ(src)     (u_int32_t)(src) & 0x00000001U
#define FORCE_ANALOG__FORCE_XPAON__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
#define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define FORCE_ANALOG__FORCE_XPAON__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define FORCE_ANALOG__FORCE_XPAON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define FORCE_ANALOG__FORCE_XPAON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field forced_xpaon */
#define FORCE_ANALOG__FORCED_XPAON__SHIFT                                     1
#define FORCE_ANALOG__FORCED_XPAON__WIDTH                                     3
#define FORCE_ANALOG__FORCED_XPAON__MASK                            0x0000000eU
#define FORCE_ANALOG__FORCED_XPAON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000eU) >> 1)
#define FORCE_ANALOG__FORCED_XPAON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000000eU)
#define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define FORCE_ANALOG__FORCED_XPAON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field force_pdadc_pwd */
#define FORCE_ANALOG__FORCE_PDADC_PWD__SHIFT                                  4
#define FORCE_ANALOG__FORCE_PDADC_PWD__WIDTH                                  1
#define FORCE_ANALOG__FORCE_PDADC_PWD__MASK                         0x00000010U
#define FORCE_ANALOG__FORCE_PDADC_PWD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define FORCE_ANALOG__FORCE_PDADC_PWD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define FORCE_ANALOG__FORCE_PDADC_PWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define FORCE_ANALOG__FORCE_PDADC_PWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define FORCE_ANALOG__FORCE_PDADC_PWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field forced_pdadc_pwd */
#define FORCE_ANALOG__FORCED_PDADC_PWD__SHIFT                                 5
#define FORCE_ANALOG__FORCED_PDADC_PWD__WIDTH                                 3
#define FORCE_ANALOG__FORCED_PDADC_PWD__MASK                        0x000000e0U
#define FORCE_ANALOG__FORCED_PDADC_PWD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000e0U) >> 5)
#define FORCE_ANALOG__FORCED_PDADC_PWD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000000e0U)
#define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define FORCE_ANALOG__FORCED_PDADC_PWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))
#define FORCE_ANALOG__TYPE                                            u_int32_t
#define FORCE_ANALOG__READ                                          0x000000ffU
#define FORCE_ANALOG__WRITE                                         0x000000ffU

#endif /* __FORCE_ANALOG_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_force_analog */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FORCE_ANALOG__NUM                  1

/* macros for BlueprintGlobalNameSpace::test_controls */
#ifndef __TEST_CONTROLS_MACRO__
#define __TEST_CONTROLS_MACRO__

/* macros for field cf_tsttrig_sel */
#define TEST_CONTROLS__CF_TSTTRIG_SEL__SHIFT                                  0
#define TEST_CONTROLS__CF_TSTTRIG_SEL__WIDTH                                  4
#define TEST_CONTROLS__CF_TSTTRIG_SEL__MASK                         0x0000000fU
#define TEST_CONTROLS__CF_TSTTRIG_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU
#define TEST_CONTROLS__CF_TSTTRIG_SEL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define TEST_CONTROLS__CF_TSTTRIG_SEL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field cf_tsttrig */
#define TEST_CONTROLS__CF_TSTTRIG__SHIFT                                      4
#define TEST_CONTROLS__CF_TSTTRIG__WIDTH                                      1
#define TEST_CONTROLS__CF_TSTTRIG__MASK                             0x00000010U
#define TEST_CONTROLS__CF_TSTTRIG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define TEST_CONTROLS__CF_TSTTRIG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define TEST_CONTROLS__CF_TSTTRIG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define TEST_CONTROLS__CF_TSTTRIG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define TEST_CONTROLS__CF_TSTTRIG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field cf_rfshift_sel */
#define TEST_CONTROLS__CF_RFSHIFT_SEL__SHIFT                                  5
#define TEST_CONTROLS__CF_RFSHIFT_SEL__WIDTH                                  2
#define TEST_CONTROLS__CF_RFSHIFT_SEL__MASK                         0x00000060U
#define TEST_CONTROLS__CF_RFSHIFT_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000060U) >> 5)
#define TEST_CONTROLS__CF_RFSHIFT_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000060U)
#define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000060U) | (((u_int32_t)(src) <<\
                    5) & 0x00000060U)
#define TEST_CONTROLS__CF_RFSHIFT_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000060U)))

/* macros for field cardbus_mode */
#define TEST_CONTROLS__CARDBUS_MODE__SHIFT                                    8
#define TEST_CONTROLS__CARDBUS_MODE__WIDTH                                    2
#define TEST_CONTROLS__CARDBUS_MODE__MASK                           0x00000300U
#define TEST_CONTROLS__CARDBUS_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define TEST_CONTROLS__CARDBUS_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define TEST_CONTROLS__CARDBUS_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field clkout_is_clk32 */
#define TEST_CONTROLS__CLKOUT_IS_CLK32__SHIFT                                10
#define TEST_CONTROLS__CLKOUT_IS_CLK32__WIDTH                                 1
#define TEST_CONTROLS__CLKOUT_IS_CLK32__MASK                        0x00000400U
#define TEST_CONTROLS__CLKOUT_IS_CLK32__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define TEST_CONTROLS__CLKOUT_IS_CLK32__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define TEST_CONTROLS__CLKOUT_IS_CLK32__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define TEST_CONTROLS__CLKOUT_IS_CLK32__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define TEST_CONTROLS__CLKOUT_IS_CLK32__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field enable_rfsilent_bb */
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SHIFT                             13
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WIDTH                              1
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MASK                     0x00002000U
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TEST_CONTROLS__ENABLE_RFSILENT_BB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field enable_mini_obs */
#define TEST_CONTROLS__ENABLE_MINI_OBS__SHIFT                                15
#define TEST_CONTROLS__ENABLE_MINI_OBS__WIDTH                                 1
#define TEST_CONTROLS__ENABLE_MINI_OBS__MASK                        0x00008000U
#define TEST_CONTROLS__ENABLE_MINI_OBS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TEST_CONTROLS__ENABLE_MINI_OBS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TEST_CONTROLS__ENABLE_MINI_OBS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TEST_CONTROLS__ENABLE_MINI_OBS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TEST_CONTROLS__ENABLE_MINI_OBS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field slow_clk160 */
#define TEST_CONTROLS__SLOW_CLK160__SHIFT                                    17
#define TEST_CONTROLS__SLOW_CLK160__WIDTH                                     1
#define TEST_CONTROLS__SLOW_CLK160__MASK                            0x00020000U
#define TEST_CONTROLS__SLOW_CLK160__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define TEST_CONTROLS__SLOW_CLK160__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define TEST_CONTROLS__SLOW_CLK160__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define TEST_CONTROLS__SLOW_CLK160__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define TEST_CONTROLS__SLOW_CLK160__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field agc_obs_sel_3 */
#define TEST_CONTROLS__AGC_OBS_SEL_3__SHIFT                                  18
#define TEST_CONTROLS__AGC_OBS_SEL_3__WIDTH                                   1
#define TEST_CONTROLS__AGC_OBS_SEL_3__MASK                          0x00040000U
#define TEST_CONTROLS__AGC_OBS_SEL_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define TEST_CONTROLS__AGC_OBS_SEL_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define TEST_CONTROLS__AGC_OBS_SEL_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define TEST_CONTROLS__AGC_OBS_SEL_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define TEST_CONTROLS__AGC_OBS_SEL_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field cf_bbb_obs_sel */
#define TEST_CONTROLS__CF_BBB_OBS_SEL__SHIFT                                 19
#define TEST_CONTROLS__CF_BBB_OBS_SEL__WIDTH                                  4
#define TEST_CONTROLS__CF_BBB_OBS_SEL__MASK                         0x00780000U
#define TEST_CONTROLS__CF_BBB_OBS_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00780000U) >> 19)
#define TEST_CONTROLS__CF_BBB_OBS_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00780000U)
#define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00780000U) | (((u_int32_t)(src) <<\
                    19) & 0x00780000U)
#define TEST_CONTROLS__CF_BBB_OBS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00780000U)))

/* macros for field rx_obs_sel_5th_bit */
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SHIFT                             23
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WIDTH                              1
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MASK                     0x00800000U
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field agc_obs_sel_4 */
#define TEST_CONTROLS__AGC_OBS_SEL_4__SHIFT                                  24
#define TEST_CONTROLS__AGC_OBS_SEL_4__WIDTH                                   1
#define TEST_CONTROLS__AGC_OBS_SEL_4__MASK                          0x01000000U
#define TEST_CONTROLS__AGC_OBS_SEL_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define TEST_CONTROLS__AGC_OBS_SEL_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TEST_CONTROLS__AGC_OBS_SEL_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TEST_CONTROLS__AGC_OBS_SEL_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TEST_CONTROLS__AGC_OBS_SEL_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field force_agc_clear */
#define TEST_CONTROLS__FORCE_AGC_CLEAR__SHIFT                                28
#define TEST_CONTROLS__FORCE_AGC_CLEAR__WIDTH                                 1
#define TEST_CONTROLS__FORCE_AGC_CLEAR__MASK                        0x10000000U
#define TEST_CONTROLS__FORCE_AGC_CLEAR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define TEST_CONTROLS__FORCE_AGC_CLEAR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TEST_CONTROLS__FORCE_AGC_CLEAR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TEST_CONTROLS__FORCE_AGC_CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TEST_CONTROLS__FORCE_AGC_CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field tstdac_out_sel */
#define TEST_CONTROLS__TSTDAC_OUT_SEL__SHIFT                                 30
#define TEST_CONTROLS__TSTDAC_OUT_SEL__WIDTH                                  2
#define TEST_CONTROLS__TSTDAC_OUT_SEL__MASK                         0xc0000000U
#define TEST_CONTROLS__TSTDAC_OUT_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define TEST_CONTROLS__TSTDAC_OUT_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define TEST_CONTROLS__TSTDAC_OUT_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define TEST_CONTROLS__TYPE                                           u_int32_t
#define TEST_CONTROLS__READ                                         0xd1fea77fU
#define TEST_CONTROLS__WRITE                                        0xd1fea77fU

#endif /* __TEST_CONTROLS_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_test_controls */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TEST_CONTROLS__NUM                 1

/* macros for BlueprintGlobalNameSpace::test_controls_status */
#ifndef __TEST_CONTROLS_STATUS_MACRO__
#define __TEST_CONTROLS_STATUS_MACRO__

/* macros for field cf_tstdac_en */
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SHIFT                             0
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WIDTH                             1
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MASK                    0x00000001U
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cf_tx_src_is_tstdac */
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SHIFT                      1
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WIDTH                      1
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MASK             0x00000002U
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field cf_tx_obs_sel */
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__SHIFT                            2
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WIDTH                            3
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MASK                   0x0000001cU
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))

/* macros for field cf_tx_obs_mux_sel */
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__SHIFT                        5
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WIDTH                        2
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MASK               0x00000060U
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000060U) >> 5)
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000060U)
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000060U) | (((u_int32_t)(src) <<\
                    5) & 0x00000060U)
#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000060U)))

/* macros for field cf_tx_src_alternate */
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SHIFT                      7
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WIDTH                      1
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MASK             0x00000080U
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field cf_tstadc_en */
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SHIFT                             8
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WIDTH                             1
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MASK                    0x00000100U
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field cf_rx_src_is_tstadc */
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SHIFT                      9
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WIDTH                      1
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MASK             0x00000200U
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field rx_obs_sel */
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__SHIFT                              10
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WIDTH                               4
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MASK                      0x00003c00U
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003c00U) >> 10)
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00003c00U)
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00003c00U)
#define TEST_CONTROLS_STATUS__RX_OBS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00003c00U)))

/* macros for field disable_a2_warm_reset */
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SHIFT                   14
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WIDTH                    1
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MASK           0x00004000U
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field reset_a2 */
#define TEST_CONTROLS_STATUS__RESET_A2__SHIFT                                15
#define TEST_CONTROLS_STATUS__RESET_A2__WIDTH                                 1
#define TEST_CONTROLS_STATUS__RESET_A2__MASK                        0x00008000U
#define TEST_CONTROLS_STATUS__RESET_A2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TEST_CONTROLS_STATUS__RESET_A2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TEST_CONTROLS_STATUS__RESET_A2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TEST_CONTROLS_STATUS__RESET_A2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TEST_CONTROLS_STATUS__RESET_A2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field agc_obs_sel */
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__SHIFT                             16
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WIDTH                              3
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MASK                     0x00070000U
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00070000U) >> 16)
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00070000U)
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((u_int32_t)(src) <<\
                    16) & 0x00070000U)
#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field cf_enable_fft_dump */
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SHIFT                      19
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WIDTH                       1
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MASK              0x00080000U
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field cf_debugport_in */
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SHIFT                         23
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WIDTH                          1
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MASK                 0x00800000U
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field disable_agc_to_a2 */
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SHIFT                       27
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WIDTH                        1
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MASK               0x08000000U
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field cf_debugport_en */
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SHIFT                         28
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WIDTH                          1
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MASK                 0x10000000U
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field cf_debugport_sel */
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__SHIFT                        29
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WIDTH                         3
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MASK                0xe0000000U
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xe0000000U) >> 29)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0xe0000000U)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define TEST_CONTROLS_STATUS__TYPE                                    u_int32_t
#define TEST_CONTROLS_STATUS__READ                                  0xf88fffffU
#define TEST_CONTROLS_STATUS__WRITE                                 0xf88fffffU

#endif /* __TEST_CONTROLS_STATUS_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_test_controls_status */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TEST_CONTROLS_STATUS__NUM          1

/* macros for BlueprintGlobalNameSpace::tstdac */
#ifndef __TSTDAC_MACRO__
#define __TSTDAC_MACRO__

/* macros for field tstdac_out_q */
#define TSTDAC__TSTDAC_OUT_Q__SHIFT                                           0
#define TSTDAC__TSTDAC_OUT_Q__WIDTH                                          10
#define TSTDAC__TSTDAC_OUT_Q__MASK                                  0x000003ffU
#define TSTDAC__TSTDAC_OUT_Q__READ(src)          (u_int32_t)(src) & 0x000003ffU

/* macros for field tstdac_out_i */
#define TSTDAC__TSTDAC_OUT_I__SHIFT                                          10
#define TSTDAC__TSTDAC_OUT_I__WIDTH                                          10
#define TSTDAC__TSTDAC_OUT_I__MASK                                  0x000ffc00U
#define TSTDAC__TSTDAC_OUT_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define TSTDAC__TYPE                                                  u_int32_t
#define TSTDAC__READ                                                0x000fffffU

#endif /* __TSTDAC_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tstdac */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TSTDAC__NUM                        1

/* macros for BlueprintGlobalNameSpace::channel_status */
#ifndef __CHANNEL_STATUS_MACRO__
#define __CHANNEL_STATUS_MACRO__

/* macros for field bt_active */
#define CHANNEL_STATUS__BT_ACTIVE__SHIFT                                      0
#define CHANNEL_STATUS__BT_ACTIVE__WIDTH                                      1
#define CHANNEL_STATUS__BT_ACTIVE__MASK                             0x00000001U
#define CHANNEL_STATUS__BT_ACTIVE__READ(src)     (u_int32_t)(src) & 0x00000001U
#define CHANNEL_STATUS__BT_ACTIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define CHANNEL_STATUS__BT_ACTIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field rx_clear_raw */
#define CHANNEL_STATUS__RX_CLEAR_RAW__SHIFT                                   1
#define CHANNEL_STATUS__RX_CLEAR_RAW__WIDTH                                   1
#define CHANNEL_STATUS__RX_CLEAR_RAW__MASK                          0x00000002U
#define CHANNEL_STATUS__RX_CLEAR_RAW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define CHANNEL_STATUS__RX_CLEAR_RAW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define CHANNEL_STATUS__RX_CLEAR_RAW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field rx_clear_mac */
#define CHANNEL_STATUS__RX_CLEAR_MAC__SHIFT                                   2
#define CHANNEL_STATUS__RX_CLEAR_MAC__WIDTH                                   1
#define CHANNEL_STATUS__RX_CLEAR_MAC__MASK                          0x00000004U
#define CHANNEL_STATUS__RX_CLEAR_MAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define CHANNEL_STATUS__RX_CLEAR_MAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define CHANNEL_STATUS__RX_CLEAR_MAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field rx_clear_pad */
#define CHANNEL_STATUS__RX_CLEAR_PAD__SHIFT                                   3
#define CHANNEL_STATUS__RX_CLEAR_PAD__WIDTH                                   1
#define CHANNEL_STATUS__RX_CLEAR_PAD__MASK                          0x00000008U
#define CHANNEL_STATUS__RX_CLEAR_PAD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define CHANNEL_STATUS__RX_CLEAR_PAD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define CHANNEL_STATUS__RX_CLEAR_PAD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field bb_sw_out_0 */
#define CHANNEL_STATUS__BB_SW_OUT_0__SHIFT                                    4
#define CHANNEL_STATUS__BB_SW_OUT_0__WIDTH                                    2
#define CHANNEL_STATUS__BB_SW_OUT_0__MASK                           0x00000030U
#define CHANNEL_STATUS__BB_SW_OUT_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)

/* macros for field bb_sw_out_1 */
#define CHANNEL_STATUS__BB_SW_OUT_1__SHIFT                                    6
#define CHANNEL_STATUS__BB_SW_OUT_1__WIDTH                                    2
#define CHANNEL_STATUS__BB_SW_OUT_1__MASK                           0x000000c0U
#define CHANNEL_STATUS__BB_SW_OUT_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)

/* macros for field bb_sw_out_2 */
#define CHANNEL_STATUS__BB_SW_OUT_2__SHIFT                                    8
#define CHANNEL_STATUS__BB_SW_OUT_2__WIDTH                                    2
#define CHANNEL_STATUS__BB_SW_OUT_2__MASK                           0x00000300U
#define CHANNEL_STATUS__BB_SW_OUT_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)

/* macros for field bb_sw_com_out */
#define CHANNEL_STATUS__BB_SW_COM_OUT__SHIFT                                 10
#define CHANNEL_STATUS__BB_SW_COM_OUT__WIDTH                                  4
#define CHANNEL_STATUS__BB_SW_COM_OUT__MASK                         0x00003c00U
#define CHANNEL_STATUS__BB_SW_COM_OUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003c00U) >> 10)

/* macros for field ant_div_cfg_used */
#define CHANNEL_STATUS__ANT_DIV_CFG_USED__SHIFT                              14
#define CHANNEL_STATUS__ANT_DIV_CFG_USED__WIDTH                               3
#define CHANNEL_STATUS__ANT_DIV_CFG_USED__MASK                      0x0001c000U
#define CHANNEL_STATUS__ANT_DIV_CFG_USED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001c000U) >> 14)
#define CHANNEL_STATUS__TYPE                                          u_int32_t
#define CHANNEL_STATUS__READ                                        0x0001ffffU

#endif /* __CHANNEL_STATUS_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_channel_status */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHANNEL_STATUS__NUM                1

/* macros for BlueprintGlobalNameSpace::chaninfo_ctrl */
#ifndef __CHANINFO_CTRL_MACRO__
#define __CHANINFO_CTRL_MACRO__

/* macros for field capture_chan_info */
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SHIFT                               0
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WIDTH                               1
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MASK                      0x00000001U
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field disable_chaninfomem */
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SHIFT                             1
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WIDTH                             1
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MASK                    0x00000002U
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field capture_sounding_packet */
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SHIFT                         2
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WIDTH                         1
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MASK                0x00000004U
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field chaninfomem_s2_read */
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SHIFT                             3
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WIDTH                             1
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MASK                    0x00000008U
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)
#define CHANINFO_CTRL__TYPE                                           u_int32_t
#define CHANINFO_CTRL__READ                                         0x0000000fU
#define CHANINFO_CTRL__WRITE                                        0x0000000fU

#endif /* __CHANINFO_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_chaninfo_ctrl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHANINFO_CTRL__NUM                 1

/* macros for BlueprintGlobalNameSpace::chan_info_noise_pwr */
#ifndef __CHAN_INFO_NOISE_PWR_MACRO__
#define __CHAN_INFO_NOISE_PWR_MACRO__

/* macros for field noise_power */
#define CHAN_INFO_NOISE_PWR__NOISE_POWER__SHIFT                               0
#define CHAN_INFO_NOISE_PWR__NOISE_POWER__WIDTH                              12
#define CHAN_INFO_NOISE_PWR__NOISE_POWER__MASK                      0x00000fffU
#define CHAN_INFO_NOISE_PWR__NOISE_POWER__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU
#define CHAN_INFO_NOISE_PWR__TYPE                                     u_int32_t
#define CHAN_INFO_NOISE_PWR__READ                                   0x00000fffU

#endif /* __CHAN_INFO_NOISE_PWR_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_noise_pwr */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_NOISE_PWR__NUM           1

/* macros for BlueprintGlobalNameSpace::chan_info_gain_diff */
#ifndef __CHAN_INFO_GAIN_DIFF_MACRO__
#define __CHAN_INFO_GAIN_DIFF_MACRO__

/* macros for field fine_ppm */
#define CHAN_INFO_GAIN_DIFF__FINE_PPM__SHIFT                                  0
#define CHAN_INFO_GAIN_DIFF__FINE_PPM__WIDTH                                 12
#define CHAN_INFO_GAIN_DIFF__FINE_PPM__MASK                         0x00000fffU
#define CHAN_INFO_GAIN_DIFF__FINE_PPM__READ(src) (u_int32_t)(src) & 0x00000fffU

/* macros for field analog_gain_diff_01 */
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__SHIFT                      12
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__WIDTH                       7
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__MASK              0x0007f000U
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0007f000U) >> 12)

/* macros for field analog_gain_diff_02 */
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__SHIFT                      19
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__WIDTH                       7
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__MASK              0x03f80000U
#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03f80000U) >> 19)
#define CHAN_INFO_GAIN_DIFF__TYPE                                     u_int32_t
#define CHAN_INFO_GAIN_DIFF__READ                                   0x03ffffffU

#endif /* __CHAN_INFO_GAIN_DIFF_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_gain_diff */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_DIFF__NUM           1

/* macros for BlueprintGlobalNameSpace::chan_info_fine_timing */
#ifndef __CHAN_INFO_FINE_TIMING_MACRO__
#define __CHAN_INFO_FINE_TIMING_MACRO__

/* macros for field coarse_ppm */
#define CHAN_INFO_FINE_TIMING__COARSE_PPM__SHIFT                              0
#define CHAN_INFO_FINE_TIMING__COARSE_PPM__WIDTH                             12
#define CHAN_INFO_FINE_TIMING__COARSE_PPM__MASK                     0x00000fffU
#define CHAN_INFO_FINE_TIMING__COARSE_PPM__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU

/* macros for field fine_timing */
#define CHAN_INFO_FINE_TIMING__FINE_TIMING__SHIFT                            12
#define CHAN_INFO_FINE_TIMING__FINE_TIMING__WIDTH                            10
#define CHAN_INFO_FINE_TIMING__FINE_TIMING__MASK                    0x003ff000U
#define CHAN_INFO_FINE_TIMING__FINE_TIMING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003ff000U) >> 12)
#define CHAN_INFO_FINE_TIMING__TYPE                                   u_int32_t
#define CHAN_INFO_FINE_TIMING__READ                                 0x003fffffU

#endif /* __CHAN_INFO_FINE_TIMING_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_fine_timing */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_FINE_TIMING__NUM         1

/* macros for BlueprintGlobalNameSpace::chan_info_gain_b0 */
#ifndef __CHAN_INFO_GAIN_B0_MACRO__
#define __CHAN_INFO_GAIN_B0_MACRO__

/* macros for field chan_info_rssi_0 */
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__SHIFT                            0
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__WIDTH                            8
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__MASK                   0x000000ffU
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU

/* macros for field chan_info_rf_gain_0 */
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__SHIFT                         8
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__WIDTH                         8
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__MASK                0x0000ff00U
#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field chan_info_mb_gain_0 */
#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__SHIFT                        16
#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__WIDTH                         7
#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__MASK                0x007f0000U
#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)

/* macros for field chan_info_xatten1_sw_0 */
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SHIFT                     23
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__WIDTH                      1
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__MASK             0x00800000U
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field chan_info_xatten2_sw_0 */
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SHIFT                     24
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__WIDTH                      1
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__MASK             0x01000000U
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define CHAN_INFO_GAIN_B0__TYPE                                       u_int32_t
#define CHAN_INFO_GAIN_B0__READ                                     0x01ffffffU

#endif /* __CHAN_INFO_GAIN_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_gain_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::scrambler_seed */
#ifndef __SCRAMBLER_SEED_MACRO__
#define __SCRAMBLER_SEED_MACRO__

/* macros for field fixed_scrambler_seed */
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__SHIFT                           0
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WIDTH                           7
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MASK                  0x0000007fU
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))
#define SCRAMBLER_SEED__TYPE                                          u_int32_t
#define SCRAMBLER_SEED__READ                                        0x0000007fU
#define SCRAMBLER_SEED__WRITE                                       0x0000007fU

#endif /* __SCRAMBLER_SEED_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_scrambler_seed */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SCRAMBLER_SEED__NUM                1

/* macros for BlueprintGlobalNameSpace::bbb_tx_ctrl */
#ifndef __BBB_TX_CTRL_MACRO__
#define __BBB_TX_CTRL_MACRO__

/* macros for field disable_scrambler */
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SHIFT                                 0
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WIDTH                                 1
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MASK                        0x00000001U
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define BBB_TX_CTRL__DISABLE_SCRAMBLER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field use_scrambler_seed */
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SHIFT                                1
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WIDTH                                1
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MASK                       0x00000002U
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field tx_dac_scale_cck */
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__SHIFT                                  2
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WIDTH                                  2
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MASK                         0x0000000cU
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field txfir_japan_cck */
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SHIFT                                   4
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WIDTH                                   1
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MASK                          0x00000010U
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field allow_1mbps_short */
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SHIFT                                 5
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WIDTH                                 1
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MASK                        0x00000020U
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field tx_cck_delay_1 */
#define BBB_TX_CTRL__TX_CCK_DELAY_1__SHIFT                                    6
#define BBB_TX_CTRL__TX_CCK_DELAY_1__WIDTH                                    3
#define BBB_TX_CTRL__TX_CCK_DELAY_1__MASK                           0x000001c0U
#define BBB_TX_CTRL__TX_CCK_DELAY_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001c0U) >> 6)
#define BBB_TX_CTRL__TX_CCK_DELAY_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000001c0U)
#define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000001c0U)
#define BBB_TX_CTRL__TX_CCK_DELAY_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000001c0U)))

/* macros for field tx_cck_delay_2 */
#define BBB_TX_CTRL__TX_CCK_DELAY_2__SHIFT                                    9
#define BBB_TX_CTRL__TX_CCK_DELAY_2__WIDTH                                    3
#define BBB_TX_CTRL__TX_CCK_DELAY_2__MASK                           0x00000e00U
#define BBB_TX_CTRL__TX_CCK_DELAY_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000e00U) >> 9)
#define BBB_TX_CTRL__TX_CCK_DELAY_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000e00U)
#define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define BBB_TX_CTRL__TX_CCK_DELAY_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))
#define BBB_TX_CTRL__TYPE                                             u_int32_t
#define BBB_TX_CTRL__READ                                           0x00000fffU
#define BBB_TX_CTRL__WRITE                                          0x00000fffU

#endif /* __BBB_TX_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_tx_ctrl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TX_CTRL__NUM                   1

/* macros for BlueprintGlobalNameSpace::bbb_txfir_0 */
#ifndef __BBB_TXFIR_0_MACRO__
#define __BBB_TXFIR_0_MACRO__

/* macros for field txfir_coeff_h0 */
#define BBB_TXFIR_0__TXFIR_COEFF_H0__SHIFT                                    0
#define BBB_TXFIR_0__TXFIR_COEFF_H0__WIDTH                                    4
#define BBB_TXFIR_0__TXFIR_COEFF_H0__MASK                           0x0000000fU
#define BBB_TXFIR_0__TXFIR_COEFF_H0__READ(src)   (u_int32_t)(src) & 0x0000000fU
#define BBB_TXFIR_0__TXFIR_COEFF_H0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define BBB_TXFIR_0__TXFIR_COEFF_H0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field txfir_coeff_h1 */
#define BBB_TXFIR_0__TXFIR_COEFF_H1__SHIFT                                    8
#define BBB_TXFIR_0__TXFIR_COEFF_H1__WIDTH                                    4
#define BBB_TXFIR_0__TXFIR_COEFF_H1__MASK                           0x00000f00U
#define BBB_TXFIR_0__TXFIR_COEFF_H1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define BBB_TXFIR_0__TXFIR_COEFF_H1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define BBB_TXFIR_0__TXFIR_COEFF_H1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field txfir_coeff_h2 */
#define BBB_TXFIR_0__TXFIR_COEFF_H2__SHIFT                                   16
#define BBB_TXFIR_0__TXFIR_COEFF_H2__WIDTH                                    5
#define BBB_TXFIR_0__TXFIR_COEFF_H2__MASK                           0x001f0000U
#define BBB_TXFIR_0__TXFIR_COEFF_H2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)
#define BBB_TXFIR_0__TXFIR_COEFF_H2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x001f0000U)
#define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x001f0000U)
#define BBB_TXFIR_0__TXFIR_COEFF_H2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x001f0000U)))

/* macros for field txfir_coeff_h3 */
#define BBB_TXFIR_0__TXFIR_COEFF_H3__SHIFT                                   24
#define BBB_TXFIR_0__TXFIR_COEFF_H3__WIDTH                                    5
#define BBB_TXFIR_0__TXFIR_COEFF_H3__MASK                           0x1f000000U
#define BBB_TXFIR_0__TXFIR_COEFF_H3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f000000U) >> 24)
#define BBB_TXFIR_0__TXFIR_COEFF_H3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x1f000000U)
#define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x1f000000U)
#define BBB_TXFIR_0__TXFIR_COEFF_H3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x1f000000U)))
#define BBB_TXFIR_0__TYPE                                             u_int32_t
#define BBB_TXFIR_0__READ                                           0x1f1f0f0fU
#define BBB_TXFIR_0__WRITE                                          0x1f1f0f0fU

#endif /* __BBB_TXFIR_0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_0__NUM                   1

/* macros for BlueprintGlobalNameSpace::bbb_txfir_1 */
#ifndef __BBB_TXFIR_1_MACRO__
#define __BBB_TXFIR_1_MACRO__

/* macros for field txfir_coeff_h4 */
#define BBB_TXFIR_1__TXFIR_COEFF_H4__SHIFT                                    0
#define BBB_TXFIR_1__TXFIR_COEFF_H4__WIDTH                                    6
#define BBB_TXFIR_1__TXFIR_COEFF_H4__MASK                           0x0000003fU
#define BBB_TXFIR_1__TXFIR_COEFF_H4__READ(src)   (u_int32_t)(src) & 0x0000003fU
#define BBB_TXFIR_1__TXFIR_COEFF_H4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define BBB_TXFIR_1__TXFIR_COEFF_H4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field txfir_coeff_h5 */
#define BBB_TXFIR_1__TXFIR_COEFF_H5__SHIFT                                    8
#define BBB_TXFIR_1__TXFIR_COEFF_H5__WIDTH                                    6
#define BBB_TXFIR_1__TXFIR_COEFF_H5__MASK                           0x00003f00U
#define BBB_TXFIR_1__TXFIR_COEFF_H5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define BBB_TXFIR_1__TXFIR_COEFF_H5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define BBB_TXFIR_1__TXFIR_COEFF_H5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field txfir_coeff_h6 */
#define BBB_TXFIR_1__TXFIR_COEFF_H6__SHIFT                                   16
#define BBB_TXFIR_1__TXFIR_COEFF_H6__WIDTH                                    7
#define BBB_TXFIR_1__TXFIR_COEFF_H6__MASK                           0x007f0000U
#define BBB_TXFIR_1__TXFIR_COEFF_H6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)
#define BBB_TXFIR_1__TXFIR_COEFF_H6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x007f0000U)
#define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x007f0000U)
#define BBB_TXFIR_1__TXFIR_COEFF_H6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x007f0000U)))

/* macros for field txfir_coeff_h7 */
#define BBB_TXFIR_1__TXFIR_COEFF_H7__SHIFT                                   24
#define BBB_TXFIR_1__TXFIR_COEFF_H7__WIDTH                                    7
#define BBB_TXFIR_1__TXFIR_COEFF_H7__MASK                           0x7f000000U
#define BBB_TXFIR_1__TXFIR_COEFF_H7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7f000000U) >> 24)
#define BBB_TXFIR_1__TXFIR_COEFF_H7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x7f000000U)
#define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define BBB_TXFIR_1__TXFIR_COEFF_H7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))
#define BBB_TXFIR_1__TYPE                                             u_int32_t
#define BBB_TXFIR_1__READ                                           0x7f7f3f3fU
#define BBB_TXFIR_1__WRITE                                          0x7f7f3f3fU

#endif /* __BBB_TXFIR_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_1__NUM                   1

/* macros for BlueprintGlobalNameSpace::bbb_txfir_2 */
#ifndef __BBB_TXFIR_2_MACRO__
#define __BBB_TXFIR_2_MACRO__

/* macros for field txfir_coeff_h8 */
#define BBB_TXFIR_2__TXFIR_COEFF_H8__SHIFT                                    0
#define BBB_TXFIR_2__TXFIR_COEFF_H8__WIDTH                                    8
#define BBB_TXFIR_2__TXFIR_COEFF_H8__MASK                           0x000000ffU
#define BBB_TXFIR_2__TXFIR_COEFF_H8__READ(src)   (u_int32_t)(src) & 0x000000ffU
#define BBB_TXFIR_2__TXFIR_COEFF_H8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define BBB_TXFIR_2__TXFIR_COEFF_H8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txfir_coeff_h9 */
#define BBB_TXFIR_2__TXFIR_COEFF_H9__SHIFT                                    8
#define BBB_TXFIR_2__TXFIR_COEFF_H9__WIDTH                                    8
#define BBB_TXFIR_2__TXFIR_COEFF_H9__MASK                           0x0000ff00U
#define BBB_TXFIR_2__TXFIR_COEFF_H9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define BBB_TXFIR_2__TXFIR_COEFF_H9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define BBB_TXFIR_2__TXFIR_COEFF_H9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txfir_coeff_h10 */
#define BBB_TXFIR_2__TXFIR_COEFF_H10__SHIFT                                  16
#define BBB_TXFIR_2__TXFIR_COEFF_H10__WIDTH                                   8
#define BBB_TXFIR_2__TXFIR_COEFF_H10__MASK                          0x00ff0000U
#define BBB_TXFIR_2__TXFIR_COEFF_H10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define BBB_TXFIR_2__TXFIR_COEFF_H10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define BBB_TXFIR_2__TXFIR_COEFF_H10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txfir_coeff_h11 */
#define BBB_TXFIR_2__TXFIR_COEFF_H11__SHIFT                                  24
#define BBB_TXFIR_2__TXFIR_COEFF_H11__WIDTH                                   8
#define BBB_TXFIR_2__TXFIR_COEFF_H11__MASK                          0xff000000U
#define BBB_TXFIR_2__TXFIR_COEFF_H11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define BBB_TXFIR_2__TXFIR_COEFF_H11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define BBB_TXFIR_2__TXFIR_COEFF_H11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define BBB_TXFIR_2__TYPE                                             u_int32_t
#define BBB_TXFIR_2__READ                                           0xffffffffU
#define BBB_TXFIR_2__WRITE                                          0xffffffffU

#endif /* __BBB_TXFIR_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_2__NUM                   1

/* macros for BlueprintGlobalNameSpace::heavy_clip_ctrl */
#ifndef __HEAVY_CLIP_CTRL_MACRO__
#define __HEAVY_CLIP_CTRL_MACRO__

/* macros for field cf_heavy_clip_enable */
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__SHIFT                          0
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WIDTH                          9
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MASK                 0x000001ffU
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field pre_emp_ht40_enable */
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SHIFT                           9
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WIDTH                           1
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MASK                  0x00000200U
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field heavy_clip_factor_xr */
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__SHIFT                         10
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WIDTH                          8
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MASK                 0x0003fc00U
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fc00U) >> 10)
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0003fc00U)
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0003fc00U)
#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0003fc00U)))
#define HEAVY_CLIP_CTRL__TYPE                                         u_int32_t
#define HEAVY_CLIP_CTRL__READ                                       0x0003ffffU
#define HEAVY_CLIP_CTRL__WRITE                                      0x0003ffffU

#endif /* __HEAVY_CLIP_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_ctrl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_CTRL__NUM               1

/* macros for BlueprintGlobalNameSpace::heavy_clip_20 */
#ifndef __HEAVY_CLIP_20_MACRO__
#define __HEAVY_CLIP_20_MACRO__

/* macros for field heavy_clip_factor_0 */
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__SHIFT                             0
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WIDTH                             8
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MASK                    0x000000ffU
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field heavy_clip_factor_1 */
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__SHIFT                             8
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WIDTH                             8
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MASK                    0x0000ff00U
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field heavy_clip_factor_2 */
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__SHIFT                            16
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WIDTH                             8
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MASK                    0x00ff0000U
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field heavy_clip_factor_3 */
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__SHIFT                            24
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WIDTH                             8
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MASK                    0xff000000U
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define HEAVY_CLIP_20__TYPE                                           u_int32_t
#define HEAVY_CLIP_20__READ                                         0xffffffffU
#define HEAVY_CLIP_20__WRITE                                        0xffffffffU

#endif /* __HEAVY_CLIP_20_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_20 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_20__NUM                 1

/* macros for BlueprintGlobalNameSpace::heavy_clip_40 */
#ifndef __HEAVY_CLIP_40_MACRO__
#define __HEAVY_CLIP_40_MACRO__

/* macros for field heavy_clip_factor_4 */
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__SHIFT                             0
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WIDTH                             8
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MASK                    0x000000ffU
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field heavy_clip_factor_5 */
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__SHIFT                             8
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WIDTH                             8
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MASK                    0x0000ff00U
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field heavy_clip_factor_6 */
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__SHIFT                            16
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WIDTH                             8
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MASK                    0x00ff0000U
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field heavy_clip_factor_7 */
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__SHIFT                            24
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WIDTH                             8
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MASK                    0xff000000U
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define HEAVY_CLIP_40__TYPE                                           u_int32_t
#define HEAVY_CLIP_40__READ                                         0xffffffffU
#define HEAVY_CLIP_40__WRITE                                        0xffffffffU

#endif /* __HEAVY_CLIP_40_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_40 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_40__NUM                 1

/* macros for BlueprintGlobalNameSpace::illegal_tx_rate */
#ifndef __ILLEGAL_TX_RATE_MACRO__
#define __ILLEGAL_TX_RATE_MACRO__

/* macros for field illegal_tx_rate */
#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SHIFT                               0
#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__WIDTH                               1
#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__MASK                      0x00000001U
#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define ILLEGAL_TX_RATE__TYPE                                         u_int32_t
#define ILLEGAL_TX_RATE__READ                                       0x00000001U

#endif /* __ILLEGAL_TX_RATE_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_illegal_tx_rate */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ILLEGAL_TX_RATE__NUM               1

/* macros for BlueprintGlobalNameSpace::powertx_rate1 */
#ifndef __POWERTX_RATE1_MACRO__
#define __POWERTX_RATE1_MACRO__

/* macros for field powertx_0 */
#define POWERTX_RATE1__POWERTX_0__SHIFT                                       0
#define POWERTX_RATE1__POWERTX_0__WIDTH                                       6
#define POWERTX_RATE1__POWERTX_0__MASK                              0x0000003fU
#define POWERTX_RATE1__POWERTX_0__READ(src)      (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE1__POWERTX_0__WRITE(src)   ((u_int32_t)(src) & 0x0000003fU)
#define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE1__POWERTX_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertx_1 */
#define POWERTX_RATE1__POWERTX_1__SHIFT                                       8
#define POWERTX_RATE1__POWERTX_1__WIDTH                                       6
#define POWERTX_RATE1__POWERTX_1__MASK                              0x00003f00U
#define POWERTX_RATE1__POWERTX_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE1__POWERTX_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE1__POWERTX_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertx_2 */
#define POWERTX_RATE1__POWERTX_2__SHIFT                                      16
#define POWERTX_RATE1__POWERTX_2__WIDTH                                       6
#define POWERTX_RATE1__POWERTX_2__MASK                              0x003f0000U
#define POWERTX_RATE1__POWERTX_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE1__POWERTX_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE1__POWERTX_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertx_3 */
#define POWERTX_RATE1__POWERTX_3__SHIFT                                      24
#define POWERTX_RATE1__POWERTX_3__WIDTH                                       6
#define POWERTX_RATE1__POWERTX_3__MASK                              0x3f000000U
#define POWERTX_RATE1__POWERTX_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE1__POWERTX_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE1__POWERTX_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE1__TYPE                                           u_int32_t
#define POWERTX_RATE1__READ                                         0x3f3f3f3fU
#define POWERTX_RATE1__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE1__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate2 */
#ifndef __POWERTX_RATE2_MACRO__
#define __POWERTX_RATE2_MACRO__

/* macros for field powertx_4 */
#define POWERTX_RATE2__POWERTX_4__SHIFT                                       0
#define POWERTX_RATE2__POWERTX_4__WIDTH                                       6
#define POWERTX_RATE2__POWERTX_4__MASK                              0x0000003fU
#define POWERTX_RATE2__POWERTX_4__READ(src)      (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE2__POWERTX_4__WRITE(src)   ((u_int32_t)(src) & 0x0000003fU)
#define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE2__POWERTX_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertx_5 */
#define POWERTX_RATE2__POWERTX_5__SHIFT                                       8
#define POWERTX_RATE2__POWERTX_5__WIDTH                                       6
#define POWERTX_RATE2__POWERTX_5__MASK                              0x00003f00U
#define POWERTX_RATE2__POWERTX_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE2__POWERTX_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE2__POWERTX_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertx_6 */
#define POWERTX_RATE2__POWERTX_6__SHIFT                                      16
#define POWERTX_RATE2__POWERTX_6__WIDTH                                       6
#define POWERTX_RATE2__POWERTX_6__MASK                              0x003f0000U
#define POWERTX_RATE2__POWERTX_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE2__POWERTX_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE2__POWERTX_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertx_7 */
#define POWERTX_RATE2__POWERTX_7__SHIFT                                      24
#define POWERTX_RATE2__POWERTX_7__WIDTH                                       6
#define POWERTX_RATE2__POWERTX_7__MASK                              0x3f000000U
#define POWERTX_RATE2__POWERTX_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE2__POWERTX_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE2__POWERTX_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE2__TYPE                                           u_int32_t
#define POWERTX_RATE2__READ                                         0x3f3f3f3fU
#define POWERTX_RATE2__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE2__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate3 */
#ifndef __POWERTX_RATE3_MACRO__
#define __POWERTX_RATE3_MACRO__

/* macros for field powertx_1l */
#define POWERTX_RATE3__POWERTX_1L__SHIFT                                      0
#define POWERTX_RATE3__POWERTX_1L__WIDTH                                      6
#define POWERTX_RATE3__POWERTX_1L__MASK                             0x0000003fU
#define POWERTX_RATE3__POWERTX_1L__READ(src)     (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE3__POWERTX_1L__WRITE(src)  ((u_int32_t)(src) & 0x0000003fU)
#define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE3__POWERTX_1L__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertx_2l */
#define POWERTX_RATE3__POWERTX_2L__SHIFT                                     16
#define POWERTX_RATE3__POWERTX_2L__WIDTH                                      6
#define POWERTX_RATE3__POWERTX_2L__MASK                             0x003f0000U
#define POWERTX_RATE3__POWERTX_2L__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE3__POWERTX_2L__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE3__POWERTX_2L__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertx_2s */
#define POWERTX_RATE3__POWERTX_2S__SHIFT                                     24
#define POWERTX_RATE3__POWERTX_2S__WIDTH                                      6
#define POWERTX_RATE3__POWERTX_2S__MASK                             0x3f000000U
#define POWERTX_RATE3__POWERTX_2S__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE3__POWERTX_2S__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE3__POWERTX_2S__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE3__TYPE                                           u_int32_t
#define POWERTX_RATE3__READ                                         0x3f3f003fU
#define POWERTX_RATE3__WRITE                                        0x3f3f003fU

#endif /* __POWERTX_RATE3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE3__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate4 */
#ifndef __POWERTX_RATE4_MACRO__
#define __POWERTX_RATE4_MACRO__

/* macros for field powertx_55l */
#define POWERTX_RATE4__POWERTX_55L__SHIFT                                     0
#define POWERTX_RATE4__POWERTX_55L__WIDTH                                     6
#define POWERTX_RATE4__POWERTX_55L__MASK                            0x0000003fU
#define POWERTX_RATE4__POWERTX_55L__READ(src)    (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE4__POWERTX_55L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
#define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE4__POWERTX_55L__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertx_55s */
#define POWERTX_RATE4__POWERTX_55S__SHIFT                                     8
#define POWERTX_RATE4__POWERTX_55S__WIDTH                                     6
#define POWERTX_RATE4__POWERTX_55S__MASK                            0x00003f00U
#define POWERTX_RATE4__POWERTX_55S__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE4__POWERTX_55S__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE4__POWERTX_55S__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertx_11l */
#define POWERTX_RATE4__POWERTX_11L__SHIFT                                    16
#define POWERTX_RATE4__POWERTX_11L__WIDTH                                     6
#define POWERTX_RATE4__POWERTX_11L__MASK                            0x003f0000U
#define POWERTX_RATE4__POWERTX_11L__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE4__POWERTX_11L__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE4__POWERTX_11L__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertx_11s */
#define POWERTX_RATE4__POWERTX_11S__SHIFT                                    24
#define POWERTX_RATE4__POWERTX_11S__WIDTH                                     6
#define POWERTX_RATE4__POWERTX_11S__MASK                            0x3f000000U
#define POWERTX_RATE4__POWERTX_11S__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE4__POWERTX_11S__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE4__POWERTX_11S__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE4__TYPE                                           u_int32_t
#define POWERTX_RATE4__READ                                         0x3f3f3f3fU
#define POWERTX_RATE4__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE4_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate4 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE4__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate5 */
#ifndef __POWERTX_RATE5_MACRO__
#define __POWERTX_RATE5_MACRO__

/* macros for field powertxht20_0 */
#define POWERTX_RATE5__POWERTXHT20_0__SHIFT                                   0
#define POWERTX_RATE5__POWERTXHT20_0__WIDTH                                   6
#define POWERTX_RATE5__POWERTXHT20_0__MASK                          0x0000003fU
#define POWERTX_RATE5__POWERTXHT20_0__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE5__POWERTXHT20_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE5__POWERTXHT20_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht20_1 */
#define POWERTX_RATE5__POWERTXHT20_1__SHIFT                                   8
#define POWERTX_RATE5__POWERTXHT20_1__WIDTH                                   6
#define POWERTX_RATE5__POWERTXHT20_1__MASK                          0x00003f00U
#define POWERTX_RATE5__POWERTXHT20_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE5__POWERTXHT20_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE5__POWERTXHT20_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht20_2 */
#define POWERTX_RATE5__POWERTXHT20_2__SHIFT                                  16
#define POWERTX_RATE5__POWERTXHT20_2__WIDTH                                   6
#define POWERTX_RATE5__POWERTXHT20_2__MASK                          0x003f0000U
#define POWERTX_RATE5__POWERTXHT20_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE5__POWERTXHT20_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE5__POWERTXHT20_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht20_3 */
#define POWERTX_RATE5__POWERTXHT20_3__SHIFT                                  24
#define POWERTX_RATE5__POWERTXHT20_3__WIDTH                                   6
#define POWERTX_RATE5__POWERTXHT20_3__MASK                          0x3f000000U
#define POWERTX_RATE5__POWERTXHT20_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE5__POWERTXHT20_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE5__POWERTXHT20_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE5__TYPE                                           u_int32_t
#define POWERTX_RATE5__READ                                         0x3f3f3f3fU
#define POWERTX_RATE5__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE5_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate5 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE5__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate6 */
#ifndef __POWERTX_RATE6_MACRO__
#define __POWERTX_RATE6_MACRO__

/* macros for field powertxht20_4 */
#define POWERTX_RATE6__POWERTXHT20_4__SHIFT                                   0
#define POWERTX_RATE6__POWERTXHT20_4__WIDTH                                   6
#define POWERTX_RATE6__POWERTXHT20_4__MASK                          0x0000003fU
#define POWERTX_RATE6__POWERTXHT20_4__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE6__POWERTXHT20_4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE6__POWERTXHT20_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht20_5 */
#define POWERTX_RATE6__POWERTXHT20_5__SHIFT                                   8
#define POWERTX_RATE6__POWERTXHT20_5__WIDTH                                   6
#define POWERTX_RATE6__POWERTXHT20_5__MASK                          0x00003f00U
#define POWERTX_RATE6__POWERTXHT20_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE6__POWERTXHT20_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE6__POWERTXHT20_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht20_6 */
#define POWERTX_RATE6__POWERTXHT20_6__SHIFT                                  16
#define POWERTX_RATE6__POWERTXHT20_6__WIDTH                                   6
#define POWERTX_RATE6__POWERTXHT20_6__MASK                          0x003f0000U
#define POWERTX_RATE6__POWERTXHT20_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE6__POWERTXHT20_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE6__POWERTXHT20_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht20_7 */
#define POWERTX_RATE6__POWERTXHT20_7__SHIFT                                  24
#define POWERTX_RATE6__POWERTXHT20_7__WIDTH                                   6
#define POWERTX_RATE6__POWERTXHT20_7__MASK                          0x3f000000U
#define POWERTX_RATE6__POWERTXHT20_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE6__POWERTXHT20_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE6__POWERTXHT20_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE6__TYPE                                           u_int32_t
#define POWERTX_RATE6__READ                                         0x3f3f3f3fU
#define POWERTX_RATE6__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE6_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate6 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE6__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate7 */
#ifndef __POWERTX_RATE7_MACRO__
#define __POWERTX_RATE7_MACRO__

/* macros for field powertxht40_0 */
#define POWERTX_RATE7__POWERTXHT40_0__SHIFT                                   0
#define POWERTX_RATE7__POWERTXHT40_0__WIDTH                                   6
#define POWERTX_RATE7__POWERTXHT40_0__MASK                          0x0000003fU
#define POWERTX_RATE7__POWERTXHT40_0__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE7__POWERTXHT40_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE7__POWERTXHT40_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht40_1 */
#define POWERTX_RATE7__POWERTXHT40_1__SHIFT                                   8
#define POWERTX_RATE7__POWERTXHT40_1__WIDTH                                   6
#define POWERTX_RATE7__POWERTXHT40_1__MASK                          0x00003f00U
#define POWERTX_RATE7__POWERTXHT40_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE7__POWERTXHT40_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE7__POWERTXHT40_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht40_2 */
#define POWERTX_RATE7__POWERTXHT40_2__SHIFT                                  16
#define POWERTX_RATE7__POWERTXHT40_2__WIDTH                                   6
#define POWERTX_RATE7__POWERTXHT40_2__MASK                          0x003f0000U
#define POWERTX_RATE7__POWERTXHT40_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE7__POWERTXHT40_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE7__POWERTXHT40_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht40_3 */
#define POWERTX_RATE7__POWERTXHT40_3__SHIFT                                  24
#define POWERTX_RATE7__POWERTXHT40_3__WIDTH                                   6
#define POWERTX_RATE7__POWERTXHT40_3__MASK                          0x3f000000U
#define POWERTX_RATE7__POWERTXHT40_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE7__POWERTXHT40_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE7__POWERTXHT40_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE7__TYPE                                           u_int32_t
#define POWERTX_RATE7__READ                                         0x3f3f3f3fU
#define POWERTX_RATE7__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE7_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate7 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE7__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate8 */
#ifndef __POWERTX_RATE8_MACRO__
#define __POWERTX_RATE8_MACRO__

/* macros for field powertxht40_4 */
#define POWERTX_RATE8__POWERTXHT40_4__SHIFT                                   0
#define POWERTX_RATE8__POWERTXHT40_4__WIDTH                                   6
#define POWERTX_RATE8__POWERTXHT40_4__MASK                          0x0000003fU
#define POWERTX_RATE8__POWERTXHT40_4__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE8__POWERTXHT40_4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE8__POWERTXHT40_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht40_5 */
#define POWERTX_RATE8__POWERTXHT40_5__SHIFT                                   8
#define POWERTX_RATE8__POWERTXHT40_5__WIDTH                                   6
#define POWERTX_RATE8__POWERTXHT40_5__MASK                          0x00003f00U
#define POWERTX_RATE8__POWERTXHT40_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE8__POWERTXHT40_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE8__POWERTXHT40_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht40_6 */
#define POWERTX_RATE8__POWERTXHT40_6__SHIFT                                  16
#define POWERTX_RATE8__POWERTXHT40_6__WIDTH                                   6
#define POWERTX_RATE8__POWERTXHT40_6__MASK                          0x003f0000U
#define POWERTX_RATE8__POWERTXHT40_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE8__POWERTXHT40_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE8__POWERTXHT40_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht40_7 */
#define POWERTX_RATE8__POWERTXHT40_7__SHIFT                                  24
#define POWERTX_RATE8__POWERTXHT40_7__WIDTH                                   6
#define POWERTX_RATE8__POWERTXHT40_7__MASK                          0x3f000000U
#define POWERTX_RATE8__POWERTXHT40_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE8__POWERTXHT40_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE8__POWERTXHT40_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE8__TYPE                                           u_int32_t
#define POWERTX_RATE8__READ                                         0x3f3f3f3fU
#define POWERTX_RATE8__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE8_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate8 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE8__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate9 */
#ifndef __POWERTX_RATE9_MACRO__
#define __POWERTX_RATE9_MACRO__

/* macros for field powertx_dup40_cck */
#define POWERTX_RATE9__POWERTX_DUP40_CCK__SHIFT                               0
#define POWERTX_RATE9__POWERTX_DUP40_CCK__WIDTH                               6
#define POWERTX_RATE9__POWERTX_DUP40_CCK__MASK                      0x0000003fU
#define POWERTX_RATE9__POWERTX_DUP40_CCK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define POWERTX_RATE9__POWERTX_DUP40_CCK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE9__POWERTX_DUP40_CCK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertx_dup40_ofdm */
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__SHIFT                              8
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WIDTH                              6
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MASK                     0x00003f00U
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE9__POWERTX_DUP40_OFDM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertx_ext20_cck */
#define POWERTX_RATE9__POWERTX_EXT20_CCK__SHIFT                              16
#define POWERTX_RATE9__POWERTX_EXT20_CCK__WIDTH                               6
#define POWERTX_RATE9__POWERTX_EXT20_CCK__MASK                      0x003f0000U
#define POWERTX_RATE9__POWERTX_EXT20_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE9__POWERTX_EXT20_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE9__POWERTX_EXT20_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertx_ext20_ofdm */
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__SHIFT                             24
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WIDTH                              6
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MASK                     0x3f000000U
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE9__POWERTX_EXT20_OFDM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE9__TYPE                                           u_int32_t
#define POWERTX_RATE9__READ                                         0x3f3f3f3fU
#define POWERTX_RATE9__WRITE                                        0x3f3f3f3fU

#endif /* __POWERTX_RATE9_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate9 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE9__NUM                 1

/* macros for BlueprintGlobalNameSpace::powertx_rate10 */
#ifndef __POWERTX_RATE10_MACRO__
#define __POWERTX_RATE10_MACRO__

/* macros for field powertxht20_8 */
#define POWERTX_RATE10__POWERTXHT20_8__SHIFT                                  0
#define POWERTX_RATE10__POWERTXHT20_8__WIDTH                                  6
#define POWERTX_RATE10__POWERTXHT20_8__MASK                         0x0000003fU
#define POWERTX_RATE10__POWERTXHT20_8__READ(src) (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE10__POWERTXHT20_8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE10__POWERTXHT20_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht20_9 */
#define POWERTX_RATE10__POWERTXHT20_9__SHIFT                                  8
#define POWERTX_RATE10__POWERTXHT20_9__WIDTH                                  6
#define POWERTX_RATE10__POWERTXHT20_9__MASK                         0x00003f00U
#define POWERTX_RATE10__POWERTXHT20_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE10__POWERTXHT20_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE10__POWERTXHT20_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht20_10 */
#define POWERTX_RATE10__POWERTXHT20_10__SHIFT                                16
#define POWERTX_RATE10__POWERTXHT20_10__WIDTH                                 6
#define POWERTX_RATE10__POWERTXHT20_10__MASK                        0x003f0000U
#define POWERTX_RATE10__POWERTXHT20_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE10__POWERTXHT20_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE10__POWERTXHT20_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht20_11 */
#define POWERTX_RATE10__POWERTXHT20_11__SHIFT                                24
#define POWERTX_RATE10__POWERTXHT20_11__WIDTH                                 6
#define POWERTX_RATE10__POWERTXHT20_11__MASK                        0x3f000000U
#define POWERTX_RATE10__POWERTXHT20_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE10__POWERTXHT20_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE10__POWERTXHT20_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE10__TYPE                                          u_int32_t
#define POWERTX_RATE10__READ                                        0x3f3f3f3fU
#define POWERTX_RATE10__WRITE                                       0x3f3f3f3fU

#endif /* __POWERTX_RATE10_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate10 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE10__NUM                1

/* macros for BlueprintGlobalNameSpace::powertx_rate11 */
#ifndef __POWERTX_RATE11_MACRO__
#define __POWERTX_RATE11_MACRO__

/* macros for field powertxht20_12 */
#define POWERTX_RATE11__POWERTXHT20_12__SHIFT                                 0
#define POWERTX_RATE11__POWERTXHT20_12__WIDTH                                 6
#define POWERTX_RATE11__POWERTXHT20_12__MASK                        0x0000003fU
#define POWERTX_RATE11__POWERTXHT20_12__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define POWERTX_RATE11__POWERTXHT20_12__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE11__POWERTXHT20_12__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht20_13 */
#define POWERTX_RATE11__POWERTXHT20_13__SHIFT                                 8
#define POWERTX_RATE11__POWERTXHT20_13__WIDTH                                 6
#define POWERTX_RATE11__POWERTXHT20_13__MASK                        0x00003f00U
#define POWERTX_RATE11__POWERTXHT20_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE11__POWERTXHT20_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE11__POWERTXHT20_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht40_12 */
#define POWERTX_RATE11__POWERTXHT40_12__SHIFT                                16
#define POWERTX_RATE11__POWERTXHT40_12__WIDTH                                 6
#define POWERTX_RATE11__POWERTXHT40_12__MASK                        0x003f0000U
#define POWERTX_RATE11__POWERTXHT40_12__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE11__POWERTXHT40_12__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE11__POWERTXHT40_12__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht40_13 */
#define POWERTX_RATE11__POWERTXHT40_13__SHIFT                                24
#define POWERTX_RATE11__POWERTXHT40_13__WIDTH                                 6
#define POWERTX_RATE11__POWERTXHT40_13__MASK                        0x3f000000U
#define POWERTX_RATE11__POWERTXHT40_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE11__POWERTXHT40_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE11__POWERTXHT40_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE11__TYPE                                          u_int32_t
#define POWERTX_RATE11__READ                                        0x3f3f3f3fU
#define POWERTX_RATE11__WRITE                                       0x3f3f3f3fU

#endif /* __POWERTX_RATE11_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate11 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE11__NUM                1

/* macros for BlueprintGlobalNameSpace::powertx_rate12 */
#ifndef __POWERTX_RATE12_MACRO__
#define __POWERTX_RATE12_MACRO__

/* macros for field powertxht40_8 */
#define POWERTX_RATE12__POWERTXHT40_8__SHIFT                                  0
#define POWERTX_RATE12__POWERTXHT40_8__WIDTH                                  6
#define POWERTX_RATE12__POWERTXHT40_8__MASK                         0x0000003fU
#define POWERTX_RATE12__POWERTXHT40_8__READ(src) (u_int32_t)(src) & 0x0000003fU
#define POWERTX_RATE12__POWERTXHT40_8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_RATE12__POWERTXHT40_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertxht40_9 */
#define POWERTX_RATE12__POWERTXHT40_9__SHIFT                                  8
#define POWERTX_RATE12__POWERTXHT40_9__WIDTH                                  6
#define POWERTX_RATE12__POWERTXHT40_9__MASK                         0x00003f00U
#define POWERTX_RATE12__POWERTXHT40_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define POWERTX_RATE12__POWERTXHT40_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define POWERTX_RATE12__POWERTXHT40_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field powertxht40_10 */
#define POWERTX_RATE12__POWERTXHT40_10__SHIFT                                16
#define POWERTX_RATE12__POWERTXHT40_10__WIDTH                                 6
#define POWERTX_RATE12__POWERTXHT40_10__MASK                        0x003f0000U
#define POWERTX_RATE12__POWERTXHT40_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define POWERTX_RATE12__POWERTXHT40_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define POWERTX_RATE12__POWERTXHT40_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field powertxht40_11 */
#define POWERTX_RATE12__POWERTXHT40_11__SHIFT                                24
#define POWERTX_RATE12__POWERTXHT40_11__WIDTH                                 6
#define POWERTX_RATE12__POWERTXHT40_11__MASK                        0x3f000000U
#define POWERTX_RATE12__POWERTXHT40_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define POWERTX_RATE12__POWERTXHT40_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define POWERTX_RATE12__POWERTXHT40_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define POWERTX_RATE12__TYPE                                          u_int32_t
#define POWERTX_RATE12__READ                                        0x3f3f3f3fU
#define POWERTX_RATE12__WRITE                                       0x3f3f3f3fU

#endif /* __POWERTX_RATE12_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate12 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE12__NUM                1

/* macros for BlueprintGlobalNameSpace::powertx_max */
#ifndef __POWERTX_MAX_MACRO__
#define __POWERTX_MAX_MACRO__

/* macros for field use_per_packet_powertx_max */
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SHIFT                        6
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WIDTH                        1
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MASK               0x00000040U
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field use_per_packet_olpc_gain_delta_adj */
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SHIFT                7
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WIDTH                1
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MASK       0x00000080U
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)
#define POWERTX_MAX__TYPE                                             u_int32_t
#define POWERTX_MAX__READ                                           0x000000c0U
#define POWERTX_MAX__WRITE                                          0x000000c0U

#endif /* __POWERTX_MAX_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_max */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_MAX__NUM                   1

/* macros for BlueprintGlobalNameSpace::powertx_sub */
#ifndef __POWERTX_SUB_MACRO__
#define __POWERTX_SUB_MACRO__

/* macros for field powertx_sub_for_2chain */
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__SHIFT                            0
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WIDTH                            6
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MASK                   0x0000003fU
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field powertx_sub_for_3chain */
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__SHIFT                            6
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WIDTH                            6
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MASK                   0x00000fc0U
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))
#define POWERTX_SUB__TYPE                                             u_int32_t
#define POWERTX_SUB__READ                                           0x00000fffU
#define POWERTX_SUB__WRITE                                          0x00000fffU

#endif /* __POWERTX_SUB_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_sub */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_SUB__NUM                   1

/* macros for BlueprintGlobalNameSpace::tpc_1 */
#ifndef __TPC_1_MACRO__
#define __TPC_1_MACRO__

/* macros for field force_dac_gain */
#define TPC_1__FORCE_DAC_GAIN__SHIFT                                          0
#define TPC_1__FORCE_DAC_GAIN__WIDTH                                          1
#define TPC_1__FORCE_DAC_GAIN__MASK                                 0x00000001U
#define TPC_1__FORCE_DAC_GAIN__READ(src)         (u_int32_t)(src) & 0x00000001U
#define TPC_1__FORCE_DAC_GAIN__WRITE(src)      ((u_int32_t)(src) & 0x00000001U)
#define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TPC_1__FORCE_DAC_GAIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TPC_1__FORCE_DAC_GAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TPC_1__FORCE_DAC_GAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field forced_dac_gain */
#define TPC_1__FORCED_DAC_GAIN__SHIFT                                         1
#define TPC_1__FORCED_DAC_GAIN__WIDTH                                         5
#define TPC_1__FORCED_DAC_GAIN__MASK                                0x0000003eU
#define TPC_1__FORCED_DAC_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003eU) >> 1)
#define TPC_1__FORCED_DAC_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000003eU)
#define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000003eU)
#define TPC_1__FORCED_DAC_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000003eU)))

/* macros for field pd_dc_offset_target */
#define TPC_1__PD_DC_OFFSET_TARGET__SHIFT                                     6
#define TPC_1__PD_DC_OFFSET_TARGET__WIDTH                                     8
#define TPC_1__PD_DC_OFFSET_TARGET__MASK                            0x00003fc0U
#define TPC_1__PD_DC_OFFSET_TARGET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003fc0U) >> 6)
#define TPC_1__PD_DC_OFFSET_TARGET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00003fc0U)
#define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00003fc0U)
#define TPC_1__PD_DC_OFFSET_TARGET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00003fc0U)))

/* macros for field num_pd_gain */
#define TPC_1__NUM_PD_GAIN__SHIFT                                            14
#define TPC_1__NUM_PD_GAIN__WIDTH                                             2
#define TPC_1__NUM_PD_GAIN__MASK                                    0x0000c000U
#define TPC_1__NUM_PD_GAIN__READ(src)  (((u_int32_t)(src) & 0x0000c000U) >> 14)
#define TPC_1__NUM_PD_GAIN__WRITE(src) (((u_int32_t)(src) << 14) & 0x0000c000U)
#define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0000c000U)
#define TPC_1__NUM_PD_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field pd_gain_setting1 */
#define TPC_1__PD_GAIN_SETTING1__SHIFT                                       16
#define TPC_1__PD_GAIN_SETTING1__WIDTH                                        2
#define TPC_1__PD_GAIN_SETTING1__MASK                               0x00030000U
#define TPC_1__PD_GAIN_SETTING1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00030000U) >> 16)
#define TPC_1__PD_GAIN_SETTING1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00030000U)
#define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00030000U) | (((u_int32_t)(src) <<\
                    16) & 0x00030000U)
#define TPC_1__PD_GAIN_SETTING1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00030000U)))

/* macros for field pd_gain_setting2 */
#define TPC_1__PD_GAIN_SETTING2__SHIFT                                       18
#define TPC_1__PD_GAIN_SETTING2__WIDTH                                        2
#define TPC_1__PD_GAIN_SETTING2__MASK                               0x000c0000U
#define TPC_1__PD_GAIN_SETTING2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000c0000U) >> 18)
#define TPC_1__PD_GAIN_SETTING2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x000c0000U)
#define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x000c0000U)
#define TPC_1__PD_GAIN_SETTING2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x000c0000U)))

/* macros for field pd_gain_setting3 */
#define TPC_1__PD_GAIN_SETTING3__SHIFT                                       20
#define TPC_1__PD_GAIN_SETTING3__WIDTH                                        2
#define TPC_1__PD_GAIN_SETTING3__MASK                               0x00300000U
#define TPC_1__PD_GAIN_SETTING3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00300000U) >> 20)
#define TPC_1__PD_GAIN_SETTING3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00300000U)
#define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00300000U) | (((u_int32_t)(src) <<\
                    20) & 0x00300000U)
#define TPC_1__PD_GAIN_SETTING3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00300000U)))

/* macros for field enable_pd_calibrate */
#define TPC_1__ENABLE_PD_CALIBRATE__SHIFT                                    22
#define TPC_1__ENABLE_PD_CALIBRATE__WIDTH                                     1
#define TPC_1__ENABLE_PD_CALIBRATE__MASK                            0x00400000U
#define TPC_1__ENABLE_PD_CALIBRATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define TPC_1__ENABLE_PD_CALIBRATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define TPC_1__ENABLE_PD_CALIBRATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define TPC_1__ENABLE_PD_CALIBRATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define TPC_1__ENABLE_PD_CALIBRATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field pd_calibrate_wait */
#define TPC_1__PD_CALIBRATE_WAIT__SHIFT                                      23
#define TPC_1__PD_CALIBRATE_WAIT__WIDTH                                       6
#define TPC_1__PD_CALIBRATE_WAIT__MASK                              0x1f800000U
#define TPC_1__PD_CALIBRATE_WAIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f800000U) >> 23)
#define TPC_1__PD_CALIBRATE_WAIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x1f800000U)
#define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x1f800000U)
#define TPC_1__PD_CALIBRATE_WAIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x1f800000U)))

/* macros for field force_pdadc_gain */
#define TPC_1__FORCE_PDADC_GAIN__SHIFT                                       29
#define TPC_1__FORCE_PDADC_GAIN__WIDTH                                        1
#define TPC_1__FORCE_PDADC_GAIN__MASK                               0x20000000U
#define TPC_1__FORCE_PDADC_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define TPC_1__FORCE_PDADC_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define TPC_1__FORCE_PDADC_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define TPC_1__FORCE_PDADC_GAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define TPC_1__FORCE_PDADC_GAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field forced_pdadc_gain */
#define TPC_1__FORCED_PDADC_GAIN__SHIFT                                      30
#define TPC_1__FORCED_PDADC_GAIN__WIDTH                                       2
#define TPC_1__FORCED_PDADC_GAIN__MASK                              0xc0000000U
#define TPC_1__FORCED_PDADC_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define TPC_1__FORCED_PDADC_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define TPC_1__FORCED_PDADC_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define TPC_1__TYPE                                                   u_int32_t
#define TPC_1__READ                                                 0xffffffffU
#define TPC_1__WRITE                                                0xffffffffU

#endif /* __TPC_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_1__NUM                         1

/* macros for BlueprintGlobalNameSpace::tpc_2 */
#ifndef __TPC_2_MACRO__
#define __TPC_2_MACRO__

/* macros for field tx_frame_to_pdadc_on */
#define TPC_2__TX_FRAME_TO_PDADC_ON__SHIFT                                    0
#define TPC_2__TX_FRAME_TO_PDADC_ON__WIDTH                                    8
#define TPC_2__TX_FRAME_TO_PDADC_ON__MASK                           0x000000ffU
#define TPC_2__TX_FRAME_TO_PDADC_ON__READ(src)   (u_int32_t)(src) & 0x000000ffU
#define TPC_2__TX_FRAME_TO_PDADC_ON__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TPC_2__TX_FRAME_TO_PDADC_ON__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tx_frame_to_pd_acc_ofdm */
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__SHIFT                                 8
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WIDTH                                 8
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MASK                        0x0000ff00U
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field tx_frame_to_pd_acc_cck */
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__SHIFT                                 16
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WIDTH                                  8
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MASK                         0x00ff0000U
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))
#define TPC_2__TYPE                                                   u_int32_t
#define TPC_2__READ                                                 0x00ffffffU
#define TPC_2__WRITE                                                0x00ffffffU

#endif /* __TPC_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_2__NUM                         1

/* macros for BlueprintGlobalNameSpace::tpc_3 */
#ifndef __TPC_3_MACRO__
#define __TPC_3_MACRO__

/* macros for field tx_end_to_pdadc_on */
#define TPC_3__TX_END_TO_PDADC_ON__SHIFT                                      0
#define TPC_3__TX_END_TO_PDADC_ON__WIDTH                                      8
#define TPC_3__TX_END_TO_PDADC_ON__MASK                             0x000000ffU
#define TPC_3__TX_END_TO_PDADC_ON__READ(src)     (u_int32_t)(src) & 0x000000ffU
#define TPC_3__TX_END_TO_PDADC_ON__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
#define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TPC_3__TX_END_TO_PDADC_ON__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field tx_end_to_pd_acc_on */
#define TPC_3__TX_END_TO_PD_ACC_ON__SHIFT                                     8
#define TPC_3__TX_END_TO_PD_ACC_ON__WIDTH                                     8
#define TPC_3__TX_END_TO_PD_ACC_ON__MASK                            0x0000ff00U
#define TPC_3__TX_END_TO_PD_ACC_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TPC_3__TX_END_TO_PD_ACC_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TPC_3__TX_END_TO_PD_ACC_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field pd_acc_window_dc_off */
#define TPC_3__PD_ACC_WINDOW_DC_OFF__SHIFT                                   16
#define TPC_3__PD_ACC_WINDOW_DC_OFF__WIDTH                                    3
#define TPC_3__PD_ACC_WINDOW_DC_OFF__MASK                           0x00070000U
#define TPC_3__PD_ACC_WINDOW_DC_OFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00070000U) >> 16)
#define TPC_3__PD_ACC_WINDOW_DC_OFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00070000U)
#define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((u_int32_t)(src) <<\
                    16) & 0x00070000U)
#define TPC_3__PD_ACC_WINDOW_DC_OFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field pd_acc_window_cal */
#define TPC_3__PD_ACC_WINDOW_CAL__SHIFT                                      19
#define TPC_3__PD_ACC_WINDOW_CAL__WIDTH                                       3
#define TPC_3__PD_ACC_WINDOW_CAL__MASK                              0x00380000U
#define TPC_3__PD_ACC_WINDOW_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00380000U) >> 19)
#define TPC_3__PD_ACC_WINDOW_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00380000U)
#define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00380000U) | (((u_int32_t)(src) <<\
                    19) & 0x00380000U)
#define TPC_3__PD_ACC_WINDOW_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00380000U)))

/* macros for field pd_acc_window_ofdm */
#define TPC_3__PD_ACC_WINDOW_OFDM__SHIFT                                     22
#define TPC_3__PD_ACC_WINDOW_OFDM__WIDTH                                      3
#define TPC_3__PD_ACC_WINDOW_OFDM__MASK                             0x01c00000U
#define TPC_3__PD_ACC_WINDOW_OFDM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01c00000U) >> 22)
#define TPC_3__PD_ACC_WINDOW_OFDM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x01c00000U)
#define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x01c00000U)
#define TPC_3__PD_ACC_WINDOW_OFDM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x01c00000U)))

/* macros for field pd_acc_window_cck */
#define TPC_3__PD_ACC_WINDOW_CCK__SHIFT                                      25
#define TPC_3__PD_ACC_WINDOW_CCK__WIDTH                                       3
#define TPC_3__PD_ACC_WINDOW_CCK__MASK                              0x0e000000U
#define TPC_3__PD_ACC_WINDOW_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0e000000U) >> 25)
#define TPC_3__PD_ACC_WINDOW_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x0e000000U)
#define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x0e000000U)
#define TPC_3__PD_ACC_WINDOW_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x0e000000U)))

/* macros for field tpc_clk_gate_enable */
#define TPC_3__TPC_CLK_GATE_ENABLE__SHIFT                                    31
#define TPC_3__TPC_CLK_GATE_ENABLE__WIDTH                                     1
#define TPC_3__TPC_CLK_GATE_ENABLE__MASK                            0x80000000U
#define TPC_3__TPC_CLK_GATE_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TPC_3__TPC_CLK_GATE_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TPC_3__TPC_CLK_GATE_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TPC_3__TPC_CLK_GATE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TPC_3__TPC_CLK_GATE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TPC_3__TYPE                                                   u_int32_t
#define TPC_3__READ                                                 0x8fffffffU
#define TPC_3__WRITE                                                0x8fffffffU

#endif /* __TPC_3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_3__NUM                         1

/* macros for BlueprintGlobalNameSpace::tpc_4_b0 */
#ifndef __TPC_4_B0_MACRO__
#define __TPC_4_B0_MACRO__

/* macros for field pd_avg_valid_0 */
#define TPC_4_B0__PD_AVG_VALID_0__SHIFT                                       0
#define TPC_4_B0__PD_AVG_VALID_0__WIDTH                                       1
#define TPC_4_B0__PD_AVG_VALID_0__MASK                              0x00000001U
#define TPC_4_B0__PD_AVG_VALID_0__READ(src)      (u_int32_t)(src) & 0x00000001U
#define TPC_4_B0__PD_AVG_VALID_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TPC_4_B0__PD_AVG_VALID_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field pd_avg_out_0 */
#define TPC_4_B0__PD_AVG_OUT_0__SHIFT                                         1
#define TPC_4_B0__PD_AVG_OUT_0__WIDTH                                         8
#define TPC_4_B0__PD_AVG_OUT_0__MASK                                0x000001feU
#define TPC_4_B0__PD_AVG_OUT_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)

/* macros for field dac_gain_0 */
#define TPC_4_B0__DAC_GAIN_0__SHIFT                                           9
#define TPC_4_B0__DAC_GAIN_0__WIDTH                                           5
#define TPC_4_B0__DAC_GAIN_0__MASK                                  0x00003e00U
#define TPC_4_B0__DAC_GAIN_0__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)

/* macros for field tx_gain_setting_0 */
#define TPC_4_B0__TX_GAIN_SETTING_0__SHIFT                                   14
#define TPC_4_B0__TX_GAIN_SETTING_0__WIDTH                                    6
#define TPC_4_B0__TX_GAIN_SETTING_0__MASK                           0x000fc000U
#define TPC_4_B0__TX_GAIN_SETTING_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fc000U) >> 14)

/* macros for field rate_sent_0 */
#define TPC_4_B0__RATE_SENT_0__SHIFT                                         20
#define TPC_4_B0__RATE_SENT_0__WIDTH                                          5
#define TPC_4_B0__RATE_SENT_0__MASK                                 0x01f00000U
#define TPC_4_B0__RATE_SENT_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)

/* macros for field error_est_update_power_thresh */
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__SHIFT                       25
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WIDTH                        6
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MASK               0x7e000000U
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7e000000U) >> 25)
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x7e000000U)
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x7e000000U)
#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x7e000000U)))
#define TPC_4_B0__TYPE                                                u_int32_t
#define TPC_4_B0__READ                                              0x7fffffffU
#define TPC_4_B0__WRITE                                             0x7fffffffU

#endif /* __TPC_4_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_4_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_4_B0__NUM                      1

/* macros for BlueprintGlobalNameSpace::tpc_5_b0 */
#ifndef __TPC_5_B0_MACRO__
#define __TPC_5_B0_MACRO__

/* macros for field pd_gain_overlap */
#define TPC_5_B0__PD_GAIN_OVERLAP__SHIFT                                      0
#define TPC_5_B0__PD_GAIN_OVERLAP__WIDTH                                      4
#define TPC_5_B0__PD_GAIN_OVERLAP__MASK                             0x0000000fU
#define TPC_5_B0__PD_GAIN_OVERLAP__READ(src)     (u_int32_t)(src) & 0x0000000fU
#define TPC_5_B0__PD_GAIN_OVERLAP__WRITE(src)  ((u_int32_t)(src) & 0x0000000fU)
#define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define TPC_5_B0__PD_GAIN_OVERLAP__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field pd_gain_boundary_1_0 */
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__SHIFT                                 4
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WIDTH                                 6
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MASK                        0x000003f0U
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field pd_gain_boundary_2_0 */
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__SHIFT                                10
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WIDTH                                 6
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MASK                        0x0000fc00U
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fc00U) >> 10)
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0000fc00U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0000fc00U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0000fc00U)))

/* macros for field pd_gain_boundary_3_0 */
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__SHIFT                                16
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WIDTH                                 6
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MASK                        0x003f0000U
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field pd_gain_boundary_4_0 */
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__SHIFT                                22
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WIDTH                                 6
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MASK                        0x0fc00000U
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fc00000U) >> 22)
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x0fc00000U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x0fc00000U)
#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x0fc00000U)))
#define TPC_5_B0__TYPE                                                u_int32_t
#define TPC_5_B0__READ                                              0x0fffffffU
#define TPC_5_B0__WRITE                                             0x0fffffffU

#endif /* __TPC_5_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_5_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_5_B0__NUM                      1

/* macros for BlueprintGlobalNameSpace::tpc_6_b0 */
#ifndef __TPC_6_B0_MACRO__
#define __TPC_6_B0_MACRO__

/* macros for field pd_dac_setting_1_0 */
#define TPC_6_B0__PD_DAC_SETTING_1_0__SHIFT                                   0
#define TPC_6_B0__PD_DAC_SETTING_1_0__WIDTH                                   6
#define TPC_6_B0__PD_DAC_SETTING_1_0__MASK                          0x0000003fU
#define TPC_6_B0__PD_DAC_SETTING_1_0__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define TPC_6_B0__PD_DAC_SETTING_1_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define TPC_6_B0__PD_DAC_SETTING_1_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field pd_dac_setting_2_0 */
#define TPC_6_B0__PD_DAC_SETTING_2_0__SHIFT                                   6
#define TPC_6_B0__PD_DAC_SETTING_2_0__WIDTH                                   6
#define TPC_6_B0__PD_DAC_SETTING_2_0__MASK                          0x00000fc0U
#define TPC_6_B0__PD_DAC_SETTING_2_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define TPC_6_B0__PD_DAC_SETTING_2_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define TPC_6_B0__PD_DAC_SETTING_2_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field pd_dac_setting_3_0 */
#define TPC_6_B0__PD_DAC_SETTING_3_0__SHIFT                                  12
#define TPC_6_B0__PD_DAC_SETTING_3_0__WIDTH                                   6
#define TPC_6_B0__PD_DAC_SETTING_3_0__MASK                          0x0003f000U
#define TPC_6_B0__PD_DAC_SETTING_3_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define TPC_6_B0__PD_DAC_SETTING_3_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define TPC_6_B0__PD_DAC_SETTING_3_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field pd_dac_setting_4_0 */
#define TPC_6_B0__PD_DAC_SETTING_4_0__SHIFT                                  18
#define TPC_6_B0__PD_DAC_SETTING_4_0__WIDTH                                   6
#define TPC_6_B0__PD_DAC_SETTING_4_0__MASK                          0x00fc0000U
#define TPC_6_B0__PD_DAC_SETTING_4_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define TPC_6_B0__PD_DAC_SETTING_4_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00fc0000U)
#define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define TPC_6_B0__PD_DAC_SETTING_4_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field error_est_mode */
#define TPC_6_B0__ERROR_EST_MODE__SHIFT                                      24
#define TPC_6_B0__ERROR_EST_MODE__WIDTH                                       2
#define TPC_6_B0__ERROR_EST_MODE__MASK                              0x03000000U
#define TPC_6_B0__ERROR_EST_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03000000U) >> 24)
#define TPC_6_B0__ERROR_EST_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x03000000U)
#define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define TPC_6_B0__ERROR_EST_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field error_est_filter_coeff */
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__SHIFT                              26
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WIDTH                               3
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MASK                      0x1c000000U
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define TPC_6_B0__ERROR_EST_FILTER_COEFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))
#define TPC_6_B0__TYPE                                                u_int32_t
#define TPC_6_B0__READ                                              0x1fffffffU
#define TPC_6_B0__WRITE                                             0x1fffffffU

#endif /* __TPC_6_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_6_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_6_B0__NUM                      1

/* macros for BlueprintGlobalNameSpace::tpc_7 */
#ifndef __TPC_7_MACRO__
#define __TPC_7_MACRO__

/* macros for field tx_gain_table_max */
#define TPC_7__TX_GAIN_TABLE_MAX__SHIFT                                       0
#define TPC_7__TX_GAIN_TABLE_MAX__WIDTH                                       6
#define TPC_7__TX_GAIN_TABLE_MAX__MASK                              0x0000003fU
#define TPC_7__TX_GAIN_TABLE_MAX__READ(src)      (u_int32_t)(src) & 0x0000003fU
#define TPC_7__TX_GAIN_TABLE_MAX__WRITE(src)   ((u_int32_t)(src) & 0x0000003fU)
#define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define TPC_7__TX_GAIN_TABLE_MAX__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field init_tx_gain_setting */
#define TPC_7__INIT_TX_GAIN_SETTING__SHIFT                                    6
#define TPC_7__INIT_TX_GAIN_SETTING__WIDTH                                    6
#define TPC_7__INIT_TX_GAIN_SETTING__MASK                           0x00000fc0U
#define TPC_7__INIT_TX_GAIN_SETTING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define TPC_7__INIT_TX_GAIN_SETTING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define TPC_7__INIT_TX_GAIN_SETTING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field en_cl_gain_mod */
#define TPC_7__EN_CL_GAIN_MOD__SHIFT                                         12
#define TPC_7__EN_CL_GAIN_MOD__WIDTH                                          1
#define TPC_7__EN_CL_GAIN_MOD__MASK                                 0x00001000U
#define TPC_7__EN_CL_GAIN_MOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define TPC_7__EN_CL_GAIN_MOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define TPC_7__EN_CL_GAIN_MOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define TPC_7__EN_CL_GAIN_MOD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define TPC_7__EN_CL_GAIN_MOD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field use_tx_pd_in_xpa */
#define TPC_7__USE_TX_PD_IN_XPA__SHIFT                                       13
#define TPC_7__USE_TX_PD_IN_XPA__WIDTH                                        1
#define TPC_7__USE_TX_PD_IN_XPA__MASK                               0x00002000U
#define TPC_7__USE_TX_PD_IN_XPA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define TPC_7__USE_TX_PD_IN_XPA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TPC_7__USE_TX_PD_IN_XPA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TPC_7__USE_TX_PD_IN_XPA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TPC_7__USE_TX_PD_IN_XPA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field extend_tx_frame_for_tpc */
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SHIFT                                14
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WIDTH                                 1
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MASK                        0x00004000U
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field use_init_tx_gain_setting_after_warm_reset */
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SHIFT              15
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WIDTH               1
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MASK      0x00008000U
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)
#define TPC_7__TYPE                                                   u_int32_t
#define TPC_7__READ                                                 0x0000ffffU
#define TPC_7__WRITE                                                0x0000ffffU

#endif /* __TPC_7_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_7 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_7__NUM                         1

/* macros for BlueprintGlobalNameSpace::tpc_8 */
#ifndef __TPC_8_MACRO__
#define __TPC_8_MACRO__

/* macros for field desired_scale_0 */
#define TPC_8__DESIRED_SCALE_0__SHIFT                                         0
#define TPC_8__DESIRED_SCALE_0__WIDTH                                         5
#define TPC_8__DESIRED_SCALE_0__MASK                                0x0000001fU
#define TPC_8__DESIRED_SCALE_0__READ(src)        (u_int32_t)(src) & 0x0000001fU
#define TPC_8__DESIRED_SCALE_0__WRITE(src)     ((u_int32_t)(src) & 0x0000001fU)
#define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_8__DESIRED_SCALE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_1 */
#define TPC_8__DESIRED_SCALE_1__SHIFT                                         5
#define TPC_8__DESIRED_SCALE_1__WIDTH                                         5
#define TPC_8__DESIRED_SCALE_1__MASK                                0x000003e0U
#define TPC_8__DESIRED_SCALE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_8__DESIRED_SCALE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_8__DESIRED_SCALE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field desired_scale_2 */
#define TPC_8__DESIRED_SCALE_2__SHIFT                                        10
#define TPC_8__DESIRED_SCALE_2__WIDTH                                         5
#define TPC_8__DESIRED_SCALE_2__MASK                                0x00007c00U
#define TPC_8__DESIRED_SCALE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define TPC_8__DESIRED_SCALE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define TPC_8__DESIRED_SCALE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field desired_scale_3 */
#define TPC_8__DESIRED_SCALE_3__SHIFT                                        15
#define TPC_8__DESIRED_SCALE_3__WIDTH                                         5
#define TPC_8__DESIRED_SCALE_3__MASK                                0x000f8000U
#define TPC_8__DESIRED_SCALE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define TPC_8__DESIRED_SCALE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define TPC_8__DESIRED_SCALE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field desired_scale_4 */
#define TPC_8__DESIRED_SCALE_4__SHIFT                                        20
#define TPC_8__DESIRED_SCALE_4__WIDTH                                         5
#define TPC_8__DESIRED_SCALE_4__MASK                                0x01f00000U
#define TPC_8__DESIRED_SCALE_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_8__DESIRED_SCALE_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define TPC_8__DESIRED_SCALE_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field desired_scale_5 */
#define TPC_8__DESIRED_SCALE_5__SHIFT                                        25
#define TPC_8__DESIRED_SCALE_5__WIDTH                                         5
#define TPC_8__DESIRED_SCALE_5__MASK                                0x3e000000U
#define TPC_8__DESIRED_SCALE_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define TPC_8__DESIRED_SCALE_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define TPC_8__DESIRED_SCALE_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))
#define TPC_8__TYPE                                                   u_int32_t
#define TPC_8__READ                                                 0x3fffffffU
#define TPC_8__WRITE                                                0x3fffffffU

#endif /* __TPC_8_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_8 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_8__NUM                         1

/* macros for BlueprintGlobalNameSpace::tpc_9 */
#ifndef __TPC_9_MACRO__
#define __TPC_9_MACRO__

/* macros for field desired_scale_6 */
#define TPC_9__DESIRED_SCALE_6__SHIFT                                         0
#define TPC_9__DESIRED_SCALE_6__WIDTH                                         5
#define TPC_9__DESIRED_SCALE_6__MASK                                0x0000001fU
#define TPC_9__DESIRED_SCALE_6__READ(src)        (u_int32_t)(src) & 0x0000001fU
#define TPC_9__DESIRED_SCALE_6__WRITE(src)     ((u_int32_t)(src) & 0x0000001fU)
#define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_9__DESIRED_SCALE_6__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_7 */
#define TPC_9__DESIRED_SCALE_7__SHIFT                                         5
#define TPC_9__DESIRED_SCALE_7__WIDTH                                         5
#define TPC_9__DESIRED_SCALE_7__MASK                                0x000003e0U
#define TPC_9__DESIRED_SCALE_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_9__DESIRED_SCALE_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_9__DESIRED_SCALE_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field desired_scale_cck */
#define TPC_9__DESIRED_SCALE_CCK__SHIFT                                      10
#define TPC_9__DESIRED_SCALE_CCK__WIDTH                                       5
#define TPC_9__DESIRED_SCALE_CCK__MASK                              0x00007c00U
#define TPC_9__DESIRED_SCALE_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define TPC_9__DESIRED_SCALE_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define TPC_9__DESIRED_SCALE_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field en_pd_dc_offset_thr */
#define TPC_9__EN_PD_DC_OFFSET_THR__SHIFT                                    20
#define TPC_9__EN_PD_DC_OFFSET_THR__WIDTH                                     1
#define TPC_9__EN_PD_DC_OFFSET_THR__MASK                            0x00100000U
#define TPC_9__EN_PD_DC_OFFSET_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define TPC_9__EN_PD_DC_OFFSET_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define TPC_9__EN_PD_DC_OFFSET_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define TPC_9__EN_PD_DC_OFFSET_THR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define TPC_9__EN_PD_DC_OFFSET_THR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field pd_dc_offset_thr */
#define TPC_9__PD_DC_OFFSET_THR__SHIFT                                       21
#define TPC_9__PD_DC_OFFSET_THR__WIDTH                                        6
#define TPC_9__PD_DC_OFFSET_THR__MASK                               0x07e00000U
#define TPC_9__PD_DC_OFFSET_THR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07e00000U) >> 21)
#define TPC_9__PD_DC_OFFSET_THR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x07e00000U)
#define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x07e00000U)
#define TPC_9__PD_DC_OFFSET_THR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x07e00000U)))

/* macros for field wait_caltx_settle */
#define TPC_9__WAIT_CALTX_SETTLE__SHIFT                                      27
#define TPC_9__WAIT_CALTX_SETTLE__WIDTH                                       4
#define TPC_9__WAIT_CALTX_SETTLE__MASK                              0x78000000U
#define TPC_9__WAIT_CALTX_SETTLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x78000000U) >> 27)
#define TPC_9__WAIT_CALTX_SETTLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x78000000U)
#define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define TPC_9__WAIT_CALTX_SETTLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))

/* macros for field disable_pdadc_residual_dc_removal */
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SHIFT                      31
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WIDTH                       1
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MASK              0x80000000U
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TPC_9__TYPE                                                   u_int32_t
#define TPC_9__READ                                                 0xfff07fffU
#define TPC_9__WRITE                                                0xfff07fffU

#endif /* __TPC_9_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_9 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_9__NUM                         1

/* macros for BlueprintGlobalNameSpace::tpc_10 */
#ifndef __TPC_10_MACRO__
#define __TPC_10_MACRO__

/* macros for field desired_scale_ht20_0 */
#define TPC_10__DESIRED_SCALE_HT20_0__SHIFT                                   0
#define TPC_10__DESIRED_SCALE_HT20_0__WIDTH                                   5
#define TPC_10__DESIRED_SCALE_HT20_0__MASK                          0x0000001fU
#define TPC_10__DESIRED_SCALE_HT20_0__READ(src)  (u_int32_t)(src) & 0x0000001fU
#define TPC_10__DESIRED_SCALE_HT20_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_10__DESIRED_SCALE_HT20_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_ht20_1 */
#define TPC_10__DESIRED_SCALE_HT20_1__SHIFT                                   5
#define TPC_10__DESIRED_SCALE_HT20_1__WIDTH                                   5
#define TPC_10__DESIRED_SCALE_HT20_1__MASK                          0x000003e0U
#define TPC_10__DESIRED_SCALE_HT20_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_10__DESIRED_SCALE_HT20_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_10__DESIRED_SCALE_HT20_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field desired_scale_ht20_2 */
#define TPC_10__DESIRED_SCALE_HT20_2__SHIFT                                  10
#define TPC_10__DESIRED_SCALE_HT20_2__WIDTH                                   5
#define TPC_10__DESIRED_SCALE_HT20_2__MASK                          0x00007c00U
#define TPC_10__DESIRED_SCALE_HT20_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define TPC_10__DESIRED_SCALE_HT20_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define TPC_10__DESIRED_SCALE_HT20_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field desired_scale_ht20_3 */
#define TPC_10__DESIRED_SCALE_HT20_3__SHIFT                                  15
#define TPC_10__DESIRED_SCALE_HT20_3__WIDTH                                   5
#define TPC_10__DESIRED_SCALE_HT20_3__MASK                          0x000f8000U
#define TPC_10__DESIRED_SCALE_HT20_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define TPC_10__DESIRED_SCALE_HT20_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define TPC_10__DESIRED_SCALE_HT20_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field desired_scale_ht20_4 */
#define TPC_10__DESIRED_SCALE_HT20_4__SHIFT                                  20
#define TPC_10__DESIRED_SCALE_HT20_4__WIDTH                                   5
#define TPC_10__DESIRED_SCALE_HT20_4__MASK                          0x01f00000U
#define TPC_10__DESIRED_SCALE_HT20_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_10__DESIRED_SCALE_HT20_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define TPC_10__DESIRED_SCALE_HT20_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field desired_scale_ht20_5 */
#define TPC_10__DESIRED_SCALE_HT20_5__SHIFT                                  25
#define TPC_10__DESIRED_SCALE_HT20_5__WIDTH                                   5
#define TPC_10__DESIRED_SCALE_HT20_5__MASK                          0x3e000000U
#define TPC_10__DESIRED_SCALE_HT20_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define TPC_10__DESIRED_SCALE_HT20_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define TPC_10__DESIRED_SCALE_HT20_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))
#define TPC_10__TYPE                                                  u_int32_t
#define TPC_10__READ                                                0x3fffffffU
#define TPC_10__WRITE                                               0x3fffffffU

#endif /* __TPC_10_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_10 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_10__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_11_b0 */
#ifndef __TPC_11_B0_MACRO__
#define __TPC_11_B0_MACRO__

/* macros for field desired_scale_ht20_6 */
#define TPC_11_B0__DESIRED_SCALE_HT20_6__SHIFT                                0
#define TPC_11_B0__DESIRED_SCALE_HT20_6__WIDTH                                5
#define TPC_11_B0__DESIRED_SCALE_HT20_6__MASK                       0x0000001fU
#define TPC_11_B0__DESIRED_SCALE_HT20_6__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define TPC_11_B0__DESIRED_SCALE_HT20_6__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_11_B0__DESIRED_SCALE_HT20_6__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_ht20_7 */
#define TPC_11_B0__DESIRED_SCALE_HT20_7__SHIFT                                5
#define TPC_11_B0__DESIRED_SCALE_HT20_7__WIDTH                                5
#define TPC_11_B0__DESIRED_SCALE_HT20_7__MASK                       0x000003e0U
#define TPC_11_B0__DESIRED_SCALE_HT20_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_11_B0__DESIRED_SCALE_HT20_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_11_B0__DESIRED_SCALE_HT20_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field olpc_gain_delta_0 */
#define TPC_11_B0__OLPC_GAIN_DELTA_0__SHIFT                                  16
#define TPC_11_B0__OLPC_GAIN_DELTA_0__WIDTH                                   8
#define TPC_11_B0__OLPC_GAIN_DELTA_0__MASK                          0x00ff0000U
#define TPC_11_B0__OLPC_GAIN_DELTA_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TPC_11_B0__OLPC_GAIN_DELTA_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TPC_11_B0__OLPC_GAIN_DELTA_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field olpc_gain_delta_0_pal_on */
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__SHIFT                           24
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WIDTH                            8
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MASK                   0xff000000U
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define TPC_11_B0__TYPE                                               u_int32_t
#define TPC_11_B0__READ                                             0xffff03ffU
#define TPC_11_B0__WRITE                                            0xffff03ffU

#endif /* __TPC_11_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_11_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_11_B0__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_12 */
#ifndef __TPC_12_MACRO__
#define __TPC_12_MACRO__

/* macros for field desired_scale_ht40_0 */
#define TPC_12__DESIRED_SCALE_HT40_0__SHIFT                                   0
#define TPC_12__DESIRED_SCALE_HT40_0__WIDTH                                   5
#define TPC_12__DESIRED_SCALE_HT40_0__MASK                          0x0000001fU
#define TPC_12__DESIRED_SCALE_HT40_0__READ(src)  (u_int32_t)(src) & 0x0000001fU
#define TPC_12__DESIRED_SCALE_HT40_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_12__DESIRED_SCALE_HT40_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_ht40_1 */
#define TPC_12__DESIRED_SCALE_HT40_1__SHIFT                                   5
#define TPC_12__DESIRED_SCALE_HT40_1__WIDTH                                   5
#define TPC_12__DESIRED_SCALE_HT40_1__MASK                          0x000003e0U
#define TPC_12__DESIRED_SCALE_HT40_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_12__DESIRED_SCALE_HT40_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_12__DESIRED_SCALE_HT40_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field desired_scale_ht40_2 */
#define TPC_12__DESIRED_SCALE_HT40_2__SHIFT                                  10
#define TPC_12__DESIRED_SCALE_HT40_2__WIDTH                                   5
#define TPC_12__DESIRED_SCALE_HT40_2__MASK                          0x00007c00U
#define TPC_12__DESIRED_SCALE_HT40_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define TPC_12__DESIRED_SCALE_HT40_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define TPC_12__DESIRED_SCALE_HT40_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field desired_scale_ht40_3 */
#define TPC_12__DESIRED_SCALE_HT40_3__SHIFT                                  15
#define TPC_12__DESIRED_SCALE_HT40_3__WIDTH                                   5
#define TPC_12__DESIRED_SCALE_HT40_3__MASK                          0x000f8000U
#define TPC_12__DESIRED_SCALE_HT40_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define TPC_12__DESIRED_SCALE_HT40_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define TPC_12__DESIRED_SCALE_HT40_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field desired_scale_ht40_4 */
#define TPC_12__DESIRED_SCALE_HT40_4__SHIFT                                  20
#define TPC_12__DESIRED_SCALE_HT40_4__WIDTH                                   5
#define TPC_12__DESIRED_SCALE_HT40_4__MASK                          0x01f00000U
#define TPC_12__DESIRED_SCALE_HT40_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_12__DESIRED_SCALE_HT40_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define TPC_12__DESIRED_SCALE_HT40_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field desired_scale_ht40_5 */
#define TPC_12__DESIRED_SCALE_HT40_5__SHIFT                                  25
#define TPC_12__DESIRED_SCALE_HT40_5__WIDTH                                   5
#define TPC_12__DESIRED_SCALE_HT40_5__MASK                          0x3e000000U
#define TPC_12__DESIRED_SCALE_HT40_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define TPC_12__DESIRED_SCALE_HT40_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define TPC_12__DESIRED_SCALE_HT40_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))
#define TPC_12__TYPE                                                  u_int32_t
#define TPC_12__READ                                                0x3fffffffU
#define TPC_12__WRITE                                               0x3fffffffU

#endif /* __TPC_12_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_12 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_12__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_13 */
#ifndef __TPC_13_MACRO__
#define __TPC_13_MACRO__

/* macros for field desired_scale_ht40_6 */
#define TPC_13__DESIRED_SCALE_HT40_6__SHIFT                                   0
#define TPC_13__DESIRED_SCALE_HT40_6__WIDTH                                   5
#define TPC_13__DESIRED_SCALE_HT40_6__MASK                          0x0000001fU
#define TPC_13__DESIRED_SCALE_HT40_6__READ(src)  (u_int32_t)(src) & 0x0000001fU
#define TPC_13__DESIRED_SCALE_HT40_6__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_13__DESIRED_SCALE_HT40_6__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_ht40_7 */
#define TPC_13__DESIRED_SCALE_HT40_7__SHIFT                                   5
#define TPC_13__DESIRED_SCALE_HT40_7__WIDTH                                   5
#define TPC_13__DESIRED_SCALE_HT40_7__MASK                          0x000003e0U
#define TPC_13__DESIRED_SCALE_HT40_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_13__DESIRED_SCALE_HT40_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_13__DESIRED_SCALE_HT40_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))
#define TPC_13__TYPE                                                  u_int32_t
#define TPC_13__READ                                                0x000003ffU
#define TPC_13__WRITE                                               0x000003ffU

#endif /* __TPC_13_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_13 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_13__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_14 */
#ifndef __TPC_14_MACRO__
#define __TPC_14_MACRO__

/* macros for field desired_scale_ht20_8 */
#define TPC_14__DESIRED_SCALE_HT20_8__SHIFT                                   0
#define TPC_14__DESIRED_SCALE_HT20_8__WIDTH                                   5
#define TPC_14__DESIRED_SCALE_HT20_8__MASK                          0x0000001fU
#define TPC_14__DESIRED_SCALE_HT20_8__READ(src)  (u_int32_t)(src) & 0x0000001fU
#define TPC_14__DESIRED_SCALE_HT20_8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_14__DESIRED_SCALE_HT20_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_ht20_9 */
#define TPC_14__DESIRED_SCALE_HT20_9__SHIFT                                   5
#define TPC_14__DESIRED_SCALE_HT20_9__WIDTH                                   5
#define TPC_14__DESIRED_SCALE_HT20_9__MASK                          0x000003e0U
#define TPC_14__DESIRED_SCALE_HT20_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_14__DESIRED_SCALE_HT20_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_14__DESIRED_SCALE_HT20_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field desired_scale_ht20_10 */
#define TPC_14__DESIRED_SCALE_HT20_10__SHIFT                                 10
#define TPC_14__DESIRED_SCALE_HT20_10__WIDTH                                  5
#define TPC_14__DESIRED_SCALE_HT20_10__MASK                         0x00007c00U
#define TPC_14__DESIRED_SCALE_HT20_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define TPC_14__DESIRED_SCALE_HT20_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define TPC_14__DESIRED_SCALE_HT20_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field desired_scale_ht20_11 */
#define TPC_14__DESIRED_SCALE_HT20_11__SHIFT                                 15
#define TPC_14__DESIRED_SCALE_HT20_11__WIDTH                                  5
#define TPC_14__DESIRED_SCALE_HT20_11__MASK                         0x000f8000U
#define TPC_14__DESIRED_SCALE_HT20_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define TPC_14__DESIRED_SCALE_HT20_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define TPC_14__DESIRED_SCALE_HT20_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field desired_scale_ht20_12 */
#define TPC_14__DESIRED_SCALE_HT20_12__SHIFT                                 20
#define TPC_14__DESIRED_SCALE_HT20_12__WIDTH                                  5
#define TPC_14__DESIRED_SCALE_HT20_12__MASK                         0x01f00000U
#define TPC_14__DESIRED_SCALE_HT20_12__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_14__DESIRED_SCALE_HT20_12__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define TPC_14__DESIRED_SCALE_HT20_12__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field desired_scale_ht20_13 */
#define TPC_14__DESIRED_SCALE_HT20_13__SHIFT                                 25
#define TPC_14__DESIRED_SCALE_HT20_13__WIDTH                                  5
#define TPC_14__DESIRED_SCALE_HT20_13__MASK                         0x3e000000U
#define TPC_14__DESIRED_SCALE_HT20_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define TPC_14__DESIRED_SCALE_HT20_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define TPC_14__DESIRED_SCALE_HT20_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))
#define TPC_14__TYPE                                                  u_int32_t
#define TPC_14__READ                                                0x3fffffffU
#define TPC_14__WRITE                                               0x3fffffffU

#endif /* __TPC_14_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_14 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_14__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_15 */
#ifndef __TPC_15_MACRO__
#define __TPC_15_MACRO__

/* macros for field desired_scale_ht40_8 */
#define TPC_15__DESIRED_SCALE_HT40_8__SHIFT                                   0
#define TPC_15__DESIRED_SCALE_HT40_8__WIDTH                                   5
#define TPC_15__DESIRED_SCALE_HT40_8__MASK                          0x0000001fU
#define TPC_15__DESIRED_SCALE_HT40_8__READ(src)  (u_int32_t)(src) & 0x0000001fU
#define TPC_15__DESIRED_SCALE_HT40_8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define TPC_15__DESIRED_SCALE_HT40_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field desired_scale_ht40_9 */
#define TPC_15__DESIRED_SCALE_HT40_9__SHIFT                                   5
#define TPC_15__DESIRED_SCALE_HT40_9__WIDTH                                   5
#define TPC_15__DESIRED_SCALE_HT40_9__MASK                          0x000003e0U
#define TPC_15__DESIRED_SCALE_HT40_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)
#define TPC_15__DESIRED_SCALE_HT40_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000003e0U)
#define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000003e0U)
#define TPC_15__DESIRED_SCALE_HT40_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000003e0U)))

/* macros for field desired_scale_ht40_10 */
#define TPC_15__DESIRED_SCALE_HT40_10__SHIFT                                 10
#define TPC_15__DESIRED_SCALE_HT40_10__WIDTH                                  5
#define TPC_15__DESIRED_SCALE_HT40_10__MASK                         0x00007c00U
#define TPC_15__DESIRED_SCALE_HT40_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)
#define TPC_15__DESIRED_SCALE_HT40_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00007c00U)
#define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define TPC_15__DESIRED_SCALE_HT40_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field desired_scale_ht40_11 */
#define TPC_15__DESIRED_SCALE_HT40_11__SHIFT                                 15
#define TPC_15__DESIRED_SCALE_HT40_11__WIDTH                                  5
#define TPC_15__DESIRED_SCALE_HT40_11__MASK                         0x000f8000U
#define TPC_15__DESIRED_SCALE_HT40_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)
#define TPC_15__DESIRED_SCALE_HT40_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x000f8000U)
#define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x000f8000U)
#define TPC_15__DESIRED_SCALE_HT40_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x000f8000U)))

/* macros for field desired_scale_ht40_12 */
#define TPC_15__DESIRED_SCALE_HT40_12__SHIFT                                 20
#define TPC_15__DESIRED_SCALE_HT40_12__WIDTH                                  5
#define TPC_15__DESIRED_SCALE_HT40_12__MASK                         0x01f00000U
#define TPC_15__DESIRED_SCALE_HT40_12__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_15__DESIRED_SCALE_HT40_12__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define TPC_15__DESIRED_SCALE_HT40_12__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))

/* macros for field desired_scale_ht40_13 */
#define TPC_15__DESIRED_SCALE_HT40_13__SHIFT                                 25
#define TPC_15__DESIRED_SCALE_HT40_13__WIDTH                                  5
#define TPC_15__DESIRED_SCALE_HT40_13__MASK                         0x3e000000U
#define TPC_15__DESIRED_SCALE_HT40_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define TPC_15__DESIRED_SCALE_HT40_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x3e000000U)
#define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x3e000000U)
#define TPC_15__DESIRED_SCALE_HT40_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x3e000000U)))
#define TPC_15__TYPE                                                  u_int32_t
#define TPC_15__READ                                                0x3fffffffU
#define TPC_15__WRITE                                               0x3fffffffU

#endif /* __TPC_15_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_15 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_15__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_16 */
#ifndef __TPC_16_MACRO__
#define __TPC_16_MACRO__

/* macros for field pdadc_par_corr_cck */
#define TPC_16__PDADC_PAR_CORR_CCK__SHIFT                                     8
#define TPC_16__PDADC_PAR_CORR_CCK__WIDTH                                     6
#define TPC_16__PDADC_PAR_CORR_CCK__MASK                            0x00003f00U
#define TPC_16__PDADC_PAR_CORR_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define TPC_16__PDADC_PAR_CORR_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define TPC_16__PDADC_PAR_CORR_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field pdadc_par_corr_ofdm */
#define TPC_16__PDADC_PAR_CORR_OFDM__SHIFT                                   16
#define TPC_16__PDADC_PAR_CORR_OFDM__WIDTH                                    6
#define TPC_16__PDADC_PAR_CORR_OFDM__MASK                           0x003f0000U
#define TPC_16__PDADC_PAR_CORR_OFDM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define TPC_16__PDADC_PAR_CORR_OFDM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define TPC_16__PDADC_PAR_CORR_OFDM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field pdadc_par_corr_ht40 */
#define TPC_16__PDADC_PAR_CORR_HT40__SHIFT                                   24
#define TPC_16__PDADC_PAR_CORR_HT40__WIDTH                                    6
#define TPC_16__PDADC_PAR_CORR_HT40__MASK                           0x3f000000U
#define TPC_16__PDADC_PAR_CORR_HT40__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define TPC_16__PDADC_PAR_CORR_HT40__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define TPC_16__PDADC_PAR_CORR_HT40__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define TPC_16__TYPE                                                  u_int32_t
#define TPC_16__READ                                                0x3f3f3f00U
#define TPC_16__WRITE                                               0x3f3f3f00U

#endif /* __TPC_16_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_16 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_16__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_17 */
#ifndef __TPC_17_MACRO__
#define __TPC_17_MACRO__

/* macros for field enable_pal */
#define TPC_17__ENABLE_PAL__SHIFT                                             0
#define TPC_17__ENABLE_PAL__WIDTH                                             1
#define TPC_17__ENABLE_PAL__MASK                                    0x00000001U
#define TPC_17__ENABLE_PAL__READ(src)            (u_int32_t)(src) & 0x00000001U
#define TPC_17__ENABLE_PAL__WRITE(src)         ((u_int32_t)(src) & 0x00000001U)
#define TPC_17__ENABLE_PAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TPC_17__ENABLE_PAL__VERIFY(src)  (!(((u_int32_t)(src) & ~0x00000001U)))
#define TPC_17__ENABLE_PAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TPC_17__ENABLE_PAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field enable_pal_cck */
#define TPC_17__ENABLE_PAL_CCK__SHIFT                                         1
#define TPC_17__ENABLE_PAL_CCK__WIDTH                                         1
#define TPC_17__ENABLE_PAL_CCK__MASK                                0x00000002U
#define TPC_17__ENABLE_PAL_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define TPC_17__ENABLE_PAL_CCK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define TPC_17__ENABLE_PAL_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define TPC_17__ENABLE_PAL_CCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TPC_17__ENABLE_PAL_CCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field enable_pal_ofdm_20 */
#define TPC_17__ENABLE_PAL_OFDM_20__SHIFT                                     2
#define TPC_17__ENABLE_PAL_OFDM_20__WIDTH                                     1
#define TPC_17__ENABLE_PAL_OFDM_20__MASK                            0x00000004U
#define TPC_17__ENABLE_PAL_OFDM_20__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define TPC_17__ENABLE_PAL_OFDM_20__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define TPC_17__ENABLE_PAL_OFDM_20__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define TPC_17__ENABLE_PAL_OFDM_20__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TPC_17__ENABLE_PAL_OFDM_20__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field enable_pal_ofdm_40 */
#define TPC_17__ENABLE_PAL_OFDM_40__SHIFT                                     3
#define TPC_17__ENABLE_PAL_OFDM_40__WIDTH                                     1
#define TPC_17__ENABLE_PAL_OFDM_40__MASK                            0x00000008U
#define TPC_17__ENABLE_PAL_OFDM_40__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define TPC_17__ENABLE_PAL_OFDM_40__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define TPC_17__ENABLE_PAL_OFDM_40__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define TPC_17__ENABLE_PAL_OFDM_40__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TPC_17__ENABLE_PAL_OFDM_40__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field pal_power_threshold */
#define TPC_17__PAL_POWER_THRESHOLD__SHIFT                                    4
#define TPC_17__PAL_POWER_THRESHOLD__WIDTH                                    6
#define TPC_17__PAL_POWER_THRESHOLD__MASK                           0x000003f0U
#define TPC_17__PAL_POWER_THRESHOLD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define TPC_17__PAL_POWER_THRESHOLD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define TPC_17__PAL_POWER_THRESHOLD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field force_pal_locked */
#define TPC_17__FORCE_PAL_LOCKED__SHIFT                                      10
#define TPC_17__FORCE_PAL_LOCKED__WIDTH                                       1
#define TPC_17__FORCE_PAL_LOCKED__MASK                              0x00000400U
#define TPC_17__FORCE_PAL_LOCKED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define TPC_17__FORCE_PAL_LOCKED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define TPC_17__FORCE_PAL_LOCKED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define TPC_17__FORCE_PAL_LOCKED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define TPC_17__FORCE_PAL_LOCKED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field init_tx_gain_setting_pal_on */
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__SHIFT                           11
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WIDTH                            6
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MASK                   0x0001f800U
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f800U) >> 11)
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x0001f800U)
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f800U) | (((u_int32_t)(src) <<\
                    11) & 0x0001f800U)
#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x0001f800U)))
#define TPC_17__TYPE                                                  u_int32_t
#define TPC_17__READ                                                0x0001ffffU
#define TPC_17__WRITE                                               0x0001ffffU

#endif /* __TPC_17_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_17 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_17__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_18 */
#ifndef __TPC_18_MACRO__
#define __TPC_18_MACRO__

/* macros for field therm_cal_value */
#define TPC_18__THERM_CAL_VALUE__SHIFT                                        0
#define TPC_18__THERM_CAL_VALUE__WIDTH                                        8
#define TPC_18__THERM_CAL_VALUE__MASK                               0x000000ffU
#define TPC_18__THERM_CAL_VALUE__READ(src)       (u_int32_t)(src) & 0x000000ffU
#define TPC_18__THERM_CAL_VALUE__WRITE(src)    ((u_int32_t)(src) & 0x000000ffU)
#define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TPC_18__THERM_CAL_VALUE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field volt_cal_value */
#define TPC_18__VOLT_CAL_VALUE__SHIFT                                         8
#define TPC_18__VOLT_CAL_VALUE__WIDTH                                         8
#define TPC_18__VOLT_CAL_VALUE__MASK                                0x0000ff00U
#define TPC_18__VOLT_CAL_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TPC_18__VOLT_CAL_VALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TPC_18__VOLT_CAL_VALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field use_legacy_tpc */
#define TPC_18__USE_LEGACY_TPC__SHIFT                                        16
#define TPC_18__USE_LEGACY_TPC__WIDTH                                         1
#define TPC_18__USE_LEGACY_TPC__MASK                                0x00010000U
#define TPC_18__USE_LEGACY_TPC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define TPC_18__USE_LEGACY_TPC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define TPC_18__USE_LEGACY_TPC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define TPC_18__USE_LEGACY_TPC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define TPC_18__USE_LEGACY_TPC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field min_power_therm_volt_gain_corr */
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__SHIFT                        17
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WIDTH                         6
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MASK                0x007e0000U
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007e0000U) >> 17)
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x007e0000U)
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x007e0000U)
#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x007e0000U)))
#define TPC_18__TYPE                                                  u_int32_t
#define TPC_18__READ                                                0x007fffffU
#define TPC_18__WRITE                                               0x007fffffU

#endif /* __TPC_18_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_18 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_18__NUM                        1

/* macros for BlueprintGlobalNameSpace::tpc_19_b0 */
#ifndef __TPC_19_B0_MACRO__
#define __TPC_19_B0_MACRO__

/* macros for field alpha_therm_0 */
#define TPC_19_B0__ALPHA_THERM_0__SHIFT                                       0
#define TPC_19_B0__ALPHA_THERM_0__WIDTH                                       8
#define TPC_19_B0__ALPHA_THERM_0__MASK                              0x000000ffU
#define TPC_19_B0__ALPHA_THERM_0__READ(src)      (u_int32_t)(src) & 0x000000ffU
#define TPC_19_B0__ALPHA_THERM_0__WRITE(src)   ((u_int32_t)(src) & 0x000000ffU)
#define TPC_19_B0__ALPHA_THERM_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TPC_19_B0__ALPHA_THERM_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field alpha_therm_pal_on_0 */
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__SHIFT                                8
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WIDTH                                8
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MASK                       0x0000ff00U
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field alpha_volt_0 */
#define TPC_19_B0__ALPHA_VOLT_0__SHIFT                                       16
#define TPC_19_B0__ALPHA_VOLT_0__WIDTH                                        7
#define TPC_19_B0__ALPHA_VOLT_0__MASK                               0x007f0000U
#define TPC_19_B0__ALPHA_VOLT_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)
#define TPC_19_B0__ALPHA_VOLT_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x007f0000U)
#define TPC_19_B0__ALPHA_VOLT_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x007f0000U)
#define TPC_19_B0__ALPHA_VOLT_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x007f0000U)))

/* macros for field alpha_volt_pal_on_0 */
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__SHIFT                                23
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WIDTH                                 7
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MASK                        0x3f800000U
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f800000U) >> 23)
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x3f800000U)
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))
#define TPC_19_B0__TYPE                                               u_int32_t
#define TPC_19_B0__READ                                             0x3fffffffU
#define TPC_19_B0__WRITE                                            0x3fffffffU

#endif /* __TPC_19_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_19_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_19_B0__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_20 */
#ifndef __TPC_20_MACRO__
#define __TPC_20_MACRO__

/* macros for field enable_pal_mcs_0 */
#define TPC_20__ENABLE_PAL_MCS_0__SHIFT                                       0
#define TPC_20__ENABLE_PAL_MCS_0__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_0__MASK                              0x00000001U
#define TPC_20__ENABLE_PAL_MCS_0__READ(src)      (u_int32_t)(src) & 0x00000001U
#define TPC_20__ENABLE_PAL_MCS_0__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
#define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TPC_20__ENABLE_PAL_MCS_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TPC_20__ENABLE_PAL_MCS_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TPC_20__ENABLE_PAL_MCS_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field enable_pal_mcs_1 */
#define TPC_20__ENABLE_PAL_MCS_1__SHIFT                                       1
#define TPC_20__ENABLE_PAL_MCS_1__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_1__MASK                              0x00000002U
#define TPC_20__ENABLE_PAL_MCS_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define TPC_20__ENABLE_PAL_MCS_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define TPC_20__ENABLE_PAL_MCS_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define TPC_20__ENABLE_PAL_MCS_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TPC_20__ENABLE_PAL_MCS_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field enable_pal_mcs_2 */
#define TPC_20__ENABLE_PAL_MCS_2__SHIFT                                       2
#define TPC_20__ENABLE_PAL_MCS_2__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_2__MASK                              0x00000004U
#define TPC_20__ENABLE_PAL_MCS_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define TPC_20__ENABLE_PAL_MCS_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define TPC_20__ENABLE_PAL_MCS_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define TPC_20__ENABLE_PAL_MCS_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TPC_20__ENABLE_PAL_MCS_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field enable_pal_mcs_3 */
#define TPC_20__ENABLE_PAL_MCS_3__SHIFT                                       3
#define TPC_20__ENABLE_PAL_MCS_3__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_3__MASK                              0x00000008U
#define TPC_20__ENABLE_PAL_MCS_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define TPC_20__ENABLE_PAL_MCS_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define TPC_20__ENABLE_PAL_MCS_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define TPC_20__ENABLE_PAL_MCS_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TPC_20__ENABLE_PAL_MCS_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field enable_pal_mcs_4 */
#define TPC_20__ENABLE_PAL_MCS_4__SHIFT                                       4
#define TPC_20__ENABLE_PAL_MCS_4__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_4__MASK                              0x00000010U
#define TPC_20__ENABLE_PAL_MCS_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define TPC_20__ENABLE_PAL_MCS_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define TPC_20__ENABLE_PAL_MCS_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define TPC_20__ENABLE_PAL_MCS_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define TPC_20__ENABLE_PAL_MCS_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field enable_pal_mcs_5 */
#define TPC_20__ENABLE_PAL_MCS_5__SHIFT                                       5
#define TPC_20__ENABLE_PAL_MCS_5__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_5__MASK                              0x00000020U
#define TPC_20__ENABLE_PAL_MCS_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define TPC_20__ENABLE_PAL_MCS_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define TPC_20__ENABLE_PAL_MCS_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define TPC_20__ENABLE_PAL_MCS_5__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define TPC_20__ENABLE_PAL_MCS_5__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field enable_pal_mcs_6 */
#define TPC_20__ENABLE_PAL_MCS_6__SHIFT                                       6
#define TPC_20__ENABLE_PAL_MCS_6__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_6__MASK                              0x00000040U
#define TPC_20__ENABLE_PAL_MCS_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define TPC_20__ENABLE_PAL_MCS_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define TPC_20__ENABLE_PAL_MCS_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define TPC_20__ENABLE_PAL_MCS_6__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define TPC_20__ENABLE_PAL_MCS_6__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field enable_pal_mcs_7 */
#define TPC_20__ENABLE_PAL_MCS_7__SHIFT                                       7
#define TPC_20__ENABLE_PAL_MCS_7__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_7__MASK                              0x00000080U
#define TPC_20__ENABLE_PAL_MCS_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define TPC_20__ENABLE_PAL_MCS_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define TPC_20__ENABLE_PAL_MCS_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define TPC_20__ENABLE_PAL_MCS_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define TPC_20__ENABLE_PAL_MCS_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field enable_pal_mcs_8 */
#define TPC_20__ENABLE_PAL_MCS_8__SHIFT                                       8
#define TPC_20__ENABLE_PAL_MCS_8__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_8__MASK                              0x00000100U
#define TPC_20__ENABLE_PAL_MCS_8__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define TPC_20__ENABLE_PAL_MCS_8__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define TPC_20__ENABLE_PAL_MCS_8__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define TPC_20__ENABLE_PAL_MCS_8__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define TPC_20__ENABLE_PAL_MCS_8__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field enable_pal_mcs_9 */
#define TPC_20__ENABLE_PAL_MCS_9__SHIFT                                       9
#define TPC_20__ENABLE_PAL_MCS_9__WIDTH                                       1
#define TPC_20__ENABLE_PAL_MCS_9__MASK                              0x00000200U
#define TPC_20__ENABLE_PAL_MCS_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define TPC_20__ENABLE_PAL_MCS_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define TPC_20__ENABLE_PAL_MCS_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define TPC_20__ENABLE_PAL_MCS_9__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define TPC_20__ENABLE_PAL_MCS_9__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field enable_pal_mcs_10 */
#define TPC_20__ENABLE_PAL_MCS_10__SHIFT                                     10
#define TPC_20__ENABLE_PAL_MCS_10__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_10__MASK                             0x00000400U
#define TPC_20__ENABLE_PAL_MCS_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define TPC_20__ENABLE_PAL_MCS_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define TPC_20__ENABLE_PAL_MCS_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define TPC_20__ENABLE_PAL_MCS_10__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define TPC_20__ENABLE_PAL_MCS_10__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field enable_pal_mcs_11 */
#define TPC_20__ENABLE_PAL_MCS_11__SHIFT                                     11
#define TPC_20__ENABLE_PAL_MCS_11__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_11__MASK                             0x00000800U
#define TPC_20__ENABLE_PAL_MCS_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define TPC_20__ENABLE_PAL_MCS_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define TPC_20__ENABLE_PAL_MCS_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define TPC_20__ENABLE_PAL_MCS_11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define TPC_20__ENABLE_PAL_MCS_11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field enable_pal_mcs_12 */
#define TPC_20__ENABLE_PAL_MCS_12__SHIFT                                     12
#define TPC_20__ENABLE_PAL_MCS_12__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_12__MASK                             0x00001000U
#define TPC_20__ENABLE_PAL_MCS_12__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define TPC_20__ENABLE_PAL_MCS_12__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define TPC_20__ENABLE_PAL_MCS_12__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define TPC_20__ENABLE_PAL_MCS_12__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define TPC_20__ENABLE_PAL_MCS_12__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field enable_pal_mcs_13 */
#define TPC_20__ENABLE_PAL_MCS_13__SHIFT                                     13
#define TPC_20__ENABLE_PAL_MCS_13__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_13__MASK                             0x00002000U
#define TPC_20__ENABLE_PAL_MCS_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define TPC_20__ENABLE_PAL_MCS_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TPC_20__ENABLE_PAL_MCS_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TPC_20__ENABLE_PAL_MCS_13__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TPC_20__ENABLE_PAL_MCS_13__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field enable_pal_mcs_14 */
#define TPC_20__ENABLE_PAL_MCS_14__SHIFT                                     14
#define TPC_20__ENABLE_PAL_MCS_14__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_14__MASK                             0x00004000U
#define TPC_20__ENABLE_PAL_MCS_14__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define TPC_20__ENABLE_PAL_MCS_14__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define TPC_20__ENABLE_PAL_MCS_14__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define TPC_20__ENABLE_PAL_MCS_14__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define TPC_20__ENABLE_PAL_MCS_14__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field enable_pal_mcs_15 */
#define TPC_20__ENABLE_PAL_MCS_15__SHIFT                                     15
#define TPC_20__ENABLE_PAL_MCS_15__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_15__MASK                             0x00008000U
#define TPC_20__ENABLE_PAL_MCS_15__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TPC_20__ENABLE_PAL_MCS_15__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TPC_20__ENABLE_PAL_MCS_15__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TPC_20__ENABLE_PAL_MCS_15__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TPC_20__ENABLE_PAL_MCS_15__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field enable_pal_mcs_16 */
#define TPC_20__ENABLE_PAL_MCS_16__SHIFT                                     16
#define TPC_20__ENABLE_PAL_MCS_16__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_16__MASK                             0x00010000U
#define TPC_20__ENABLE_PAL_MCS_16__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define TPC_20__ENABLE_PAL_MCS_16__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define TPC_20__ENABLE_PAL_MCS_16__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define TPC_20__ENABLE_PAL_MCS_16__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define TPC_20__ENABLE_PAL_MCS_16__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field enable_pal_mcs_17 */
#define TPC_20__ENABLE_PAL_MCS_17__SHIFT                                     17
#define TPC_20__ENABLE_PAL_MCS_17__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_17__MASK                             0x00020000U
#define TPC_20__ENABLE_PAL_MCS_17__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define TPC_20__ENABLE_PAL_MCS_17__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define TPC_20__ENABLE_PAL_MCS_17__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define TPC_20__ENABLE_PAL_MCS_17__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define TPC_20__ENABLE_PAL_MCS_17__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field enable_pal_mcs_18 */
#define TPC_20__ENABLE_PAL_MCS_18__SHIFT                                     18
#define TPC_20__ENABLE_PAL_MCS_18__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_18__MASK                             0x00040000U
#define TPC_20__ENABLE_PAL_MCS_18__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define TPC_20__ENABLE_PAL_MCS_18__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define TPC_20__ENABLE_PAL_MCS_18__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define TPC_20__ENABLE_PAL_MCS_18__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define TPC_20__ENABLE_PAL_MCS_18__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field enable_pal_mcs_19 */
#define TPC_20__ENABLE_PAL_MCS_19__SHIFT                                     19
#define TPC_20__ENABLE_PAL_MCS_19__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_19__MASK                             0x00080000U
#define TPC_20__ENABLE_PAL_MCS_19__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00080000U) >> 19)
#define TPC_20__ENABLE_PAL_MCS_19__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define TPC_20__ENABLE_PAL_MCS_19__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define TPC_20__ENABLE_PAL_MCS_19__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define TPC_20__ENABLE_PAL_MCS_19__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field enable_pal_mcs_20 */
#define TPC_20__ENABLE_PAL_MCS_20__SHIFT                                     20
#define TPC_20__ENABLE_PAL_MCS_20__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_20__MASK                             0x00100000U
#define TPC_20__ENABLE_PAL_MCS_20__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define TPC_20__ENABLE_PAL_MCS_20__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define TPC_20__ENABLE_PAL_MCS_20__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define TPC_20__ENABLE_PAL_MCS_20__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define TPC_20__ENABLE_PAL_MCS_20__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field enable_pal_mcs_21 */
#define TPC_20__ENABLE_PAL_MCS_21__SHIFT                                     21
#define TPC_20__ENABLE_PAL_MCS_21__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_21__MASK                             0x00200000U
#define TPC_20__ENABLE_PAL_MCS_21__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define TPC_20__ENABLE_PAL_MCS_21__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define TPC_20__ENABLE_PAL_MCS_21__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define TPC_20__ENABLE_PAL_MCS_21__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define TPC_20__ENABLE_PAL_MCS_21__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field enable_pal_mcs_22 */
#define TPC_20__ENABLE_PAL_MCS_22__SHIFT                                     22
#define TPC_20__ENABLE_PAL_MCS_22__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_22__MASK                             0x00400000U
#define TPC_20__ENABLE_PAL_MCS_22__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define TPC_20__ENABLE_PAL_MCS_22__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define TPC_20__ENABLE_PAL_MCS_22__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define TPC_20__ENABLE_PAL_MCS_22__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define TPC_20__ENABLE_PAL_MCS_22__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field enable_pal_mcs_23 */
#define TPC_20__ENABLE_PAL_MCS_23__SHIFT                                     23
#define TPC_20__ENABLE_PAL_MCS_23__WIDTH                                      1
#define TPC_20__ENABLE_PAL_MCS_23__MASK                             0x00800000U
#define TPC_20__ENABLE_PAL_MCS_23__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define TPC_20__ENABLE_PAL_MCS_23__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TPC_20__ENABLE_PAL_MCS_23__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TPC_20__ENABLE_PAL_MCS_23__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TPC_20__ENABLE_PAL_MCS_23__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)
#define TPC_20__TYPE                                                  u_int32_t
#define TPC_20__READ                                                0x00ffffffU
#define TPC_20__WRITE                                               0x00ffffffU

#endif /* __TPC_20_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_20 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_20__NUM                        1

/* macros for BlueprintGlobalNameSpace::therm_adc_1 */
#ifndef __THERM_ADC_1_MACRO__
#define __THERM_ADC_1_MACRO__

/* macros for field init_therm_setting */
#define THERM_ADC_1__INIT_THERM_SETTING__SHIFT                                0
#define THERM_ADC_1__INIT_THERM_SETTING__WIDTH                                8
#define THERM_ADC_1__INIT_THERM_SETTING__MASK                       0x000000ffU
#define THERM_ADC_1__INIT_THERM_SETTING__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define THERM_ADC_1__INIT_THERM_SETTING__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define THERM_ADC_1__INIT_THERM_SETTING__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field init_volt_setting */
#define THERM_ADC_1__INIT_VOLT_SETTING__SHIFT                                 8
#define THERM_ADC_1__INIT_VOLT_SETTING__WIDTH                                 8
#define THERM_ADC_1__INIT_VOLT_SETTING__MASK                        0x0000ff00U
#define THERM_ADC_1__INIT_VOLT_SETTING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define THERM_ADC_1__INIT_VOLT_SETTING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define THERM_ADC_1__INIT_VOLT_SETTING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field init_atb_setting */
#define THERM_ADC_1__INIT_ATB_SETTING__SHIFT                                 16
#define THERM_ADC_1__INIT_ATB_SETTING__WIDTH                                  8
#define THERM_ADC_1__INIT_ATB_SETTING__MASK                         0x00ff0000U
#define THERM_ADC_1__INIT_ATB_SETTING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define THERM_ADC_1__INIT_ATB_SETTING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define THERM_ADC_1__INIT_ATB_SETTING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field samples_cnt_coding */
#define THERM_ADC_1__SAMPLES_CNT_CODING__SHIFT                               24
#define THERM_ADC_1__SAMPLES_CNT_CODING__WIDTH                                2
#define THERM_ADC_1__SAMPLES_CNT_CODING__MASK                       0x03000000U
#define THERM_ADC_1__SAMPLES_CNT_CODING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03000000U) >> 24)
#define THERM_ADC_1__SAMPLES_CNT_CODING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x03000000U)
#define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define THERM_ADC_1__SAMPLES_CNT_CODING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field use_init_therm_volt_atb_after_warm_reset */
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SHIFT         26
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WIDTH          1
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MASK 0x04000000U
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field force_therm_volt_atb_to_init_settings */
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SHIFT            27
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WIDTH             1
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MASK    0x08000000U
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field check_done_for_1st_adc_meas_of_each_frame */
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__SHIFT        28
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WIDTH         1
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MASK \
                    0x10000000U
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field therm_measure_reset */
#define THERM_ADC_1__THERM_MEASURE_RESET__SHIFT                              29
#define THERM_ADC_1__THERM_MEASURE_RESET__WIDTH                               1
#define THERM_ADC_1__THERM_MEASURE_RESET__MASK                      0x20000000U
#define THERM_ADC_1__THERM_MEASURE_RESET__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define THERM_ADC_1__THERM_MEASURE_RESET__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define THERM_ADC_1__THERM_MEASURE_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define THERM_ADC_1__THERM_MEASURE_RESET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define THERM_ADC_1__THERM_MEASURE_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define THERM_ADC_1__THERM_MEASURE_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define THERM_ADC_1__TYPE                                             u_int32_t
#define THERM_ADC_1__READ                                           0x3fffffffU
#define THERM_ADC_1__WRITE                                          0x3fffffffU

#endif /* __THERM_ADC_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_1__NUM                   1

/* macros for BlueprintGlobalNameSpace::therm_adc_2 */
#ifndef __THERM_ADC_2_MACRO__
#define __THERM_ADC_2_MACRO__

/* macros for field measure_therm_freq */
#define THERM_ADC_2__MEASURE_THERM_FREQ__SHIFT                                0
#define THERM_ADC_2__MEASURE_THERM_FREQ__WIDTH                               12
#define THERM_ADC_2__MEASURE_THERM_FREQ__MASK                       0x00000fffU
#define THERM_ADC_2__MEASURE_THERM_FREQ__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU
#define THERM_ADC_2__MEASURE_THERM_FREQ__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000fffU)
#define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define THERM_ADC_2__MEASURE_THERM_FREQ__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field measure_volt_freq */
#define THERM_ADC_2__MEASURE_VOLT_FREQ__SHIFT                                12
#define THERM_ADC_2__MEASURE_VOLT_FREQ__WIDTH                                10
#define THERM_ADC_2__MEASURE_VOLT_FREQ__MASK                        0x003ff000U
#define THERM_ADC_2__MEASURE_VOLT_FREQ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003ff000U) >> 12)
#define THERM_ADC_2__MEASURE_VOLT_FREQ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x003ff000U)
#define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x003ff000U)
#define THERM_ADC_2__MEASURE_VOLT_FREQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x003ff000U)))

/* macros for field measure_atb_freq */
#define THERM_ADC_2__MEASURE_ATB_FREQ__SHIFT                                 22
#define THERM_ADC_2__MEASURE_ATB_FREQ__WIDTH                                 10
#define THERM_ADC_2__MEASURE_ATB_FREQ__MASK                         0xffc00000U
#define THERM_ADC_2__MEASURE_ATB_FREQ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffc00000U) >> 22)
#define THERM_ADC_2__MEASURE_ATB_FREQ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0xffc00000U)
#define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffc00000U) | (((u_int32_t)(src) <<\
                    22) & 0xffc00000U)
#define THERM_ADC_2__MEASURE_ATB_FREQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0xffc00000U)))
#define THERM_ADC_2__TYPE                                             u_int32_t
#define THERM_ADC_2__READ                                           0xffffffffU
#define THERM_ADC_2__WRITE                                          0xffffffffU

#endif /* __THERM_ADC_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_2__NUM                   1

/* macros for BlueprintGlobalNameSpace::therm_adc_3 */
#ifndef __THERM_ADC_3_MACRO__
#define __THERM_ADC_3_MACRO__

/* macros for field therm_adc_offset */
#define THERM_ADC_3__THERM_ADC_OFFSET__SHIFT                                  0
#define THERM_ADC_3__THERM_ADC_OFFSET__WIDTH                                  8
#define THERM_ADC_3__THERM_ADC_OFFSET__MASK                         0x000000ffU
#define THERM_ADC_3__THERM_ADC_OFFSET__READ(src) (u_int32_t)(src) & 0x000000ffU
#define THERM_ADC_3__THERM_ADC_OFFSET__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define THERM_ADC_3__THERM_ADC_OFFSET__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field therm_adc_scaled_gain */
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__SHIFT                             8
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WIDTH                             9
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MASK                    0x0001ff00U
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001ff00U) >> 8)
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0001ff00U)
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0001ff00U)
#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0001ff00U)))

/* macros for field adc_interval */
#define THERM_ADC_3__ADC_INTERVAL__SHIFT                                     17
#define THERM_ADC_3__ADC_INTERVAL__WIDTH                                     13
#define THERM_ADC_3__ADC_INTERVAL__MASK                             0x3ffe0000U
#define THERM_ADC_3__ADC_INTERVAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3ffe0000U) >> 17)
#define THERM_ADC_3__ADC_INTERVAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x3ffe0000U)
#define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3ffe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x3ffe0000U)
#define THERM_ADC_3__ADC_INTERVAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x3ffe0000U)))
#define THERM_ADC_3__TYPE                                             u_int32_t
#define THERM_ADC_3__READ                                           0x3fffffffU
#define THERM_ADC_3__WRITE                                          0x3fffffffU

#endif /* __THERM_ADC_3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_3__NUM                   1

/* macros for BlueprintGlobalNameSpace::therm_adc_4 */
#ifndef __THERM_ADC_4_MACRO__
#define __THERM_ADC_4_MACRO__

/* macros for field latest_therm_value */
#define THERM_ADC_4__LATEST_THERM_VALUE__SHIFT                                0
#define THERM_ADC_4__LATEST_THERM_VALUE__WIDTH                                8
#define THERM_ADC_4__LATEST_THERM_VALUE__MASK                       0x000000ffU
#define THERM_ADC_4__LATEST_THERM_VALUE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU

/* macros for field latest_volt_value */
#define THERM_ADC_4__LATEST_VOLT_VALUE__SHIFT                                 8
#define THERM_ADC_4__LATEST_VOLT_VALUE__WIDTH                                 8
#define THERM_ADC_4__LATEST_VOLT_VALUE__MASK                        0x0000ff00U
#define THERM_ADC_4__LATEST_VOLT_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field latest_atb_value */
#define THERM_ADC_4__LATEST_ATB_VALUE__SHIFT                                 16
#define THERM_ADC_4__LATEST_ATB_VALUE__WIDTH                                  8
#define THERM_ADC_4__LATEST_ATB_VALUE__MASK                         0x00ff0000U
#define THERM_ADC_4__LATEST_ATB_VALUE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field force_therm_chain */
#define THERM_ADC_4__FORCE_THERM_CHAIN__SHIFT                                24
#define THERM_ADC_4__FORCE_THERM_CHAIN__WIDTH                                 1
#define THERM_ADC_4__FORCE_THERM_CHAIN__MASK                        0x01000000U
#define THERM_ADC_4__FORCE_THERM_CHAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define THERM_ADC_4__FORCE_THERM_CHAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define THERM_ADC_4__FORCE_THERM_CHAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define THERM_ADC_4__FORCE_THERM_CHAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define THERM_ADC_4__FORCE_THERM_CHAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define THERM_ADC_4__FORCE_THERM_CHAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field preferred_therm_chain */
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__SHIFT                            25
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__WIDTH                             3
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__MASK                    0x0e000000U
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0e000000U) >> 25)
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x0e000000U)
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x0e000000U)
#define THERM_ADC_4__PREFERRED_THERM_CHAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x0e000000U)))
#define THERM_ADC_4__TYPE                                             u_int32_t
#define THERM_ADC_4__READ                                           0x0fffffffU
#define THERM_ADC_4__WRITE                                          0x0fffffffU

#endif /* __THERM_ADC_4_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_4 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_4__NUM                   1

/* macros for BlueprintGlobalNameSpace::tx_forced_gain */
#ifndef __TX_FORCED_GAIN_MACRO__
#define __TX_FORCED_GAIN_MACRO__

/* macros for field force_tx_gain */
#define TX_FORCED_GAIN__FORCE_TX_GAIN__SHIFT                                  0
#define TX_FORCED_GAIN__FORCE_TX_GAIN__WIDTH                                  1
#define TX_FORCED_GAIN__FORCE_TX_GAIN__MASK                         0x00000001U
#define TX_FORCED_GAIN__FORCE_TX_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U
#define TX_FORCED_GAIN__FORCE_TX_GAIN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TX_FORCED_GAIN__FORCE_TX_GAIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TX_FORCED_GAIN__FORCE_TX_GAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TX_FORCED_GAIN__FORCE_TX_GAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field forced_txbb1dbgain */
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__SHIFT                             1
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WIDTH                             3
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MASK                    0x0000000eU
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000eU) >> 1)
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000000eU)
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field forced_txbb6dbgain */
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__SHIFT                             4
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WIDTH                             2
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MASK                    0x00000030U
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field forced_txmxrgain */
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__SHIFT                               6
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WIDTH                               4
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MASK                      0x000003c0U
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003c0U) >> 6)
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000003c0U)
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000003c0U)
#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000003c0U)))

/* macros for field forced_padrvgnA */
#define TX_FORCED_GAIN__FORCED_PADRVGNA__SHIFT                               10
#define TX_FORCED_GAIN__FORCED_PADRVGNA__WIDTH                                4
#define TX_FORCED_GAIN__FORCED_PADRVGNA__MASK                       0x00003c00U
#define TX_FORCED_GAIN__FORCED_PADRVGNA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003c00U) >> 10)
#define TX_FORCED_GAIN__FORCED_PADRVGNA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00003c00U)
#define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00003c00U)
#define TX_FORCED_GAIN__FORCED_PADRVGNA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00003c00U)))

/* macros for field forced_padrvgnB */
#define TX_FORCED_GAIN__FORCED_PADRVGNB__SHIFT                               14
#define TX_FORCED_GAIN__FORCED_PADRVGNB__WIDTH                                4
#define TX_FORCED_GAIN__FORCED_PADRVGNB__MASK                       0x0003c000U
#define TX_FORCED_GAIN__FORCED_PADRVGNB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003c000U) >> 14)
#define TX_FORCED_GAIN__FORCED_PADRVGNB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0003c000U)
#define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0003c000U)
#define TX_FORCED_GAIN__FORCED_PADRVGNB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0003c000U)))

/* macros for field forced_padrvgnC */
#define TX_FORCED_GAIN__FORCED_PADRVGNC__SHIFT                               18
#define TX_FORCED_GAIN__FORCED_PADRVGNC__WIDTH                                4
#define TX_FORCED_GAIN__FORCED_PADRVGNC__MASK                       0x003c0000U
#define TX_FORCED_GAIN__FORCED_PADRVGNC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003c0000U) >> 18)
#define TX_FORCED_GAIN__FORCED_PADRVGNC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x003c0000U)
#define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x003c0000U)
#define TX_FORCED_GAIN__FORCED_PADRVGNC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x003c0000U)))

/* macros for field forced_padrvgnD */
#define TX_FORCED_GAIN__FORCED_PADRVGND__SHIFT                               22
#define TX_FORCED_GAIN__FORCED_PADRVGND__WIDTH                                2
#define TX_FORCED_GAIN__FORCED_PADRVGND__MASK                       0x00c00000U
#define TX_FORCED_GAIN__FORCED_PADRVGND__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00c00000U) >> 22)
#define TX_FORCED_GAIN__FORCED_PADRVGND__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00c00000U)
#define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x00c00000U)
#define TX_FORCED_GAIN__FORCED_PADRVGND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00c00000U)))

/* macros for field forced_enable_PAL */
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SHIFT                             24
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WIDTH                              1
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MASK                     0x01000000U
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field forced_ob */
#define TX_FORCED_GAIN__FORCED_OB__SHIFT                                     25
#define TX_FORCED_GAIN__FORCED_OB__WIDTH                                      3
#define TX_FORCED_GAIN__FORCED_OB__MASK                             0x0e000000U
#define TX_FORCED_GAIN__FORCED_OB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0e000000U) >> 25)
#define TX_FORCED_GAIN__FORCED_OB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x0e000000U)
#define TX_FORCED_GAIN__FORCED_OB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x0e000000U)
#define TX_FORCED_GAIN__FORCED_OB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x0e000000U)))

/* macros for field forced_db */
#define TX_FORCED_GAIN__FORCED_DB__SHIFT                                     28
#define TX_FORCED_GAIN__FORCED_DB__WIDTH                                      3
#define TX_FORCED_GAIN__FORCED_DB__MASK                             0x70000000U
#define TX_FORCED_GAIN__FORCED_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x70000000U) >> 28)
#define TX_FORCED_GAIN__FORCED_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x70000000U)
#define TX_FORCED_GAIN__FORCED_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x70000000U) | (((u_int32_t)(src) <<\
                    28) & 0x70000000U)
#define TX_FORCED_GAIN__FORCED_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x70000000U)))

/* macros for field forced_green_paprd_enable */
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SHIFT                     31
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WIDTH                      1
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MASK             0x80000000U
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TX_FORCED_GAIN__TYPE                                          u_int32_t
#define TX_FORCED_GAIN__READ                                        0xffffffffU
#define TX_FORCED_GAIN__WRITE                                       0xffffffffU

#endif /* __TX_FORCED_GAIN_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_forced_gain */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_FORCED_GAIN__NUM                1

/* macros for BlueprintGlobalNameSpace::pdadc_tab */
#ifndef __PDADC_TAB_MACRO__
#define __PDADC_TAB_MACRO__

/* macros for field tab_entry */
#define PDADC_TAB__TAB_ENTRY__SHIFT                                           0
#define PDADC_TAB__TAB_ENTRY__WIDTH                                          32
#define PDADC_TAB__TAB_ENTRY__MASK                                  0xffffffffU
#define PDADC_TAB__TAB_ENTRY__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define PDADC_TAB__TYPE                                               u_int32_t
#define PDADC_TAB__WRITE                                            0x00000000U

#endif /* __PDADC_TAB_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_pdadc_tab_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PDADC_TAB_B0__NUM                 32

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_1 */
#ifndef __TX_GAIN_TAB_1_MACRO__
#define __TX_GAIN_TAB_1_MACRO__

/* macros for field tg_table1 */
#define TX_GAIN_TAB_1__TG_TABLE1__SHIFT                                       0
#define TX_GAIN_TAB_1__TG_TABLE1__WIDTH                                      32
#define TX_GAIN_TAB_1__TG_TABLE1__MASK                              0xffffffffU
#define TX_GAIN_TAB_1__TG_TABLE1__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_1__TG_TABLE1__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_1__TG_TABLE1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_1__TYPE                                           u_int32_t
#define TX_GAIN_TAB_1__READ                                         0xffffffffU
#define TX_GAIN_TAB_1__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_1__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_2 */
#ifndef __TX_GAIN_TAB_2_MACRO__
#define __TX_GAIN_TAB_2_MACRO__

/* macros for field tg_table2 */
#define TX_GAIN_TAB_2__TG_TABLE2__SHIFT                                       0
#define TX_GAIN_TAB_2__TG_TABLE2__WIDTH                                      32
#define TX_GAIN_TAB_2__TG_TABLE2__MASK                              0xffffffffU
#define TX_GAIN_TAB_2__TG_TABLE2__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_2__TG_TABLE2__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_2__TG_TABLE2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_2__TYPE                                           u_int32_t
#define TX_GAIN_TAB_2__READ                                         0xffffffffU
#define TX_GAIN_TAB_2__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_2__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_3 */
#ifndef __TX_GAIN_TAB_3_MACRO__
#define __TX_GAIN_TAB_3_MACRO__

/* macros for field tg_table3 */
#define TX_GAIN_TAB_3__TG_TABLE3__SHIFT                                       0
#define TX_GAIN_TAB_3__TG_TABLE3__WIDTH                                      32
#define TX_GAIN_TAB_3__TG_TABLE3__MASK                              0xffffffffU
#define TX_GAIN_TAB_3__TG_TABLE3__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_3__TG_TABLE3__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_3__TG_TABLE3__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_3__TYPE                                           u_int32_t
#define TX_GAIN_TAB_3__READ                                         0xffffffffU
#define TX_GAIN_TAB_3__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_3__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_4 */
#ifndef __TX_GAIN_TAB_4_MACRO__
#define __TX_GAIN_TAB_4_MACRO__

/* macros for field tg_table4 */
#define TX_GAIN_TAB_4__TG_TABLE4__SHIFT                                       0
#define TX_GAIN_TAB_4__TG_TABLE4__WIDTH                                      32
#define TX_GAIN_TAB_4__TG_TABLE4__MASK                              0xffffffffU
#define TX_GAIN_TAB_4__TG_TABLE4__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_4__TG_TABLE4__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_4__TG_TABLE4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_4__TYPE                                           u_int32_t
#define TX_GAIN_TAB_4__READ                                         0xffffffffU
#define TX_GAIN_TAB_4__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_4_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_4 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_4__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_5 */
#ifndef __TX_GAIN_TAB_5_MACRO__
#define __TX_GAIN_TAB_5_MACRO__

/* macros for field tg_table5 */
#define TX_GAIN_TAB_5__TG_TABLE5__SHIFT                                       0
#define TX_GAIN_TAB_5__TG_TABLE5__WIDTH                                      32
#define TX_GAIN_TAB_5__TG_TABLE5__MASK                              0xffffffffU
#define TX_GAIN_TAB_5__TG_TABLE5__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_5__TG_TABLE5__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_5__TG_TABLE5__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_5__TYPE                                           u_int32_t
#define TX_GAIN_TAB_5__READ                                         0xffffffffU
#define TX_GAIN_TAB_5__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_5_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_5 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_5__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_6 */
#ifndef __TX_GAIN_TAB_6_MACRO__
#define __TX_GAIN_TAB_6_MACRO__

/* macros for field tg_table6 */
#define TX_GAIN_TAB_6__TG_TABLE6__SHIFT                                       0
#define TX_GAIN_TAB_6__TG_TABLE6__WIDTH                                      32
#define TX_GAIN_TAB_6__TG_TABLE6__MASK                              0xffffffffU
#define TX_GAIN_TAB_6__TG_TABLE6__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_6__TG_TABLE6__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_6__TG_TABLE6__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_6__TYPE                                           u_int32_t
#define TX_GAIN_TAB_6__READ                                         0xffffffffU
#define TX_GAIN_TAB_6__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_6_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_6 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_6__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_7 */
#ifndef __TX_GAIN_TAB_7_MACRO__
#define __TX_GAIN_TAB_7_MACRO__

/* macros for field tg_table7 */
#define TX_GAIN_TAB_7__TG_TABLE7__SHIFT                                       0
#define TX_GAIN_TAB_7__TG_TABLE7__WIDTH                                      32
#define TX_GAIN_TAB_7__TG_TABLE7__MASK                              0xffffffffU
#define TX_GAIN_TAB_7__TG_TABLE7__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_7__TG_TABLE7__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_7__TG_TABLE7__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_7__TYPE                                           u_int32_t
#define TX_GAIN_TAB_7__READ                                         0xffffffffU
#define TX_GAIN_TAB_7__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_7_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_7 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_7__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_8 */
#ifndef __TX_GAIN_TAB_8_MACRO__
#define __TX_GAIN_TAB_8_MACRO__

/* macros for field tg_table8 */
#define TX_GAIN_TAB_8__TG_TABLE8__SHIFT                                       0
#define TX_GAIN_TAB_8__TG_TABLE8__WIDTH                                      32
#define TX_GAIN_TAB_8__TG_TABLE8__MASK                              0xffffffffU
#define TX_GAIN_TAB_8__TG_TABLE8__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_8__TG_TABLE8__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_8__TG_TABLE8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_8__TYPE                                           u_int32_t
#define TX_GAIN_TAB_8__READ                                         0xffffffffU
#define TX_GAIN_TAB_8__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_8_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_8 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_8__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_9 */
#ifndef __TX_GAIN_TAB_9_MACRO__
#define __TX_GAIN_TAB_9_MACRO__

/* macros for field tg_table9 */
#define TX_GAIN_TAB_9__TG_TABLE9__SHIFT                                       0
#define TX_GAIN_TAB_9__TG_TABLE9__WIDTH                                      32
#define TX_GAIN_TAB_9__TG_TABLE9__MASK                              0xffffffffU
#define TX_GAIN_TAB_9__TG_TABLE9__READ(src)      (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_9__TG_TABLE9__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_9__TG_TABLE9__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_9__TYPE                                           u_int32_t
#define TX_GAIN_TAB_9__READ                                         0xffffffffU
#define TX_GAIN_TAB_9__WRITE                                        0xffffffffU

#endif /* __TX_GAIN_TAB_9_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_9 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_9__NUM                 1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_10 */
#ifndef __TX_GAIN_TAB_10_MACRO__
#define __TX_GAIN_TAB_10_MACRO__

/* macros for field tg_table10 */
#define TX_GAIN_TAB_10__TG_TABLE10__SHIFT                                     0
#define TX_GAIN_TAB_10__TG_TABLE10__WIDTH                                    32
#define TX_GAIN_TAB_10__TG_TABLE10__MASK                            0xffffffffU
#define TX_GAIN_TAB_10__TG_TABLE10__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_10__TG_TABLE10__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_10__TG_TABLE10__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_10__TYPE                                          u_int32_t
#define TX_GAIN_TAB_10__READ                                        0xffffffffU
#define TX_GAIN_TAB_10__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_10_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_10 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_10__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_11 */
#ifndef __TX_GAIN_TAB_11_MACRO__
#define __TX_GAIN_TAB_11_MACRO__

/* macros for field tg_table11 */
#define TX_GAIN_TAB_11__TG_TABLE11__SHIFT                                     0
#define TX_GAIN_TAB_11__TG_TABLE11__WIDTH                                    32
#define TX_GAIN_TAB_11__TG_TABLE11__MASK                            0xffffffffU
#define TX_GAIN_TAB_11__TG_TABLE11__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_11__TG_TABLE11__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_11__TG_TABLE11__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_11__TYPE                                          u_int32_t
#define TX_GAIN_TAB_11__READ                                        0xffffffffU
#define TX_GAIN_TAB_11__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_11_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_11 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_11__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_12 */
#ifndef __TX_GAIN_TAB_12_MACRO__
#define __TX_GAIN_TAB_12_MACRO__

/* macros for field tg_table12 */
#define TX_GAIN_TAB_12__TG_TABLE12__SHIFT                                     0
#define TX_GAIN_TAB_12__TG_TABLE12__WIDTH                                    32
#define TX_GAIN_TAB_12__TG_TABLE12__MASK                            0xffffffffU
#define TX_GAIN_TAB_12__TG_TABLE12__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_12__TG_TABLE12__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_12__TG_TABLE12__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_12__TYPE                                          u_int32_t
#define TX_GAIN_TAB_12__READ                                        0xffffffffU
#define TX_GAIN_TAB_12__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_12_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_12 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_12__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_13 */
#ifndef __TX_GAIN_TAB_13_MACRO__
#define __TX_GAIN_TAB_13_MACRO__

/* macros for field tg_table13 */
#define TX_GAIN_TAB_13__TG_TABLE13__SHIFT                                     0
#define TX_GAIN_TAB_13__TG_TABLE13__WIDTH                                    32
#define TX_GAIN_TAB_13__TG_TABLE13__MASK                            0xffffffffU
#define TX_GAIN_TAB_13__TG_TABLE13__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_13__TG_TABLE13__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_13__TG_TABLE13__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_13__TYPE                                          u_int32_t
#define TX_GAIN_TAB_13__READ                                        0xffffffffU
#define TX_GAIN_TAB_13__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_13_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_13 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_13__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_14 */
#ifndef __TX_GAIN_TAB_14_MACRO__
#define __TX_GAIN_TAB_14_MACRO__

/* macros for field tg_table14 */
#define TX_GAIN_TAB_14__TG_TABLE14__SHIFT                                     0
#define TX_GAIN_TAB_14__TG_TABLE14__WIDTH                                    32
#define TX_GAIN_TAB_14__TG_TABLE14__MASK                            0xffffffffU
#define TX_GAIN_TAB_14__TG_TABLE14__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_14__TG_TABLE14__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_14__TG_TABLE14__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_14__TYPE                                          u_int32_t
#define TX_GAIN_TAB_14__READ                                        0xffffffffU
#define TX_GAIN_TAB_14__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_14_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_14 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_14__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_15 */
#ifndef __TX_GAIN_TAB_15_MACRO__
#define __TX_GAIN_TAB_15_MACRO__

/* macros for field tg_table15 */
#define TX_GAIN_TAB_15__TG_TABLE15__SHIFT                                     0
#define TX_GAIN_TAB_15__TG_TABLE15__WIDTH                                    32
#define TX_GAIN_TAB_15__TG_TABLE15__MASK                            0xffffffffU
#define TX_GAIN_TAB_15__TG_TABLE15__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_15__TG_TABLE15__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_15__TG_TABLE15__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_15__TYPE                                          u_int32_t
#define TX_GAIN_TAB_15__READ                                        0xffffffffU
#define TX_GAIN_TAB_15__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_15_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_15 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_15__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_16 */
#ifndef __TX_GAIN_TAB_16_MACRO__
#define __TX_GAIN_TAB_16_MACRO__

/* macros for field tg_table16 */
#define TX_GAIN_TAB_16__TG_TABLE16__SHIFT                                     0
#define TX_GAIN_TAB_16__TG_TABLE16__WIDTH                                    32
#define TX_GAIN_TAB_16__TG_TABLE16__MASK                            0xffffffffU
#define TX_GAIN_TAB_16__TG_TABLE16__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_16__TG_TABLE16__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_16__TG_TABLE16__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_16__TYPE                                          u_int32_t
#define TX_GAIN_TAB_16__READ                                        0xffffffffU
#define TX_GAIN_TAB_16__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_16_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_16 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_16__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_17 */
#ifndef __TX_GAIN_TAB_17_MACRO__
#define __TX_GAIN_TAB_17_MACRO__

/* macros for field tg_table17 */
#define TX_GAIN_TAB_17__TG_TABLE17__SHIFT                                     0
#define TX_GAIN_TAB_17__TG_TABLE17__WIDTH                                    32
#define TX_GAIN_TAB_17__TG_TABLE17__MASK                            0xffffffffU
#define TX_GAIN_TAB_17__TG_TABLE17__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_17__TG_TABLE17__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_17__TG_TABLE17__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_17__TYPE                                          u_int32_t
#define TX_GAIN_TAB_17__READ                                        0xffffffffU
#define TX_GAIN_TAB_17__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_17_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_17 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_17__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_18 */
#ifndef __TX_GAIN_TAB_18_MACRO__
#define __TX_GAIN_TAB_18_MACRO__

/* macros for field tg_table18 */
#define TX_GAIN_TAB_18__TG_TABLE18__SHIFT                                     0
#define TX_GAIN_TAB_18__TG_TABLE18__WIDTH                                    32
#define TX_GAIN_TAB_18__TG_TABLE18__MASK                            0xffffffffU
#define TX_GAIN_TAB_18__TG_TABLE18__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_18__TG_TABLE18__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_18__TG_TABLE18__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_18__TYPE                                          u_int32_t
#define TX_GAIN_TAB_18__READ                                        0xffffffffU
#define TX_GAIN_TAB_18__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_18_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_18 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_18__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_19 */
#ifndef __TX_GAIN_TAB_19_MACRO__
#define __TX_GAIN_TAB_19_MACRO__

/* macros for field tg_table19 */
#define TX_GAIN_TAB_19__TG_TABLE19__SHIFT                                     0
#define TX_GAIN_TAB_19__TG_TABLE19__WIDTH                                    32
#define TX_GAIN_TAB_19__TG_TABLE19__MASK                            0xffffffffU
#define TX_GAIN_TAB_19__TG_TABLE19__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_19__TG_TABLE19__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_19__TG_TABLE19__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_19__TYPE                                          u_int32_t
#define TX_GAIN_TAB_19__READ                                        0xffffffffU
#define TX_GAIN_TAB_19__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_19_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_19 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_19__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_20 */
#ifndef __TX_GAIN_TAB_20_MACRO__
#define __TX_GAIN_TAB_20_MACRO__

/* macros for field tg_table20 */
#define TX_GAIN_TAB_20__TG_TABLE20__SHIFT                                     0
#define TX_GAIN_TAB_20__TG_TABLE20__WIDTH                                    32
#define TX_GAIN_TAB_20__TG_TABLE20__MASK                            0xffffffffU
#define TX_GAIN_TAB_20__TG_TABLE20__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_20__TG_TABLE20__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_20__TG_TABLE20__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_20__TYPE                                          u_int32_t
#define TX_GAIN_TAB_20__READ                                        0xffffffffU
#define TX_GAIN_TAB_20__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_20_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_20 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_20__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_21 */
#ifndef __TX_GAIN_TAB_21_MACRO__
#define __TX_GAIN_TAB_21_MACRO__

/* macros for field tg_table21 */
#define TX_GAIN_TAB_21__TG_TABLE21__SHIFT                                     0
#define TX_GAIN_TAB_21__TG_TABLE21__WIDTH                                    32
#define TX_GAIN_TAB_21__TG_TABLE21__MASK                            0xffffffffU
#define TX_GAIN_TAB_21__TG_TABLE21__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_21__TG_TABLE21__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_21__TG_TABLE21__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_21__TYPE                                          u_int32_t
#define TX_GAIN_TAB_21__READ                                        0xffffffffU
#define TX_GAIN_TAB_21__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_21_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_21 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_21__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_22 */
#ifndef __TX_GAIN_TAB_22_MACRO__
#define __TX_GAIN_TAB_22_MACRO__

/* macros for field tg_table22 */
#define TX_GAIN_TAB_22__TG_TABLE22__SHIFT                                     0
#define TX_GAIN_TAB_22__TG_TABLE22__WIDTH                                    32
#define TX_GAIN_TAB_22__TG_TABLE22__MASK                            0xffffffffU
#define TX_GAIN_TAB_22__TG_TABLE22__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_22__TG_TABLE22__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_22__TG_TABLE22__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_22__TYPE                                          u_int32_t
#define TX_GAIN_TAB_22__READ                                        0xffffffffU
#define TX_GAIN_TAB_22__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_22_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_22 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_22__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_23 */
#ifndef __TX_GAIN_TAB_23_MACRO__
#define __TX_GAIN_TAB_23_MACRO__

/* macros for field tg_table23 */
#define TX_GAIN_TAB_23__TG_TABLE23__SHIFT                                     0
#define TX_GAIN_TAB_23__TG_TABLE23__WIDTH                                    32
#define TX_GAIN_TAB_23__TG_TABLE23__MASK                            0xffffffffU
#define TX_GAIN_TAB_23__TG_TABLE23__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_23__TG_TABLE23__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_23__TG_TABLE23__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_23__TYPE                                          u_int32_t
#define TX_GAIN_TAB_23__READ                                        0xffffffffU
#define TX_GAIN_TAB_23__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_23_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_23 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_23__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_24 */
#ifndef __TX_GAIN_TAB_24_MACRO__
#define __TX_GAIN_TAB_24_MACRO__

/* macros for field tg_table24 */
#define TX_GAIN_TAB_24__TG_TABLE24__SHIFT                                     0
#define TX_GAIN_TAB_24__TG_TABLE24__WIDTH                                    32
#define TX_GAIN_TAB_24__TG_TABLE24__MASK                            0xffffffffU
#define TX_GAIN_TAB_24__TG_TABLE24__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_24__TG_TABLE24__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_24__TG_TABLE24__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_24__TYPE                                          u_int32_t
#define TX_GAIN_TAB_24__READ                                        0xffffffffU
#define TX_GAIN_TAB_24__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_24_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_24 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_24__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_25 */
#ifndef __TX_GAIN_TAB_25_MACRO__
#define __TX_GAIN_TAB_25_MACRO__

/* macros for field tg_table25 */
#define TX_GAIN_TAB_25__TG_TABLE25__SHIFT                                     0
#define TX_GAIN_TAB_25__TG_TABLE25__WIDTH                                    32
#define TX_GAIN_TAB_25__TG_TABLE25__MASK                            0xffffffffU
#define TX_GAIN_TAB_25__TG_TABLE25__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_25__TG_TABLE25__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_25__TG_TABLE25__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_25__TYPE                                          u_int32_t
#define TX_GAIN_TAB_25__READ                                        0xffffffffU
#define TX_GAIN_TAB_25__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_25_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_25 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_25__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_26 */
#ifndef __TX_GAIN_TAB_26_MACRO__
#define __TX_GAIN_TAB_26_MACRO__

/* macros for field tg_table26 */
#define TX_GAIN_TAB_26__TG_TABLE26__SHIFT                                     0
#define TX_GAIN_TAB_26__TG_TABLE26__WIDTH                                    32
#define TX_GAIN_TAB_26__TG_TABLE26__MASK                            0xffffffffU
#define TX_GAIN_TAB_26__TG_TABLE26__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_26__TG_TABLE26__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_26__TG_TABLE26__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_26__TYPE                                          u_int32_t
#define TX_GAIN_TAB_26__READ                                        0xffffffffU
#define TX_GAIN_TAB_26__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_26_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_26 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_26__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_27 */
#ifndef __TX_GAIN_TAB_27_MACRO__
#define __TX_GAIN_TAB_27_MACRO__

/* macros for field tg_table27 */
#define TX_GAIN_TAB_27__TG_TABLE27__SHIFT                                     0
#define TX_GAIN_TAB_27__TG_TABLE27__WIDTH                                    32
#define TX_GAIN_TAB_27__TG_TABLE27__MASK                            0xffffffffU
#define TX_GAIN_TAB_27__TG_TABLE27__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_27__TG_TABLE27__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_27__TG_TABLE27__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_27__TYPE                                          u_int32_t
#define TX_GAIN_TAB_27__READ                                        0xffffffffU
#define TX_GAIN_TAB_27__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_27_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_27 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_27__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_28 */
#ifndef __TX_GAIN_TAB_28_MACRO__
#define __TX_GAIN_TAB_28_MACRO__

/* macros for field tg_table28 */
#define TX_GAIN_TAB_28__TG_TABLE28__SHIFT                                     0
#define TX_GAIN_TAB_28__TG_TABLE28__WIDTH                                    32
#define TX_GAIN_TAB_28__TG_TABLE28__MASK                            0xffffffffU
#define TX_GAIN_TAB_28__TG_TABLE28__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_28__TG_TABLE28__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_28__TG_TABLE28__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_28__TYPE                                          u_int32_t
#define TX_GAIN_TAB_28__READ                                        0xffffffffU
#define TX_GAIN_TAB_28__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_28_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_28 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_28__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_29 */
#ifndef __TX_GAIN_TAB_29_MACRO__
#define __TX_GAIN_TAB_29_MACRO__

/* macros for field tg_table29 */
#define TX_GAIN_TAB_29__TG_TABLE29__SHIFT                                     0
#define TX_GAIN_TAB_29__TG_TABLE29__WIDTH                                    32
#define TX_GAIN_TAB_29__TG_TABLE29__MASK                            0xffffffffU
#define TX_GAIN_TAB_29__TG_TABLE29__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_29__TG_TABLE29__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_29__TG_TABLE29__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_29__TYPE                                          u_int32_t
#define TX_GAIN_TAB_29__READ                                        0xffffffffU
#define TX_GAIN_TAB_29__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_29_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_29 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_29__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_30 */
#ifndef __TX_GAIN_TAB_30_MACRO__
#define __TX_GAIN_TAB_30_MACRO__

/* macros for field tg_table30 */
#define TX_GAIN_TAB_30__TG_TABLE30__SHIFT                                     0
#define TX_GAIN_TAB_30__TG_TABLE30__WIDTH                                    32
#define TX_GAIN_TAB_30__TG_TABLE30__MASK                            0xffffffffU
#define TX_GAIN_TAB_30__TG_TABLE30__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_30__TG_TABLE30__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_30__TG_TABLE30__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_30__TYPE                                          u_int32_t
#define TX_GAIN_TAB_30__READ                                        0xffffffffU
#define TX_GAIN_TAB_30__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_30_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_30 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_30__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_31 */
#ifndef __TX_GAIN_TAB_31_MACRO__
#define __TX_GAIN_TAB_31_MACRO__

/* macros for field tg_table31 */
#define TX_GAIN_TAB_31__TG_TABLE31__SHIFT                                     0
#define TX_GAIN_TAB_31__TG_TABLE31__WIDTH                                    32
#define TX_GAIN_TAB_31__TG_TABLE31__MASK                            0xffffffffU
#define TX_GAIN_TAB_31__TG_TABLE31__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_31__TG_TABLE31__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_31__TG_TABLE31__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_31__TYPE                                          u_int32_t
#define TX_GAIN_TAB_31__READ                                        0xffffffffU
#define TX_GAIN_TAB_31__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_31_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_31 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_31__NUM                1

/* macros for BlueprintGlobalNameSpace::tx_gain_tab_32 */
#ifndef __TX_GAIN_TAB_32_MACRO__
#define __TX_GAIN_TAB_32_MACRO__

/* macros for field tg_table32 */
#define TX_GAIN_TAB_32__TG_TABLE32__SHIFT                                     0
#define TX_GAIN_TAB_32__TG_TABLE32__WIDTH                                    32
#define TX_GAIN_TAB_32__TG_TABLE32__MASK                            0xffffffffU
#define TX_GAIN_TAB_32__TG_TABLE32__READ(src)    (u_int32_t)(src) & 0xffffffffU
#define TX_GAIN_TAB_32__TG_TABLE32__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
#define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TX_GAIN_TAB_32__TG_TABLE32__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TX_GAIN_TAB_32__TYPE                                          u_int32_t
#define TX_GAIN_TAB_32__READ                                        0xffffffffU
#define TX_GAIN_TAB_32__WRITE                                       0xffffffffU

#endif /* __TX_GAIN_TAB_32_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_32 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_32__NUM                1

/* macros for BlueprintGlobalNameSpace::rtt_ctrl */
#ifndef __RTT_CTRL_MACRO__
#define __RTT_CTRL_MACRO__

/* macros for field ena_radio_retention */
#define RTT_CTRL__ENA_RADIO_RETENTION__SHIFT                                  0
#define RTT_CTRL__ENA_RADIO_RETENTION__WIDTH                                  1
#define RTT_CTRL__ENA_RADIO_RETENTION__MASK                         0x00000001U
#define RTT_CTRL__ENA_RADIO_RETENTION__READ(src) (u_int32_t)(src) & 0x00000001U
#define RTT_CTRL__ENA_RADIO_RETENTION__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTT_CTRL__ENA_RADIO_RETENTION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTT_CTRL__ENA_RADIO_RETENTION__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTT_CTRL__ENA_RADIO_RETENTION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTT_CTRL__ENA_RADIO_RETENTION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field restore_mask */
#define RTT_CTRL__RESTORE_MASK__SHIFT                                         1
#define RTT_CTRL__RESTORE_MASK__WIDTH                                         6
#define RTT_CTRL__RESTORE_MASK__MASK                                0x0000007eU
#define RTT_CTRL__RESTORE_MASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000007eU) >> 1)
#define RTT_CTRL__RESTORE_MASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000007eU)
#define RTT_CTRL__RESTORE_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000007eU)
#define RTT_CTRL__RESTORE_MASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000007eU)))

/* macros for field force_radio_restore */
#define RTT_CTRL__FORCE_RADIO_RESTORE__SHIFT                                  7
#define RTT_CTRL__FORCE_RADIO_RESTORE__WIDTH                                  1
#define RTT_CTRL__FORCE_RADIO_RESTORE__MASK                         0x00000080U
#define RTT_CTRL__FORCE_RADIO_RESTORE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define RTT_CTRL__FORCE_RADIO_RESTORE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define RTT_CTRL__FORCE_RADIO_RESTORE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RTT_CTRL__FORCE_RADIO_RESTORE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define RTT_CTRL__FORCE_RADIO_RESTORE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RTT_CTRL__FORCE_RADIO_RESTORE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)
#define RTT_CTRL__TYPE                                                u_int32_t
#define RTT_CTRL__READ                                              0x000000ffU
#define RTT_CTRL__WRITE                                             0x000000ffU

#endif /* __RTT_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_ctrl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_CTRL__NUM                      1

/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b0 */
#ifndef __RTT_TABLE_SW_INTF_B0_MACRO__
#define __RTT_TABLE_SW_INTF_B0_MACRO__

/* macros for field sw_rtt_table_access_0 */
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__SHIFT                    0
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WIDTH                    1
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MASK           0x00000001U
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field sw_rtt_table_write_0 */
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__SHIFT                     1
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WIDTH                     1
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MASK            0x00000002U
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field sw_rtt_table_addr_0 */
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__SHIFT                      2
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WIDTH                      3
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MASK             0x0000001cU
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))
#define RTT_TABLE_SW_INTF_B0__TYPE                                    u_int32_t
#define RTT_TABLE_SW_INTF_B0__READ                                  0x0000001fU
#define RTT_TABLE_SW_INTF_B0__WRITE                                 0x0000001fU

#endif /* __RTT_TABLE_SW_INTF_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_table_sw_intf_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_TABLE_SW_INTF_B0__NUM          1

/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b0 */
#ifndef __RTT_TABLE_SW_INTF_1_B0_MACRO__
#define __RTT_TABLE_SW_INTF_1_B0_MACRO__

/* macros for field sw_rtt_table_data_0 */
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__SHIFT                    4
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WIDTH                   28
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MASK           0xfffffff0U
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfffffff0U) >> 4)
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0xfffffff0U)
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffff0U) | (((u_int32_t)(src) <<\
                    4) & 0xfffffff0U)
#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0xfffffff0U)))
#define RTT_TABLE_SW_INTF_1_B0__TYPE                                  u_int32_t
#define RTT_TABLE_SW_INTF_1_B0__READ                                0xfffffff0U
#define RTT_TABLE_SW_INTF_1_B0__WRITE                               0xfffffff0U

#endif /* __RTT_TABLE_SW_INTF_1_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_table_sw_intf_1_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B0__NUM        1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_0 */
#ifndef __CALTX_GAIN_SET_0_MACRO__
#define __CALTX_GAIN_SET_0_MACRO__

/* macros for field caltx_gain_set_0 */
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__SHIFT                             0
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WIDTH                            14
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MASK                    0x00003fffU
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_1 */
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__SHIFT                            14
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WIDTH                            14
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MASK                    0x0fffc000U
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_0__TYPE                                        u_int32_t
#define CALTX_GAIN_SET_0__READ                                      0x0fffffffU
#define CALTX_GAIN_SET_0__WRITE                                     0x0fffffffU

#endif /* __CALTX_GAIN_SET_0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_0__NUM              1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_2 */
#ifndef __CALTX_GAIN_SET_2_MACRO__
#define __CALTX_GAIN_SET_2_MACRO__

/* macros for field caltx_gain_set_2 */
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__SHIFT                             0
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WIDTH                            14
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MASK                    0x00003fffU
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_3 */
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__SHIFT                            14
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WIDTH                            14
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MASK                    0x0fffc000U
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_2__TYPE                                        u_int32_t
#define CALTX_GAIN_SET_2__READ                                      0x0fffffffU
#define CALTX_GAIN_SET_2__WRITE                                     0x0fffffffU

#endif /* __CALTX_GAIN_SET_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_2__NUM              1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_4 */
#ifndef __CALTX_GAIN_SET_4_MACRO__
#define __CALTX_GAIN_SET_4_MACRO__

/* macros for field caltx_gain_set_4 */
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__SHIFT                             0
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WIDTH                            14
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MASK                    0x00003fffU
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_5 */
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__SHIFT                            14
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WIDTH                            14
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MASK                    0x0fffc000U
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_4__TYPE                                        u_int32_t
#define CALTX_GAIN_SET_4__READ                                      0x0fffffffU
#define CALTX_GAIN_SET_4__WRITE                                     0x0fffffffU

#endif /* __CALTX_GAIN_SET_4_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_4 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_4__NUM              1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_6 */
#ifndef __CALTX_GAIN_SET_6_MACRO__
#define __CALTX_GAIN_SET_6_MACRO__

/* macros for field caltx_gain_set_6 */
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__SHIFT                             0
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WIDTH                            14
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MASK                    0x00003fffU
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_7 */
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__SHIFT                            14
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WIDTH                            14
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MASK                    0x0fffc000U
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_6__TYPE                                        u_int32_t
#define CALTX_GAIN_SET_6__READ                                      0x0fffffffU
#define CALTX_GAIN_SET_6__WRITE                                     0x0fffffffU

#endif /* __CALTX_GAIN_SET_6_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_6 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_6__NUM              1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_8 */
#ifndef __CALTX_GAIN_SET_8_MACRO__
#define __CALTX_GAIN_SET_8_MACRO__

/* macros for field caltx_gain_set_8 */
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__SHIFT                             0
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WIDTH                            14
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MASK                    0x00003fffU
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_9 */
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__SHIFT                            14
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WIDTH                            14
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MASK                    0x0fffc000U
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_8__TYPE                                        u_int32_t
#define CALTX_GAIN_SET_8__READ                                      0x0fffffffU
#define CALTX_GAIN_SET_8__WRITE                                     0x0fffffffU

#endif /* __CALTX_GAIN_SET_8_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_8 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_8__NUM              1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_10 */
#ifndef __CALTX_GAIN_SET_10_MACRO__
#define __CALTX_GAIN_SET_10_MACRO__

/* macros for field caltx_gain_set_10 */
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__SHIFT                           0
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WIDTH                          14
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MASK                  0x00003fffU
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_11 */
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__SHIFT                          14
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WIDTH                          14
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_10__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_10__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_10__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_10_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_10 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_10__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_12 */
#ifndef __CALTX_GAIN_SET_12_MACRO__
#define __CALTX_GAIN_SET_12_MACRO__

/* macros for field caltx_gain_set_12 */
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__SHIFT                           0
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WIDTH                          14
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MASK                  0x00003fffU
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_13 */
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__SHIFT                          14
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WIDTH                          14
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_12__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_12__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_12__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_12_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_12 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_12__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_14 */
#ifndef __CALTX_GAIN_SET_14_MACRO__
#define __CALTX_GAIN_SET_14_MACRO__

/* macros for field caltx_gain_set_14 */
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__SHIFT                           0
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WIDTH                          14
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MASK                  0x00003fffU
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_15 */
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__SHIFT                          14
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WIDTH                          14
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_14__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_14__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_14__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_14_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_14 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_14__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_16 */
#ifndef __CALTX_GAIN_SET_16_MACRO__
#define __CALTX_GAIN_SET_16_MACRO__

/* macros for field caltx_gain_set_16 */
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__SHIFT                           0
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WIDTH                          14
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MASK                  0x00003fffU
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_17 */
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__SHIFT                          14
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WIDTH                          14
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_16__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_16__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_16__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_16_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_16 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_16__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_18 */
#ifndef __CALTX_GAIN_SET_18_MACRO__
#define __CALTX_GAIN_SET_18_MACRO__

/* macros for field caltx_gain_set_18 */
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__SHIFT                           0
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WIDTH                          14
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MASK                  0x00003fffU
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_19 */
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__SHIFT                          14
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WIDTH                          14
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_18__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_18__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_18__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_18_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_18 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_18__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_20 */
#ifndef __CALTX_GAIN_SET_20_MACRO__
#define __CALTX_GAIN_SET_20_MACRO__

/* macros for field caltx_gain_set_20 */
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__SHIFT                           0
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WIDTH                          14
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MASK                  0x00003fffU
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_21 */
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__SHIFT                          14
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WIDTH                          14
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_20__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_20__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_20__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_20_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_20 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_20__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_22 */
#ifndef __CALTX_GAIN_SET_22_MACRO__
#define __CALTX_GAIN_SET_22_MACRO__

/* macros for field caltx_gain_set_22 */
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__SHIFT                           0
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WIDTH                          14
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MASK                  0x00003fffU
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_23 */
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__SHIFT                          14
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WIDTH                          14
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_22__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_22__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_22__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_22_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_22 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_22__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_24 */
#ifndef __CALTX_GAIN_SET_24_MACRO__
#define __CALTX_GAIN_SET_24_MACRO__

/* macros for field caltx_gain_set_24 */
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__SHIFT                           0
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WIDTH                          14
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MASK                  0x00003fffU
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_25 */
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__SHIFT                          14
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WIDTH                          14
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_24__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_24__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_24__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_24_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_24 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_24__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_26 */
#ifndef __CALTX_GAIN_SET_26_MACRO__
#define __CALTX_GAIN_SET_26_MACRO__

/* macros for field caltx_gain_set_26 */
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__SHIFT                           0
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WIDTH                          14
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MASK                  0x00003fffU
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_27 */
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__SHIFT                          14
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WIDTH                          14
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_26__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_26__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_26__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_26_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_26 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_26__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_28 */
#ifndef __CALTX_GAIN_SET_28_MACRO__
#define __CALTX_GAIN_SET_28_MACRO__

/* macros for field caltx_gain_set_28 */
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__SHIFT                           0
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WIDTH                          14
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MASK                  0x00003fffU
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_29 */
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__SHIFT                          14
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WIDTH                          14
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_28__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_28__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_28__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_28_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_28 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_28__NUM             1

/* macros for BlueprintGlobalNameSpace::caltx_gain_set_30 */
#ifndef __CALTX_GAIN_SET_30_MACRO__
#define __CALTX_GAIN_SET_30_MACRO__

/* macros for field caltx_gain_set_30 */
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__SHIFT                           0
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WIDTH                          14
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MASK                  0x00003fffU
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field caltx_gain_set_31 */
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__SHIFT                          14
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WIDTH                          14
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MASK                  0x0fffc000U
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define CALTX_GAIN_SET_30__TYPE                                       u_int32_t
#define CALTX_GAIN_SET_30__READ                                     0x0fffffffU
#define CALTX_GAIN_SET_30__WRITE                                    0x0fffffffU

#endif /* __CALTX_GAIN_SET_30_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_30 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_30__NUM             1

/* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */
#ifndef __TXIQCAL_CONTROL_0_MACRO__
#define __TXIQCAL_CONTROL_0_MACRO__

/* macros for field iqc_tx_table_sel */
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SHIFT                            0
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WIDTH                            1
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MASK                   0x00000001U
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field base_tx_tone_db */
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__SHIFT                             1
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WIDTH                             6
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MASK                    0x0000007eU
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000007eU) >> 1)
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000007eU)
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000007eU)
#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000007eU)))

/* macros for field max_tx_tone_gain */
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__SHIFT                            7
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WIDTH                            6
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MASK                   0x00001f80U
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f80U) >> 7)
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00001f80U)
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00001f80U)
#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00001f80U)))

/* macros for field min_tx_tone_gain */
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__SHIFT                           13
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WIDTH                            6
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MASK                   0x0007e000U
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0007e000U) >> 13)
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0007e000U)
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0007e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0007e000U)
#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0007e000U)))

/* macros for field caltxshift_delay */
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__SHIFT                           19
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WIDTH                            4
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MASK                   0x00780000U
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00780000U) >> 19)
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00780000U)
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00780000U) | (((u_int32_t)(src) <<\
                    19) & 0x00780000U)
#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00780000U)))

/* macros for field loopback_delay */
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__SHIFT                             23
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WIDTH                              7
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MASK                     0x3f800000U
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f800000U) >> 23)
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x3f800000U)
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))

/* macros for field enable_combined_carr_iq_cal */
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SHIFT                30
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WIDTH                 1
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MASK        0x40000000U
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field enable_txiq_calibrate */
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT                      31
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH                       1
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK              0x80000000U
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TXIQCAL_CONTROL_0__TYPE                                       u_int32_t
#define TXIQCAL_CONTROL_0__READ                                     0xffffffffU
#define TXIQCAL_CONTROL_0__WRITE                                    0xffffffffU

#endif /* __TXIQCAL_CONTROL_0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_0__NUM             1

/* macros for BlueprintGlobalNameSpace::txiqcal_control_1 */
#ifndef __TXIQCAL_CONTROL_1_MACRO__
#define __TXIQCAL_CONTROL_1_MACRO__

/* macros for field rx_init_gain_db */
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__SHIFT                             0
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WIDTH                             6
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MASK                    0x0000003fU
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field max_rx_gain_db */
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__SHIFT                              6
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WIDTH                              6
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MASK                     0x00000fc0U
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field min_rx_gain_db */
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__SHIFT                             12
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WIDTH                              6
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MASK                     0x0003f000U
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field iqcorr_i_q_coff_delpt */
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__SHIFT                      18
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WIDTH                       7
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MASK              0x01fc0000U
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fc0000U) >> 18)
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x01fc0000U)
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x01fc0000U)
#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x01fc0000U)))
#define TXIQCAL_CONTROL_1__TYPE                                       u_int32_t
#define TXIQCAL_CONTROL_1__READ                                     0x01ffffffU
#define TXIQCAL_CONTROL_1__WRITE                                    0x01ffffffU

#endif /* __TXIQCAL_CONTROL_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_1__NUM             1

/* macros for BlueprintGlobalNameSpace::txiqcal_control_2 */
#ifndef __TXIQCAL_CONTROL_2_MACRO__
#define __TXIQCAL_CONTROL_2_MACRO__

/* macros for field iqc_forced_pagain */
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__SHIFT                           0
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WIDTH                           4
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MASK                  0x0000000fU
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field iqcal_min_tx_gain */
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__SHIFT                           4
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WIDTH                           5
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MASK                  0x000001f0U
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001f0U) >> 4)
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000001f0U)
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000001f0U)
#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000001f0U)))

/* macros for field iqcal_max_tx_gain */
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__SHIFT                           9
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WIDTH                           5
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MASK                  0x00003e00U
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003e00U) >> 9)
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00003e00U)
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00003e00U)
#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00003e00U)))
#define TXIQCAL_CONTROL_2__TYPE                                       u_int32_t
#define TXIQCAL_CONTROL_2__READ                                     0x00003fffU
#define TXIQCAL_CONTROL_2__WRITE                                    0x00003fffU

#endif /* __TXIQCAL_CONTROL_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_2__NUM             1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b0 */
#ifndef __TXIQ_CORR_COEFF_01_B0_MACRO__
#define __TXIQ_CORR_COEFF_01_B0_MACRO__

/* macros for field iqc_coeff_table_0_0 */
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__SHIFT                     0
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WIDTH                    14
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_1_0 */
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__SHIFT                    14
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WIDTH                    14
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_01_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_01_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_01_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_01_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_01_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_01_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b0 */
#ifndef __TXIQ_CORR_COEFF_23_B0_MACRO__
#define __TXIQ_CORR_COEFF_23_B0_MACRO__

/* macros for field iqc_coeff_table_2_0 */
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__SHIFT                     0
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WIDTH                    14
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_3_0 */
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__SHIFT                    14
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WIDTH                    14
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_23_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_23_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_23_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_23_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_23_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_23_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b0 */
#ifndef __TXIQ_CORR_COEFF_45_B0_MACRO__
#define __TXIQ_CORR_COEFF_45_B0_MACRO__

/* macros for field iqc_coeff_table_4_0 */
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__SHIFT                     0
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WIDTH                    14
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_5_0 */
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__SHIFT                    14
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WIDTH                    14
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_45_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_45_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_45_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_45_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_45_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_45_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b0 */
#ifndef __TXIQ_CORR_COEFF_67_B0_MACRO__
#define __TXIQ_CORR_COEFF_67_B0_MACRO__

/* macros for field iqc_coeff_table_6_0 */
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__SHIFT                     0
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WIDTH                    14
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_7_0 */
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__SHIFT                    14
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WIDTH                    14
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_67_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_67_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_67_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_67_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_67_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_67_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b0 */
#ifndef __TXIQ_CORR_COEFF_89_B0_MACRO__
#define __TXIQ_CORR_COEFF_89_B0_MACRO__

/* macros for field iqc_coeff_table_8_0 */
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__SHIFT                     0
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WIDTH                    14
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_9_0 */
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__SHIFT                    14
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WIDTH                    14
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_89_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_89_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_89_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_89_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_89_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_89_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b0 */
#ifndef __TXIQ_CORR_COEFF_AB_B0_MACRO__
#define __TXIQ_CORR_COEFF_AB_B0_MACRO__

/* macros for field iqc_coeff_table_a_0 */
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__SHIFT                     0
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WIDTH                    14
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_b_0 */
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__SHIFT                    14
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WIDTH                    14
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_AB_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_AB_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_AB_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_AB_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_ab_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b0 */
#ifndef __TXIQ_CORR_COEFF_CD_B0_MACRO__
#define __TXIQ_CORR_COEFF_CD_B0_MACRO__

/* macros for field iqc_coeff_table_c_0 */
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__SHIFT                     0
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WIDTH                    14
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_d_0 */
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__SHIFT                    14
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WIDTH                    14
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_CD_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_CD_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_CD_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_CD_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_cd_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b0 */
#ifndef __TXIQ_CORR_COEFF_EF_B0_MACRO__
#define __TXIQ_CORR_COEFF_EF_B0_MACRO__

/* macros for field iqc_coeff_table_e_0 */
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__SHIFT                     0
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WIDTH                    14
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_f_0 */
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__SHIFT                    14
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WIDTH                    14
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_EF_B0__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_EF_B0__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_EF_B0__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_EF_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_ef_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B0__NUM         1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_0 */
#ifndef __CAL_RXBB_GAIN_TBL_0_MACRO__
#define __CAL_RXBB_GAIN_TBL_0_MACRO__

/* macros for field txcal_rx_bb_gain_table_0 */
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__SHIFT                  0
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MASK         0x000000ffU
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txcal_rx_bb_gain_table_1 */
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__SHIFT                  8
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MASK         0x0000ff00U
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txcal_rx_bb_gain_table_2 */
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__SHIFT                 16
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MASK         0x00ff0000U
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txcal_rx_bb_gain_table_3 */
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__SHIFT                 24
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MASK         0xff000000U
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define CAL_RXBB_GAIN_TBL_0__TYPE                                     u_int32_t
#define CAL_RXBB_GAIN_TBL_0__READ                                   0xffffffffU
#define CAL_RXBB_GAIN_TBL_0__WRITE                                  0xffffffffU

#endif /* __CAL_RXBB_GAIN_TBL_0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_0__NUM           1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_4 */
#ifndef __CAL_RXBB_GAIN_TBL_4_MACRO__
#define __CAL_RXBB_GAIN_TBL_4_MACRO__

/* macros for field txcal_rx_bb_gain_table_4 */
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__SHIFT                  0
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MASK         0x000000ffU
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txcal_rx_bb_gain_table_5 */
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__SHIFT                  8
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MASK         0x0000ff00U
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txcal_rx_bb_gain_table_6 */
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__SHIFT                 16
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MASK         0x00ff0000U
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txcal_rx_bb_gain_table_7 */
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__SHIFT                 24
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MASK         0xff000000U
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define CAL_RXBB_GAIN_TBL_4__TYPE                                     u_int32_t
#define CAL_RXBB_GAIN_TBL_4__READ                                   0xffffffffU
#define CAL_RXBB_GAIN_TBL_4__WRITE                                  0xffffffffU

#endif /* __CAL_RXBB_GAIN_TBL_4_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_4 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_4__NUM           1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_8 */
#ifndef __CAL_RXBB_GAIN_TBL_8_MACRO__
#define __CAL_RXBB_GAIN_TBL_8_MACRO__

/* macros for field txcal_rx_bb_gain_table_8 */
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__SHIFT                  0
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MASK         0x000000ffU
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txcal_rx_bb_gain_table_9 */
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__SHIFT                  8
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WIDTH                  8
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MASK         0x0000ff00U
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txcal_rx_bb_gain_table_10 */
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__SHIFT                16
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WIDTH                 8
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MASK        0x00ff0000U
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txcal_rx_bb_gain_table_11 */
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__SHIFT                24
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WIDTH                 8
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MASK        0xff000000U
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define CAL_RXBB_GAIN_TBL_8__TYPE                                     u_int32_t
#define CAL_RXBB_GAIN_TBL_8__READ                                   0xffffffffU
#define CAL_RXBB_GAIN_TBL_8__WRITE                                  0xffffffffU

#endif /* __CAL_RXBB_GAIN_TBL_8_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_8 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_8__NUM           1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_12 */
#ifndef __CAL_RXBB_GAIN_TBL_12_MACRO__
#define __CAL_RXBB_GAIN_TBL_12_MACRO__

/* macros for field txcal_rx_bb_gain_table_12 */
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__SHIFT                0
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WIDTH                8
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MASK       0x000000ffU
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txcal_rx_bb_gain_table_13 */
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__SHIFT                8
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WIDTH                8
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MASK       0x0000ff00U
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txcal_rx_bb_gain_table_14 */
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__SHIFT               16
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WIDTH                8
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MASK       0x00ff0000U
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txcal_rx_bb_gain_table_15 */
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__SHIFT               24
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WIDTH                8
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MASK       0xff000000U
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define CAL_RXBB_GAIN_TBL_12__TYPE                                    u_int32_t
#define CAL_RXBB_GAIN_TBL_12__READ                                  0xffffffffU
#define CAL_RXBB_GAIN_TBL_12__WRITE                                 0xffffffffU

#endif /* __CAL_RXBB_GAIN_TBL_12_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_12 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_12__NUM          1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_16 */
#ifndef __CAL_RXBB_GAIN_TBL_16_MACRO__
#define __CAL_RXBB_GAIN_TBL_16_MACRO__

/* macros for field txcal_rx_bb_gain_table_16 */
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__SHIFT                0
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WIDTH                8
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MASK       0x000000ffU
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txcal_rx_bb_gain_table_17 */
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__SHIFT                8
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WIDTH                8
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MASK       0x0000ff00U
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txcal_rx_bb_gain_table_18 */
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__SHIFT               16
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WIDTH                8
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MASK       0x00ff0000U
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txcal_rx_bb_gain_table_19 */
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__SHIFT               24
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WIDTH                8
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MASK       0xff000000U
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define CAL_RXBB_GAIN_TBL_16__TYPE                                    u_int32_t
#define CAL_RXBB_GAIN_TBL_16__READ                                  0xffffffffU
#define CAL_RXBB_GAIN_TBL_16__WRITE                                 0xffffffffU

#endif /* __CAL_RXBB_GAIN_TBL_16_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_16 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_16__NUM          1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_20 */
#ifndef __CAL_RXBB_GAIN_TBL_20_MACRO__
#define __CAL_RXBB_GAIN_TBL_20_MACRO__

/* macros for field txcal_rx_bb_gain_table_20 */
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__SHIFT                0
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WIDTH                8
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MASK       0x000000ffU
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field txcal_rx_bb_gain_table_21 */
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__SHIFT                8
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WIDTH                8
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MASK       0x0000ff00U
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field txcal_rx_bb_gain_table_22 */
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__SHIFT               16
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WIDTH                8
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MASK       0x00ff0000U
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field txcal_rx_bb_gain_table_23 */
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__SHIFT               24
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WIDTH                8
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MASK       0xff000000U
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define CAL_RXBB_GAIN_TBL_20__TYPE                                    u_int32_t
#define CAL_RXBB_GAIN_TBL_20__READ                                  0xffffffffU
#define CAL_RXBB_GAIN_TBL_20__WRITE                                 0xffffffffU

#endif /* __CAL_RXBB_GAIN_TBL_20_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_20 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_20__NUM          1

/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_24 */
#ifndef __CAL_RXBB_GAIN_TBL_24_MACRO__
#define __CAL_RXBB_GAIN_TBL_24_MACRO__

/* macros for field txcal_rx_bb_gain_table_24 */
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__SHIFT                0
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WIDTH                8
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MASK       0x000000ffU
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))
#define CAL_RXBB_GAIN_TBL_24__TYPE                                    u_int32_t
#define CAL_RXBB_GAIN_TBL_24__READ                                  0x000000ffU
#define CAL_RXBB_GAIN_TBL_24__WRITE                                 0x000000ffU

#endif /* __CAL_RXBB_GAIN_TBL_24_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_24 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_24__NUM          1

/* macros for BlueprintGlobalNameSpace::txiqcal_status_b0 */
#ifndef __TXIQCAL_STATUS_B0_MACRO__
#define __TXIQCAL_STATUS_B0_MACRO__

/* macros for field txiqcal_failed_0 */
#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SHIFT                            0
#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__WIDTH                            1
#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__MASK                   0x00000001U
#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field calibrated_gains_0 */
#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__SHIFT                          1
#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__WIDTH                          5
#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__MASK                 0x0000003eU
#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003eU) >> 1)

/* macros for field tone_gain_used_0 */
#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__SHIFT                            6
#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__WIDTH                            6
#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__MASK                   0x00000fc0U
#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)

/* macros for field rx_gain_used_0 */
#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__SHIFT                             12
#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__WIDTH                              6
#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__MASK                     0x0003f000U
#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)

/* macros for field last_meas_addr_0 */
#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__SHIFT                           18
#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__WIDTH                            6
#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__MASK                   0x00fc0000U
#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define TXIQCAL_STATUS_B0__TYPE                                       u_int32_t
#define TXIQCAL_STATUS_B0__READ                                     0x00ffffffU

#endif /* __TXIQCAL_STATUS_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_status_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_STATUS_B0__NUM             1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl1 */
#ifndef __PAPRD_TRAINER_CNTL1_MACRO__
#define __PAPRD_TRAINER_CNTL1_MACRO__

/* macros for field cf_paprd_train_enable */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SHIFT                     0
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WIDTH                     1
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MASK            0x00000001U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cf_paprd_agc2_settling */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__SHIFT                    1
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WIDTH                    7
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MASK           0x000000feU
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000feU) >> 1)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000000feU)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000feU) | (((u_int32_t)(src) <<\
                    1) & 0x000000feU)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000000feU)))

/* macros for field cf_paprd_iqcorr_enable */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SHIFT                    8
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WIDTH                    1
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MASK           0x00000100U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field cf_paprd_rx_bb_gain_force */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SHIFT                 9
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WIDTH                 1
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MASK        0x00000200U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field cf_paprd_tx_gain_force */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SHIFT                   10
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WIDTH                    1
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MASK           0x00000400U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field cf_paprd_lb_enable */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SHIFT                       11
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WIDTH                        1
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MASK               0x00000800U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field cf_paprd_lb_skip */
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__SHIFT                         12
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WIDTH                          7
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MASK                 0x0007f000U
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0007f000U) >> 12)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0007f000U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0007f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0007f000U)
#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0007f000U)))
#define PAPRD_TRAINER_CNTL1__TYPE                                     u_int32_t
#define PAPRD_TRAINER_CNTL1__READ                                   0x0007ffffU
#define PAPRD_TRAINER_CNTL1__WRITE                                  0x0007ffffU

#endif /* __PAPRD_TRAINER_CNTL1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL1__NUM           1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl2 */
#ifndef __PAPRD_TRAINER_CNTL2_MACRO__
#define __PAPRD_TRAINER_CNTL2_MACRO__

/* macros for field cf_paprd_init_rx_bb_gain */
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__SHIFT                  0
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WIDTH                 32
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MASK         0xffffffffU
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define PAPRD_TRAINER_CNTL2__TYPE                                     u_int32_t
#define PAPRD_TRAINER_CNTL2__READ                                   0xffffffffU
#define PAPRD_TRAINER_CNTL2__WRITE                                  0xffffffffU

#endif /* __PAPRD_TRAINER_CNTL2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL2__NUM           1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl3 */
#ifndef __PAPRD_TRAINER_CNTL3_MACRO__
#define __PAPRD_TRAINER_CNTL3_MACRO__

/* macros for field cf_paprd_adc_desired_size */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__SHIFT                 0
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WIDTH                 6
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MASK        0x0000003fU
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field cf_paprd_quick_drop */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__SHIFT                       6
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WIDTH                       6
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MASK              0x00000fc0U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field cf_paprd_min_loopback_del */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__SHIFT                12
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WIDTH                 5
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MASK        0x0001f000U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field cf_paprd_num_corr_stages */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__SHIFT                 17
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WIDTH                  3
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MASK         0x000e0000U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000e0000U) >> 17)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x000e0000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field cf_paprd_coarse_corr_len */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__SHIFT                 20
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WIDTH                  4
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MASK         0x00f00000U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00f00000U) >> 20)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00f00000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x00f00000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field cf_paprd_fine_corr_len */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__SHIFT                   24
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WIDTH                    4
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MASK           0x0f000000U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f000000U) >> 24)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x0f000000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x0f000000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field cf_paprd_reuse_corr */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SHIFT                      28
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WIDTH                       1
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MASK              0x10000000U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field cf_paprd_bbtxmix_disable */
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SHIFT                 29
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WIDTH                  1
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MASK         0x20000000U
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)
#define PAPRD_TRAINER_CNTL3__TYPE                                     u_int32_t
#define PAPRD_TRAINER_CNTL3__READ                                   0x3fffffffU
#define PAPRD_TRAINER_CNTL3__WRITE                                  0x3fffffffU

#endif /* __PAPRD_TRAINER_CNTL3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL3__NUM           1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl4 */
#ifndef __PAPRD_TRAINER_CNTL4_MACRO__
#define __PAPRD_TRAINER_CNTL4_MACRO__

/* macros for field cf_paprd_min_corr */
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__SHIFT                         0
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WIDTH                        12
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MASK                0x00000fffU
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000fffU
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000fffU)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((u_int32_t)(src) &\
                    0x00000fffU)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field cf_paprd_safety_delta */
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__SHIFT                    12
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WIDTH                     4
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MASK            0x0000f000U
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field cf_paprd_num_train_samples */
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__SHIFT               16
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WIDTH               10
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MASK       0x03ff0000U
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03ff0000U) >> 16)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x03ff0000U)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x03ff0000U)
#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x03ff0000U)))
#define PAPRD_TRAINER_CNTL4__TYPE                                     u_int32_t
#define PAPRD_TRAINER_CNTL4__READ                                   0x03ffffffU
#define PAPRD_TRAINER_CNTL4__WRITE                                  0x03ffffffU

#endif /* __PAPRD_TRAINER_CNTL4_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl4 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL4__NUM           1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat1 */
#ifndef __PAPRD_TRAINER_STAT1_MACRO__
#define __PAPRD_TRAINER_STAT1_MACRO__

/* macros for field paprd_train_done */
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SHIFT                          0
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WIDTH                          1
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MASK                 0x00000001U
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_train_incomplete */
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SHIFT                    1
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__WIDTH                    1
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__MASK           0x00000002U
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_corr_err */
#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SHIFT                            2
#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__WIDTH                            1
#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__MASK                   0x00000004U
#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field paprd_train_active */
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SHIFT                        3
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__WIDTH                        1
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__MASK               0x00000008U
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field paprd_rx_gain_idx */
#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__SHIFT                         4
#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__WIDTH                         5
#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__MASK                0x000001f0U
#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001f0U) >> 4)

/* macros for field paprd_agc2_pwr */
#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__SHIFT                            9
#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__WIDTH                            8
#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__MASK                   0x0001fe00U
#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fe00U) >> 9)
#define PAPRD_TRAINER_STAT1__TYPE                                     u_int32_t
#define PAPRD_TRAINER_STAT1__READ                                   0x0001ffffU
#define PAPRD_TRAINER_STAT1__WRITE                                  0x0001ffffU

#endif /* __PAPRD_TRAINER_STAT1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT1__NUM           1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat2 */
#ifndef __PAPRD_TRAINER_STAT2_MACRO__
#define __PAPRD_TRAINER_STAT2_MACRO__

/* macros for field paprd_fine_val */
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__SHIFT                            0
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__WIDTH                           16
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__MASK                   0x0000ffffU
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000ffffU

/* macros for field paprd_coarse_idx */
#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__SHIFT                         16
#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__WIDTH                          5
#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__MASK                 0x001f0000U
#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)

/* macros for field paprd_fine_idx */
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__SHIFT                           21
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__WIDTH                            2
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__MASK                   0x00600000U
#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00600000U) >> 21)
#define PAPRD_TRAINER_STAT2__TYPE                                     u_int32_t
#define PAPRD_TRAINER_STAT2__READ                                   0x007fffffU

#endif /* __PAPRD_TRAINER_STAT2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT2__NUM           1

/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat3 */
#ifndef __PAPRD_TRAINER_STAT3_MACRO__
#define __PAPRD_TRAINER_STAT3_MACRO__

/* macros for field paprd_train_samples_cnt */
#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__SHIFT                   0
#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__WIDTH                  20
#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__MASK          0x000fffffU
#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000fffffU
#define PAPRD_TRAINER_STAT3__TYPE                                     u_int32_t
#define PAPRD_TRAINER_STAT3__READ                                   0x000fffffU

#endif /* __PAPRD_TRAINER_STAT3_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat3 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT3__NUM           1

/* macros for BlueprintGlobalNameSpace::watchdog_status */
#ifndef __WATCHDOG_STATUS_MACRO__
#define __WATCHDOG_STATUS_MACRO__

/* macros for field watchdog_status_1 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__SHIFT                             0
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WIDTH                             3
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MASK                    0x00000007U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000007U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000007U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field watchdog_timeout */
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SHIFT                              3
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WIDTH                              1
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MASK                     0x00000008U
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field watchdog_status_2 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__SHIFT                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MASK                    0x000000f0U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field watchdog_status_3 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__SHIFT                             8
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MASK                    0x00000f00U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field watchdog_status_4 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__SHIFT                            12
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MASK                    0x0000f000U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field watchdog_status_5 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__SHIFT                            16
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MASK                    0x000f0000U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field watchdog_status_6 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__SHIFT                            20
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MASK                    0x00f00000U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00f00000U) >> 20)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00f00000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x00f00000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field watchdog_status_7 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__SHIFT                            24
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MASK                    0x0f000000U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0f000000U) >> 24)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x0f000000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x0f000000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field watchdog_status_8 */
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__SHIFT                            28
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WIDTH                             4
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MASK                    0xf0000000U
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf0000000U) >> 28)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0xf0000000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((u_int32_t)(src) <<\
                    28) & 0xf0000000U)
#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define WATCHDOG_STATUS__TYPE                                         u_int32_t
#define WATCHDOG_STATUS__READ                                       0xffffffffU
#define WATCHDOG_STATUS__WRITE                                      0xffffffffU

#endif /* __WATCHDOG_STATUS_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_status */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_STATUS__NUM               1

/* macros for BlueprintGlobalNameSpace::watchdog_ctrl_1 */
#ifndef __WATCHDOG_CTRL_1_MACRO__
#define __WATCHDOG_CTRL_1_MACRO__

/* macros for field enable_watchdog_timeout_reset_non_idle */
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__SHIFT        0
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WIDTH        1
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MASK \
                    0x00000001U
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field enable_watchdog_timeout_reset_idle */
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__SHIFT            1
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WIDTH            1
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MASK   0x00000002U
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field watchdog_timeout_reset_non_idle_limit */
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__SHIFT         2
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WIDTH        14
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MASK \
                    0x0000fffcU
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fffcU) >> 2)
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000fffcU)
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0000fffcU)
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000fffcU)))

/* macros for field watchdog_timeout_reset_idle_limit */
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__SHIFT            16
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WIDTH            16
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MASK    0xffff0000U
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0xffff0000U)
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((u_int32_t)(src) <<\
                    16) & 0xffff0000U)
#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define WATCHDOG_CTRL_1__TYPE                                         u_int32_t
#define WATCHDOG_CTRL_1__READ                                       0xffffffffU
#define WATCHDOG_CTRL_1__WRITE                                      0xffffffffU

#endif /* __WATCHDOG_CTRL_1_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_ctrl_1 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_CTRL_1__NUM               1

/* macros for BlueprintGlobalNameSpace::watchdog_ctrl_2 */
#ifndef __WATCHDOG_CTRL_2_MACRO__
#define __WATCHDOG_CTRL_2_MACRO__

/* macros for field force_fast_adc_clk */
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SHIFT                            0
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WIDTH                            1
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MASK                   0x00000001U
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field watchdog_timeout_reset_ena */
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__SHIFT                    1
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WIDTH                    1
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MASK           0x00000002U
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field watchdog_irq_ena */
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__SHIFT                              2
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WIDTH                              1
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MASK                     0x00000004U
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)
#define WATCHDOG_CTRL_2__TYPE                                         u_int32_t
#define WATCHDOG_CTRL_2__READ                                       0x00000007U
#define WATCHDOG_CTRL_2__WRITE                                      0x00000007U

#endif /* __WATCHDOG_CTRL_2_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_ctrl_2 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_CTRL_2__NUM               1

/* macros for BlueprintGlobalNameSpace::bluetooth_cntl */
#ifndef __BLUETOOTH_CNTL_MACRO__
#define __BLUETOOTH_CNTL_MACRO__

/* macros for field bt_break_cck_en */
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SHIFT                                0
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WIDTH                                1
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MASK                       0x00000001U
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field bt_ant_halt_wlan */
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SHIFT                               1
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WIDTH                               1
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MASK                      0x00000002U
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)
#define BLUETOOTH_CNTL__TYPE                                          u_int32_t
#define BLUETOOTH_CNTL__READ                                        0x00000003U
#define BLUETOOTH_CNTL__WRITE                                       0x00000003U

#endif /* __BLUETOOTH_CNTL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_bluetooth_cntl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BLUETOOTH_CNTL__NUM                1

/* macros for BlueprintGlobalNameSpace::phyonly_warm_reset */
#ifndef __PHYONLY_WARM_RESET_MACRO__
#define __PHYONLY_WARM_RESET_MACRO__

/* macros for field phyonly_rst_warm_l */
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SHIFT                         0
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WIDTH                         1
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MASK                0x00000001U
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)
#define PHYONLY_WARM_RESET__TYPE                                      u_int32_t
#define PHYONLY_WARM_RESET__READ                                    0x00000001U
#define PHYONLY_WARM_RESET__WRITE                                   0x00000001U

#endif /* __PHYONLY_WARM_RESET_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_phyonly_warm_reset */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PHYONLY_WARM_RESET__NUM            1

/* macros for BlueprintGlobalNameSpace::phyonly_control */
#ifndef __PHYONLY_CONTROL_MACRO__
#define __PHYONLY_CONTROL_MACRO__

/* macros for field rx_drain_rate */
#define PHYONLY_CONTROL__RX_DRAIN_RATE__SHIFT                                 0
#define PHYONLY_CONTROL__RX_DRAIN_RATE__WIDTH                                 1
#define PHYONLY_CONTROL__RX_DRAIN_RATE__MASK                        0x00000001U
#define PHYONLY_CONTROL__RX_DRAIN_RATE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PHYONLY_CONTROL__RX_DRAIN_RATE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PHYONLY_CONTROL__RX_DRAIN_RATE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PHYONLY_CONTROL__RX_DRAIN_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PHYONLY_CONTROL__RX_DRAIN_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field late_tx_signal_symbol */
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SHIFT                         1
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WIDTH                         1
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MASK                0x00000002U
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field generate_scrambler */
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SHIFT                            2
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WIDTH                            1
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MASK                   0x00000004U
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field tx_antenna_select */
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SHIFT                             3
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WIDTH                             1
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MASK                    0x00000008U
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field static_tx_antenna */
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SHIFT                             4
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WIDTH                             1
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MASK                    0x00000010U
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field rx_antenna_select */
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SHIFT                             5
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WIDTH                             1
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MASK                    0x00000020U
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field static_rx_antenna */
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SHIFT                             6
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WIDTH                             1
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MASK                    0x00000040U
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field en_low_freq_sleep */
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SHIFT                             7
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WIDTH                             1
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MASK                    0x00000080U
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)
#define PHYONLY_CONTROL__TYPE                                         u_int32_t
#define PHYONLY_CONTROL__READ                                       0x000000ffU
#define PHYONLY_CONTROL__WRITE                                      0x000000ffU

#endif /* __PHYONLY_CONTROL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_phyonly_control */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PHYONLY_CONTROL__NUM               1

/* macros for BlueprintGlobalNameSpace::eco_ctrl */
#ifndef __ECO_CTRL_MACRO__
#define __ECO_CTRL_MACRO__

/* macros for field eco_ctrl */
#define ECO_CTRL__ECO_CTRL__SHIFT                                             0
#define ECO_CTRL__ECO_CTRL__WIDTH                                             8
#define ECO_CTRL__ECO_CTRL__MASK                                    0x000000ffU
#define ECO_CTRL__ECO_CTRL__READ(src)            (u_int32_t)(src) & 0x000000ffU
#define ECO_CTRL__ECO_CTRL__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
#define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define ECO_CTRL__ECO_CTRL__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))
#define ECO_CTRL__TYPE                                                u_int32_t
#define ECO_CTRL__READ                                              0x000000ffU
#define ECO_CTRL__WRITE                                             0x000000ffU

#endif /* __ECO_CTRL_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_eco_ctrl */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ECO_CTRL__NUM                      1

/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b0 */
#ifndef __TABLES_INTF_ADDR_B0_MACRO__
#define __TABLES_INTF_ADDR_B0_MACRO__

/* macros for field tables_addr_0 */
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__SHIFT                             2
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WIDTH                            16
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MASK                    0x0003fffcU
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field addr_auto_incr_0 */
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__SHIFT                         31
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WIDTH                          1
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MASK                 0x80000000U
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TABLES_INTF_ADDR_B0__TYPE                                     u_int32_t
#define TABLES_INTF_ADDR_B0__READ                                   0x8003fffcU
#define TABLES_INTF_ADDR_B0__WRITE                                  0x8003fffcU

#endif /* __TABLES_INTF_ADDR_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tables_intf_addr_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TABLES_INTF_ADDR_B0__NUM           1

/* macros for BlueprintGlobalNameSpace::tables_intf_data_b0 */
#ifndef __TABLES_INTF_DATA_B0_MACRO__
#define __TABLES_INTF_DATA_B0_MACRO__

/* macros for field tables_data_0 */
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__SHIFT                             0
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__WIDTH                            32
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__MASK                    0xffffffffU
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TABLES_INTF_DATA_B0__TABLES_DATA_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TABLES_INTF_DATA_B0__TYPE                                     u_int32_t
#define TABLES_INTF_DATA_B0__READ                                   0xffffffffU
#define TABLES_INTF_DATA_B0__WRITE                                  0xffffffffU

#endif /* __TABLES_INTF_DATA_B0_MACRO__ */


/* macros for bb_reg_map.bb_sm_reg_map.BB_tables_intf_data_b0 */
#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TABLES_INTF_DATA_B0__NUM           1

/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b1 */
#ifndef __EXT_CHAN_PWR_THR_2_B1_MACRO__
#define __EXT_CHAN_PWR_THR_2_B1_MACRO__

/* macros for field cf_maxCCApwr_ext_1 */
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__SHIFT                      0
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WIDTH                      9
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MASK             0x000001ffU
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field minCCApwr_ext_1 */
#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__SHIFT                        16
#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__WIDTH                         9
#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__MASK                0x01ff0000U
#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01ff0000U) >> 16)
#define EXT_CHAN_PWR_THR_2_B1__TYPE                                   u_int32_t
#define EXT_CHAN_PWR_THR_2_B1__READ                                 0x01ff01ffU
#define EXT_CHAN_PWR_THR_2_B1__WRITE                                0x01ff01ffU

#endif /* __EXT_CHAN_PWR_THR_2_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_ext_chan_pwr_thr_2_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B1__NUM       1

/* macros for BlueprintGlobalNameSpace::spur_report_b1 */
#ifndef __SPUR_REPORT_B1_MACRO__
#define __SPUR_REPORT_B1_MACRO__

/* macros for field spur_est_i_1 */
#define SPUR_REPORT_B1__SPUR_EST_I_1__SHIFT                                   0
#define SPUR_REPORT_B1__SPUR_EST_I_1__WIDTH                                   8
#define SPUR_REPORT_B1__SPUR_EST_I_1__MASK                          0x000000ffU
#define SPUR_REPORT_B1__SPUR_EST_I_1__READ(src)  (u_int32_t)(src) & 0x000000ffU

/* macros for field spur_est_q_1 */
#define SPUR_REPORT_B1__SPUR_EST_Q_1__SHIFT                                   8
#define SPUR_REPORT_B1__SPUR_EST_Q_1__WIDTH                                   8
#define SPUR_REPORT_B1__SPUR_EST_Q_1__MASK                          0x0000ff00U
#define SPUR_REPORT_B1__SPUR_EST_Q_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field power_with_spur_removed_1 */
#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__SHIFT                     16
#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__WIDTH                     16
#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__MASK             0xffff0000U
#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define SPUR_REPORT_B1__TYPE                                          u_int32_t
#define SPUR_REPORT_B1__READ                                        0xffffffffU

#endif /* __SPUR_REPORT_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_spur_report_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_SPUR_REPORT_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b1 */
#ifndef __IQ_ADC_MEAS_0_B1_MACRO__
#define __IQ_ADC_MEAS_0_B1_MACRO__

/* macros for field gain_dc_iq_cal_meas_0_1 */
#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__SHIFT                      0
#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__WIDTH                     32
#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__MASK             0xffffffffU
#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_0_B1__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_0_B1__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_0_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_0_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_0_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b1 */
#ifndef __IQ_ADC_MEAS_1_B1_MACRO__
#define __IQ_ADC_MEAS_1_B1_MACRO__

/* macros for field gain_dc_iq_cal_meas_1_1 */
#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__SHIFT                      0
#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__WIDTH                     32
#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__MASK             0xffffffffU
#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_1_B1__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_1_B1__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_1_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_1_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_1_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b1 */
#ifndef __IQ_ADC_MEAS_2_B1_MACRO__
#define __IQ_ADC_MEAS_2_B1_MACRO__

/* macros for field gain_dc_iq_cal_meas_2_1 */
#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__SHIFT                      0
#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__WIDTH                     32
#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__MASK             0xffffffffU
#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_2_B1__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_2_B1__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_2_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_2_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_2_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b1 */
#ifndef __IQ_ADC_MEAS_3_B1_MACRO__
#define __IQ_ADC_MEAS_3_B1_MACRO__

/* macros for field gain_dc_iq_cal_meas_3_1 */
#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__SHIFT                      0
#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__WIDTH                     32
#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__MASK             0xffffffffU
#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_3_B1__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_3_B1__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_3_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_3_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_3_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b1 */
#ifndef __TX_PHASE_RAMP_B1_MACRO__
#define __TX_PHASE_RAMP_B1_MACRO__

/* macros for field cf_phase_ramp_enable_1 */
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SHIFT                       0
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WIDTH                       1
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MASK              0x00000001U
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cf_phase_ramp_bias_1 */
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__SHIFT                         1
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WIDTH                         6
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MASK                0x0000007eU
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000007eU) >> 1)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000007eU)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000007eU)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000007eU)))

/* macros for field cf_phase_ramp_init_1 */
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__SHIFT                         7
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WIDTH                        10
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MASK                0x0001ff80U
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001ff80U) >> 7)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x0001ff80U)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ff80U) | (((u_int32_t)(src) <<\
                    7) & 0x0001ff80U)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x0001ff80U)))

/* macros for field cf_phase_ramp_alpha_1 */
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__SHIFT                       17
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WIDTH                        8
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MASK               0x01fe0000U
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fe0000U) >> 17)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x01fe0000U)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x01fe0000U)
#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x01fe0000U)))
#define TX_PHASE_RAMP_B1__TYPE                                        u_int32_t
#define TX_PHASE_RAMP_B1__READ                                      0x01ffffffU
#define TX_PHASE_RAMP_B1__WRITE                                     0x01ffffffU

#endif /* __TX_PHASE_RAMP_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_tx_phase_ramp_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_TX_PHASE_RAMP_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b1 */
#ifndef __ADC_GAIN_DC_CORR_B1_MACRO__
#define __ADC_GAIN_DC_CORR_B1_MACRO__

/* macros for field adc_gain_corr_q_coeff_1 */
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__SHIFT                   0
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WIDTH                   6
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MASK          0x0000003fU
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field adc_gain_corr_i_coeff_1 */
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__SHIFT                   6
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WIDTH                   6
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MASK          0x00000fc0U
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field adc_dc_corr_q_coeff_1 */
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__SHIFT                    12
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WIDTH                     9
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MASK            0x001ff000U
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001ff000U) >> 12)
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x001ff000U)
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x001ff000U)
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x001ff000U)))

/* macros for field adc_dc_corr_i_coeff_1 */
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__SHIFT                    21
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WIDTH                     9
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MASK            0x3fe00000U
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3fe00000U) >> 21)
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x3fe00000U)
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x3fe00000U)
#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x3fe00000U)))
#define ADC_GAIN_DC_CORR_B1__TYPE                                     u_int32_t
#define ADC_GAIN_DC_CORR_B1__READ                                   0x3fffffffU
#define ADC_GAIN_DC_CORR_B1__WRITE                                  0x3fffffffU

#endif /* __ADC_GAIN_DC_CORR_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_adc_gain_dc_corr_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_ADC_GAIN_DC_CORR_B1__NUM         1

/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b1 */
#ifndef __RX_IQ_CORR_B1_MACRO__
#define __RX_IQ_CORR_B1_MACRO__

/* macros for field rx_iqcorr_q_q_coff_1 */
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__SHIFT                            0
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WIDTH                            7
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MASK                   0x0000007fU
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field rx_iqcorr_q_i_coff_1 */
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__SHIFT                            7
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WIDTH                            7
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MASK                   0x00003f80U
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f80U) >> 7)
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00003f80U)
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00003f80U)
#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00003f80U)))

/* macros for field loopback_iqcorr_q_q_coff_1 */
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__SHIFT                     15
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WIDTH                      7
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MASK             0x003f8000U
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f8000U) >> 15)
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x003f8000U)
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x003f8000U)
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x003f8000U)))

/* macros for field loopback_iqcorr_q_i_coff_1 */
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__SHIFT                     22
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WIDTH                      7
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MASK             0x1fc00000U
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1fc00000U) >> 22)
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x1fc00000U)
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x1fc00000U)
#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x1fc00000U)))
#define RX_IQ_CORR_B1__TYPE                                           u_int32_t
#define RX_IQ_CORR_B1__READ                                         0x1fffbfffU
#define RX_IQ_CORR_B1__WRITE                                        0x1fffbfffU

#endif /* __RX_IQ_CORR_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_rx_iq_corr_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_RX_IQ_CORR_B1__NUM               1

/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b1 */
#ifndef __PAPRD_CTRL0_B1_MACRO__
#define __PAPRD_CTRL0_B1_MACRO__

/* macros for field paprd_enable_1 */
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SHIFT                                 0
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WIDTH                                 1
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MASK                        0x00000001U
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_adaptive_use_single_table_1 */
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SHIFT              1
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WIDTH              1
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MASK     0x00000002U
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_valid_gain_1 */
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__SHIFT                             2
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WIDTH                            25
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MASK                    0x07fffffcU
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fffffcU) >> 2)
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x07fffffcU)
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fffffcU) | (((u_int32_t)(src) <<\
                    2) & 0x07fffffcU)
#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x07fffffcU)))

/* macros for field paprd_mag_thrsh_1 */
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__SHIFT                             27
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WIDTH                              5
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MASK                     0xf8000000U
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf8000000U) >> 27)
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0xf8000000U)
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define PAPRD_CTRL0_B1__TYPE                                          u_int32_t
#define PAPRD_CTRL0_B1__READ                                        0xffffffffU
#define PAPRD_CTRL0_B1__WRITE                                       0xffffffffU

#endif /* __PAPRD_CTRL0_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_ctrl0_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_CTRL0_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b1 */
#ifndef __PAPRD_CTRL1_B1_MACRO__
#define __PAPRD_CTRL1_B1_MACRO__

/* macros for field paprd_adaptive_scaling_enable_1 */
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SHIFT                0
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WIDTH                1
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MASK       0x00000001U
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_adaptive_am2am_enable_1 */
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SHIFT                  1
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WIDTH                  1
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MASK         0x00000002U
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_adaptive_am2pm_enable_1 */
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SHIFT                  2
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WIDTH                  1
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MASK         0x00000004U
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field paprd_power_at_am2am_cal_1 */
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__SHIFT                     3
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WIDTH                     6
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MASK            0x000001f8U
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001f8U) >> 3)
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000001f8U)
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000001f8U)
#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000001f8U)))

/* macros for field pa_gain_scale_factor_1 */
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__SHIFT                         9
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WIDTH                         8
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MASK                0x0001fe00U
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fe00U) >> 9)
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x0001fe00U)
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001fe00U) | (((u_int32_t)(src) <<\
                    9) & 0x0001fe00U)
#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x0001fe00U)))

/* macros for field paprd_mag_scale_factor_1 */
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__SHIFT                      17
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WIDTH                      10
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MASK              0x07fe0000U
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fe0000U) >> 17)
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x07fe0000U)
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x07fe0000U)
#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x07fe0000U)))

/* macros for field paprd_trainer_iandq_sel_1 */
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SHIFT                     27
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WIDTH                      1
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MASK             0x08000000U
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)
#define PAPRD_CTRL1_B1__TYPE                                          u_int32_t
#define PAPRD_CTRL1_B1__READ                                        0x0fffffffU
#define PAPRD_CTRL1_B1__WRITE                                       0x0fffffffU

#endif /* __PAPRD_CTRL1_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_ctrl1_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_CTRL1_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::pa_gain123_b1 */
#ifndef __PA_GAIN123_B1_MACRO__
#define __PA_GAIN123_B1_MACRO__

/* macros for field pa_gain1_1 */
#define PA_GAIN123_B1__PA_GAIN1_1__SHIFT                                      0
#define PA_GAIN123_B1__PA_GAIN1_1__WIDTH                                     10
#define PA_GAIN123_B1__PA_GAIN1_1__MASK                             0x000003ffU
#define PA_GAIN123_B1__PA_GAIN1_1__READ(src)     (u_int32_t)(src) & 0x000003ffU
#define PA_GAIN123_B1__PA_GAIN1_1__WRITE(src)  ((u_int32_t)(src) & 0x000003ffU)
#define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PA_GAIN123_B1__PA_GAIN1_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field pa_gain2_1 */
#define PA_GAIN123_B1__PA_GAIN2_1__SHIFT                                     10
#define PA_GAIN123_B1__PA_GAIN2_1__WIDTH                                     10
#define PA_GAIN123_B1__PA_GAIN2_1__MASK                             0x000ffc00U
#define PA_GAIN123_B1__PA_GAIN2_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define PA_GAIN123_B1__PA_GAIN2_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define PA_GAIN123_B1__PA_GAIN2_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field pa_gain3_1 */
#define PA_GAIN123_B1__PA_GAIN3_1__SHIFT                                     20
#define PA_GAIN123_B1__PA_GAIN3_1__WIDTH                                     10
#define PA_GAIN123_B1__PA_GAIN3_1__MASK                             0x3ff00000U
#define PA_GAIN123_B1__PA_GAIN3_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3ff00000U) >> 20)
#define PA_GAIN123_B1__PA_GAIN3_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x3ff00000U)
#define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
                    20) & 0x3ff00000U)
#define PA_GAIN123_B1__PA_GAIN3_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x3ff00000U)))
#define PA_GAIN123_B1__TYPE                                           u_int32_t
#define PA_GAIN123_B1__READ                                         0x3fffffffU
#define PA_GAIN123_B1__WRITE                                        0x3fffffffU

#endif /* __PA_GAIN123_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_pa_gain123_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PA_GAIN123_B1__NUM               1

/* macros for BlueprintGlobalNameSpace::pa_gain45_b1 */
#ifndef __PA_GAIN45_B1_MACRO__
#define __PA_GAIN45_B1_MACRO__

/* macros for field pa_gain4_1 */
#define PA_GAIN45_B1__PA_GAIN4_1__SHIFT                                       0
#define PA_GAIN45_B1__PA_GAIN4_1__WIDTH                                      10
#define PA_GAIN45_B1__PA_GAIN4_1__MASK                              0x000003ffU
#define PA_GAIN45_B1__PA_GAIN4_1__READ(src)      (u_int32_t)(src) & 0x000003ffU
#define PA_GAIN45_B1__PA_GAIN4_1__WRITE(src)   ((u_int32_t)(src) & 0x000003ffU)
#define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PA_GAIN45_B1__PA_GAIN4_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field pa_gain5_1 */
#define PA_GAIN45_B1__PA_GAIN5_1__SHIFT                                      10
#define PA_GAIN45_B1__PA_GAIN5_1__WIDTH                                      10
#define PA_GAIN45_B1__PA_GAIN5_1__MASK                              0x000ffc00U
#define PA_GAIN45_B1__PA_GAIN5_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define PA_GAIN45_B1__PA_GAIN5_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define PA_GAIN45_B1__PA_GAIN5_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field paprd_adaptive_table_valid_1 */
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__SHIFT                    20
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WIDTH                     5
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MASK            0x01f00000U
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))
#define PA_GAIN45_B1__TYPE                                            u_int32_t
#define PA_GAIN45_B1__READ                                          0x01ffffffU
#define PA_GAIN45_B1__WRITE                                         0x01ffffffU

#endif /* __PA_GAIN45_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_pa_gain45_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PA_GAIN45_B1__NUM                1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_0_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_0_B1_MACRO__

/* macros for field paprd_pre_post_scaling_0_1 */
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_0_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_0_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_0_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_1_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_1_B1_MACRO__

/* macros for field paprd_pre_post_scaling_1_1 */
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_1_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_1_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_1_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_2_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_2_B1_MACRO__

/* macros for field paprd_pre_post_scaling_2_1 */
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_2_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_2_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_2_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_3_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_3_B1_MACRO__

/* macros for field paprd_pre_post_scaling_3_1 */
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_3_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_3_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_3_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_4_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_4_B1_MACRO__

/* macros for field paprd_pre_post_scaling_4_1 */
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_4_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_4_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_4_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_5_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_5_B1_MACRO__

/* macros for field paprd_pre_post_scaling_5_1 */
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_5_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_5_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_5_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_6_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_6_B1_MACRO__

/* macros for field paprd_pre_post_scaling_6_1 */
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_6_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_6_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_6_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b1 */
#ifndef __PAPRD_PRE_POST_SCALE_7_B1_MACRO__
#define __PAPRD_PRE_POST_SCALE_7_B1_MACRO__

/* macros for field paprd_pre_post_scaling_7_1 */
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__SHIFT          0
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WIDTH         18
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_7_B1__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_7_B1__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B1__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_7_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B1__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */
#ifndef __PAPRD_MEM_TAB_MACRO__
#define __PAPRD_MEM_TAB_MACRO__

/* macros for field paprd_mem */
#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT                                       0
#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH                                      22
#define PAPRD_MEM_TAB__PAPRD_MEM__MASK                              0x003fffffU
#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src)      (u_int32_t)(src) & 0x003fffffU
#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src)   ((u_int32_t)(src) & 0x003fffffU)
#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003fffffU) | ((u_int32_t)(src) &\
                    0x003fffffU)
#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x003fffffU)))
#define PAPRD_MEM_TAB__TYPE                                           u_int32_t
#define PAPRD_MEM_TAB__READ                                         0x003fffffU
#define PAPRD_MEM_TAB__WRITE                                        0x003fffffU

#endif /* __PAPRD_MEM_TAB_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_mem_tab_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_MEM_TAB_B1__NUM          120

/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */
#ifndef __CHAN_INFO_CHAN_TAB_MACRO__
#define __CHAN_INFO_CHAN_TAB_MACRO__

/* macros for field chaninfo_word */
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT                              0
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH                             32
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK                     0xffffffffU
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CHAN_INFO_CHAN_TAB__TYPE                                      u_int32_t
#define CHAN_INFO_CHAN_TAB__READ                                    0xffffffffU

#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_chan_info_chan_tab_b1 */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B1__NUM      60

/* macros for BlueprintGlobalNameSpace::chn1_tables_intf_addr */
#ifndef __CHN1_TABLES_INTF_ADDR_MACRO__
#define __CHN1_TABLES_INTF_ADDR_MACRO__

/* macros for field chn1_tables_addr */
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__SHIFT                        2
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WIDTH                       16
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MASK               0x0003fffcU
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field chn1_addr_auto_incr */
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__SHIFT                    31
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WIDTH                     1
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MASK            0x80000000U
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define CHN1_TABLES_INTF_ADDR__TYPE                                   u_int32_t
#define CHN1_TABLES_INTF_ADDR__READ                                 0x8003fffcU
#define CHN1_TABLES_INTF_ADDR__WRITE                                0x8003fffcU

#endif /* __CHN1_TABLES_INTF_ADDR_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_chn1_tables_intf_addr */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHN1_TABLES_INTF_ADDR__NUM       1

/* macros for BlueprintGlobalNameSpace::chn1_tables_intf_data */
#ifndef __CHN1_TABLES_INTF_DATA_MACRO__
#define __CHN1_TABLES_INTF_DATA_MACRO__

/* macros for field chn1_tables_data */
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__SHIFT                        0
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WIDTH                       32
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MASK               0xffffffffU
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CHN1_TABLES_INTF_DATA__TYPE                                   u_int32_t
#define CHN1_TABLES_INTF_DATA__READ                                 0xffffffffU
#define CHN1_TABLES_INTF_DATA__WRITE                                0xffffffffU

#endif /* __CHN1_TABLES_INTF_DATA_MACRO__ */


/* macros for bb_reg_map.bb_chn1_reg_map.BB_chn1_tables_intf_data */
#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHN1_TABLES_INTF_DATA__NUM       1

/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b1 */
#ifndef __GAIN_FORCE_MAX_GAINS_B1_MACRO__
#define __GAIN_FORCE_MAX_GAINS_B1_MACRO__

/* macros for field rf_gain_f_1 */
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__SHIFT                           0
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WIDTH                           8
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MASK                  0x000000ffU
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field mb_gain_f_1 */
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__SHIFT                           8
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WIDTH                           8
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MASK                  0x0000ff00U
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field xatten1_sw_f_1 */
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SHIFT                       16
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WIDTH                        1
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MASK               0x00010000U
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field xatten2_sw_f_1 */
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SHIFT                       17
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WIDTH                        1
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MASK               0x00020000U
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field xatten1_hyst_margin_1 */
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__SHIFT                18
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WIDTH                 7
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MASK        0x01fc0000U
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fc0000U) >> 18)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x01fc0000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x01fc0000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x01fc0000U)))

/* macros for field xatten2_hyst_margin_1 */
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__SHIFT                25
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WIDTH                 7
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MASK        0xfe000000U
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfe000000U) >> 25)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0xfe000000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfe000000U) | (((u_int32_t)(src) <<\
                    25) & 0xfe000000U)
#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0xfe000000U)))
#define GAIN_FORCE_MAX_GAINS_B1__TYPE                                 u_int32_t
#define GAIN_FORCE_MAX_GAINS_B1__READ                               0xffffffffU
#define GAIN_FORCE_MAX_GAINS_B1__WRITE                              0xffffffffU

#endif /* __GAIN_FORCE_MAX_GAINS_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_gain_force_max_gains_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B1__NUM     1

/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b1 */
#ifndef __EXT_ATTEN_SWITCH_CTL_B1_MACRO__
#define __EXT_ATTEN_SWITCH_CTL_B1_MACRO__

/* macros for field xatten1_db_1 */
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__SHIFT                          0
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WIDTH                          6
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MASK                 0x0000003fU
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field xatten2_db_1 */
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__SHIFT                          6
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WIDTH                          6
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MASK                 0x00000fc0U
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field xatten1_margin_1 */
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__SHIFT                     12
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WIDTH                      5
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MASK             0x0001f000U
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field xatten2_margin_1 */
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__SHIFT                     17
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WIDTH                      5
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MASK             0x003e0000U
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003e0000U) >> 17)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x003e0000U)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field xlna_gain_db_1 */
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__SHIFT                       22
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WIDTH                        5
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MASK               0x07c00000U
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))
#define EXT_ATTEN_SWITCH_CTL_B1__TYPE                                 u_int32_t
#define EXT_ATTEN_SWITCH_CTL_B1__READ                               0x07ffffffU
#define EXT_ATTEN_SWITCH_CTL_B1__WRITE                              0x07ffffffU

#endif /* __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_ext_atten_switch_ctl_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B1__NUM     1

/* macros for BlueprintGlobalNameSpace::cca_b1 */
#ifndef __CCA_B1_MACRO__
#define __CCA_B1_MACRO__

/* macros for field cf_maxCCApwr_1 */
#define CCA_B1__CF_MAXCCAPWR_1__SHIFT                                         0
#define CCA_B1__CF_MAXCCAPWR_1__WIDTH                                         9
#define CCA_B1__CF_MAXCCAPWR_1__MASK                                0x000001ffU
#define CCA_B1__CF_MAXCCAPWR_1__READ(src)        (u_int32_t)(src) & 0x000001ffU
#define CCA_B1__CF_MAXCCAPWR_1__WRITE(src)     ((u_int32_t)(src) & 0x000001ffU)
#define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define CCA_B1__CF_MAXCCAPWR_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field minCCApwr_1 */
#define CCA_B1__MINCCAPWR_1__SHIFT                                           20
#define CCA_B1__MINCCAPWR_1__WIDTH                                            9
#define CCA_B1__MINCCAPWR_1__MASK                                   0x1ff00000U
#define CCA_B1__MINCCAPWR_1__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
#define CCA_B1__TYPE                                                  u_int32_t
#define CCA_B1__READ                                                0x1ff001ffU
#define CCA_B1__WRITE                                               0x1ff001ffU

#endif /* __CCA_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_cca_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_CCA_B1__NUM                      1

/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b1 */
#ifndef __CCA_CTRL_2_B1_MACRO__
#define __CCA_CTRL_2_B1_MACRO__

/* macros for field minCCApwr_thr_1 */
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__SHIFT                                 0
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WIDTH                                 9
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MASK                        0x000001ffU
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field NF_gain_comp_1 */
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__SHIFT                                 10
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WIDTH                                  8
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MASK                         0x0003fc00U
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fc00U) >> 10)
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0003fc00U)
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0003fc00U)
#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0003fc00U)))
#define CCA_CTRL_2_B1__TYPE                                           u_int32_t
#define CCA_CTRL_2_B1__READ                                         0x0003fdffU
#define CCA_CTRL_2_B1__WRITE                                        0x0003fdffU

#endif /* __CCA_CTRL_2_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_cca_ctrl_2_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_CCA_CTRL_2_B1__NUM               1

/* macros for BlueprintGlobalNameSpace::rssi_b1 */
#ifndef __RSSI_B1_MACRO__
#define __RSSI_B1_MACRO__

/* macros for field rssi_1 */
#define RSSI_B1__RSSI_1__SHIFT                                                0
#define RSSI_B1__RSSI_1__WIDTH                                                8
#define RSSI_B1__RSSI_1__MASK                                       0x000000ffU
#define RSSI_B1__RSSI_1__READ(src)               (u_int32_t)(src) & 0x000000ffU

/* macros for field rssi_ext_1 */
#define RSSI_B1__RSSI_EXT_1__SHIFT                                            8
#define RSSI_B1__RSSI_EXT_1__WIDTH                                            8
#define RSSI_B1__RSSI_EXT_1__MASK                                   0x0000ff00U
#define RSSI_B1__RSSI_EXT_1__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define RSSI_B1__TYPE                                                 u_int32_t
#define RSSI_B1__READ                                               0x0000ffffU

#endif /* __RSSI_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_rssi_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_RSSI_B1__NUM                     1

/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b1 */
#ifndef __SPUR_EST_CCK_REPORT_B1_MACRO__
#define __SPUR_EST_CCK_REPORT_B1_MACRO__

/* macros for field spur_est_sd_i_1_cck */
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__SHIFT                    0
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__WIDTH                    8
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__MASK           0x000000ffU
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU

/* macros for field spur_est_sd_q_1_cck */
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__SHIFT                    8
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__WIDTH                    8
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__MASK           0x0000ff00U
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field spur_est_i_1_cck */
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__SHIFT                      16
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__WIDTH                       8
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__MASK              0x00ff0000U
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field spur_est_q_1_cck */
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__SHIFT                      24
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__WIDTH                       8
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__MASK              0xff000000U
#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define SPUR_EST_CCK_REPORT_B1__TYPE                                  u_int32_t
#define SPUR_EST_CCK_REPORT_B1__READ                                0xffffffffU

#endif /* __SPUR_EST_CCK_REPORT_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_spur_est_cck_report_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_SPUR_EST_CCK_REPORT_B1__NUM      1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b1 */
#ifndef __AGC_DIG_DC_STATUS_I_B1_MACRO__
#define __AGC_DIG_DC_STATUS_I_B1_MACRO__

/* macros for field dig_dc_C1_res_i_1 */
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__SHIFT                      0
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__MASK             0x000001ffU
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU

/* macros for field dig_dc_C2_res_i_1 */
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__SHIFT                      9
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__MASK             0x0003fe00U
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fe00U) >> 9)

/* macros for field dig_dc_C3_res_i_1 */
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__SHIFT                     18
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__MASK             0x07fc0000U
#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fc0000U) >> 18)
#define AGC_DIG_DC_STATUS_I_B1__TYPE                                  u_int32_t
#define AGC_DIG_DC_STATUS_I_B1__READ                                0x07ffffffU

#endif /* __AGC_DIG_DC_STATUS_I_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_agc_dig_dc_status_i_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B1__NUM      1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b1 */
#ifndef __AGC_DIG_DC_STATUS_Q_B1_MACRO__
#define __AGC_DIG_DC_STATUS_Q_B1_MACRO__

/* macros for field dig_dc_C1_res_q_1 */
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__SHIFT                      0
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__MASK             0x000001ffU
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU

/* macros for field dig_dc_C2_res_q_1 */
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__SHIFT                      9
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__MASK             0x0003fe00U
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fe00U) >> 9)

/* macros for field dig_dc_C3_res_q_1 */
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__SHIFT                     18
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__MASK             0x07fc0000U
#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fc0000U) >> 18)
#define AGC_DIG_DC_STATUS_Q_B1__TYPE                                  u_int32_t
#define AGC_DIG_DC_STATUS_Q_B1__READ                                0x07ffffffU

#endif /* __AGC_DIG_DC_STATUS_Q_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_agc_dig_dc_status_q_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B1__NUM      1

/* macros for BlueprintGlobalNameSpace::dc_cal_status_b1 */
#ifndef __DC_CAL_STATUS_B1_MACRO__
#define __DC_CAL_STATUS_B1_MACRO__

/* macros for field offsetC1I_1 */
#define DC_CAL_STATUS_B1__OFFSETC1I_1__SHIFT                                  0
#define DC_CAL_STATUS_B1__OFFSETC1I_1__WIDTH                                  5
#define DC_CAL_STATUS_B1__OFFSETC1I_1__MASK                         0x0000001fU
#define DC_CAL_STATUS_B1__OFFSETC1I_1__READ(src) (u_int32_t)(src) & 0x0000001fU

/* macros for field offsetC1Q_1 */
#define DC_CAL_STATUS_B1__OFFSETC1Q_1__SHIFT                                  5
#define DC_CAL_STATUS_B1__OFFSETC1Q_1__WIDTH                                  5
#define DC_CAL_STATUS_B1__OFFSETC1Q_1__MASK                         0x000003e0U
#define DC_CAL_STATUS_B1__OFFSETC1Q_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)

/* macros for field offsetC2I_1 */
#define DC_CAL_STATUS_B1__OFFSETC2I_1__SHIFT                                 10
#define DC_CAL_STATUS_B1__OFFSETC2I_1__WIDTH                                  5
#define DC_CAL_STATUS_B1__OFFSETC2I_1__MASK                         0x00007c00U
#define DC_CAL_STATUS_B1__OFFSETC2I_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)

/* macros for field offsetC2Q_1 */
#define DC_CAL_STATUS_B1__OFFSETC2Q_1__SHIFT                                 15
#define DC_CAL_STATUS_B1__OFFSETC2Q_1__WIDTH                                  5
#define DC_CAL_STATUS_B1__OFFSETC2Q_1__MASK                         0x000f8000U
#define DC_CAL_STATUS_B1__OFFSETC2Q_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)

/* macros for field offsetC3I_1 */
#define DC_CAL_STATUS_B1__OFFSETC3I_1__SHIFT                                 20
#define DC_CAL_STATUS_B1__OFFSETC3I_1__WIDTH                                  5
#define DC_CAL_STATUS_B1__OFFSETC3I_1__MASK                         0x01f00000U
#define DC_CAL_STATUS_B1__OFFSETC3I_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)

/* macros for field offsetC3Q_1 */
#define DC_CAL_STATUS_B1__OFFSETC3Q_1__SHIFT                                 25
#define DC_CAL_STATUS_B1__OFFSETC3Q_1__WIDTH                                  5
#define DC_CAL_STATUS_B1__OFFSETC3Q_1__MASK                         0x3e000000U
#define DC_CAL_STATUS_B1__OFFSETC3Q_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define DC_CAL_STATUS_B1__TYPE                                        u_int32_t
#define DC_CAL_STATUS_B1__READ                                      0x3fffffffU

#endif /* __DC_CAL_STATUS_B1_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_dc_cal_status_b1 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_DC_CAL_STATUS_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::rx_ocgain2 */
#ifndef __RX_OCGAIN2_MACRO__
#define __RX_OCGAIN2_MACRO__

/* macros for field gain_entry2 */
#define RX_OCGAIN2__GAIN_ENTRY2__SHIFT                                        0
#define RX_OCGAIN2__GAIN_ENTRY2__WIDTH                                       32
#define RX_OCGAIN2__GAIN_ENTRY2__MASK                               0xffffffffU
#define RX_OCGAIN2__GAIN_ENTRY2__READ(src)       (u_int32_t)(src) & 0xffffffffU
#define RX_OCGAIN2__GAIN_ENTRY2__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
#define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define RX_OCGAIN2__GAIN_ENTRY2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define RX_OCGAIN2__TYPE                                              u_int32_t
#define RX_OCGAIN2__READ                                            0xffffffffU
#define RX_OCGAIN2__WRITE                                           0xffffffffU

#endif /* __RX_OCGAIN2_MACRO__ */


/* macros for bb_reg_map.bb_agc1_reg_map.BB_rx_ocgain2 */
#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_RX_OCGAIN2__NUM                128

/* macros for BlueprintGlobalNameSpace::switch_table_chn_b1 */
#ifndef __SWITCH_TABLE_CHN_B1_MACRO__
#define __SWITCH_TABLE_CHN_B1_MACRO__

/* macros for field switch_table_idle_1 */
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__SHIFT                       0
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WIDTH                       2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MASK              0x00000003U
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field switch_table_t_1 */
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__SHIFT                          2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WIDTH                          2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MASK                 0x0000000cU
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field switch_table_r_1 */
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__SHIFT                          4
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WIDTH                          2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MASK                 0x00000030U
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field switch_table_rx1_1 */
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__SHIFT                        6
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WIDTH                        2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MASK               0x000000c0U
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field switch_table_rx12_1 */
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__SHIFT                       8
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WIDTH                       2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MASK              0x00000300U
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field switch_table_b_1 */
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__SHIFT                         10
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WIDTH                          2
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MASK                 0x00000c00U
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))
#define SWITCH_TABLE_CHN_B1__TYPE                                     u_int32_t
#define SWITCH_TABLE_CHN_B1__READ                                   0x00000fffU
#define SWITCH_TABLE_CHN_B1__WRITE                                  0x00000fffU

#endif /* __SWITCH_TABLE_CHN_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_switch_table_chn_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_SWITCH_TABLE_CHN_B1__NUM          1

/* macros for BlueprintGlobalNameSpace::fcal_2_b1 */
#ifndef __FCAL_2_B1_MACRO__
#define __FCAL_2_B1_MACRO__

/* macros for field flc_sw_cap_val_1 */
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__SHIFT                                    3
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WIDTH                                    5
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MASK                           0x000000f8U
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f8U) >> 3)
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000000f8U)
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000000f8U)
#define FCAL_2_B1__FLC_SW_CAP_VAL_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000000f8U)))

/* macros for field flc_cap_val_status_1 */
#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__SHIFT                               20
#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__WIDTH                                5
#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__MASK                       0x01f00000U
#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define FCAL_2_B1__TYPE                                               u_int32_t
#define FCAL_2_B1__READ                                             0x01f000f8U
#define FCAL_2_B1__WRITE                                            0x01f000f8U

#endif /* __FCAL_2_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_fcal_2_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_FCAL_2_B1__NUM                    1

/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b1 */
#ifndef __DFT_TONE_CTRL_B1_MACRO__
#define __DFT_TONE_CTRL_B1_MACRO__

/* macros for field dft_tone_en_1 */
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SHIFT                                0
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WIDTH                                1
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MASK                       0x00000001U
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field dft_tone_amp_sel_1 */
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__SHIFT                           2
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WIDTH                           2
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MASK                  0x0000000cU
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field dft_tone_freq_ang_1 */
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__SHIFT                          4
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WIDTH                          9
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MASK                 0x00001ff0U
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001ff0U) >> 4)
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00001ff0U)
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001ff0U) | (((u_int32_t)(src) <<\
                    4) & 0x00001ff0U)
#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00001ff0U)))
#define DFT_TONE_CTRL_B1__TYPE                                        u_int32_t
#define DFT_TONE_CTRL_B1__READ                                      0x00001ffdU
#define DFT_TONE_CTRL_B1__WRITE                                     0x00001ffdU

#endif /* __DFT_TONE_CTRL_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_dft_tone_ctrl_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_DFT_TONE_CTRL_B1__NUM             1

/* macros for BlueprintGlobalNameSpace::cl_map_0 */
#ifndef __CL_MAP_0_MACRO__
#define __CL_MAP_0_MACRO__

/* macros for field cl_map_0 */
#define CL_MAP_0__CL_MAP_0__SHIFT                                             0
#define CL_MAP_0__CL_MAP_0__WIDTH                                            32
#define CL_MAP_0__CL_MAP_0__MASK                                    0xffffffffU
#define CL_MAP_0__CL_MAP_0__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_0__CL_MAP_0__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_0__CL_MAP_0__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_0__TYPE                                                u_int32_t
#define CL_MAP_0__READ                                              0xffffffffU
#define CL_MAP_0__WRITE                                             0xffffffffU

#endif /* __CL_MAP_0_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_0_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_0_B1__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_1 */
#ifndef __CL_MAP_1_MACRO__
#define __CL_MAP_1_MACRO__

/* macros for field cl_map_1 */
#define CL_MAP_1__CL_MAP_1__SHIFT                                             0
#define CL_MAP_1__CL_MAP_1__WIDTH                                            32
#define CL_MAP_1__CL_MAP_1__MASK                                    0xffffffffU
#define CL_MAP_1__CL_MAP_1__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_1__CL_MAP_1__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_1__CL_MAP_1__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_1__TYPE                                                u_int32_t
#define CL_MAP_1__READ                                              0xffffffffU
#define CL_MAP_1__WRITE                                             0xffffffffU

#endif /* __CL_MAP_1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_1_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_1_B1__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_2 */
#ifndef __CL_MAP_2_MACRO__
#define __CL_MAP_2_MACRO__

/* macros for field cl_map_2 */
#define CL_MAP_2__CL_MAP_2__SHIFT                                             0
#define CL_MAP_2__CL_MAP_2__WIDTH                                            32
#define CL_MAP_2__CL_MAP_2__MASK                                    0xffffffffU
#define CL_MAP_2__CL_MAP_2__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_2__CL_MAP_2__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_2__CL_MAP_2__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_2__TYPE                                                u_int32_t
#define CL_MAP_2__READ                                              0xffffffffU
#define CL_MAP_2__WRITE                                             0xffffffffU

#endif /* __CL_MAP_2_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_2_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_2_B1__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_3 */
#ifndef __CL_MAP_3_MACRO__
#define __CL_MAP_3_MACRO__

/* macros for field cl_map_3 */
#define CL_MAP_3__CL_MAP_3__SHIFT                                             0
#define CL_MAP_3__CL_MAP_3__WIDTH                                            32
#define CL_MAP_3__CL_MAP_3__MASK                                    0xffffffffU
#define CL_MAP_3__CL_MAP_3__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_3__CL_MAP_3__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_3__CL_MAP_3__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_3__TYPE                                                u_int32_t
#define CL_MAP_3__READ                                              0xffffffffU
#define CL_MAP_3__WRITE                                             0xffffffffU

#endif /* __CL_MAP_3_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_3_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_3_B1__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */
#ifndef __CL_MAP_PAL_0_MACRO__
#define __CL_MAP_PAL_0_MACRO__

/* macros for field cl_map_0 */
#define CL_MAP_PAL_0__CL_MAP_0__SHIFT                                         0
#define CL_MAP_PAL_0__CL_MAP_0__WIDTH                                        32
#define CL_MAP_PAL_0__CL_MAP_0__MASK                                0xffffffffU
#define CL_MAP_PAL_0__CL_MAP_0__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_0__TYPE                                            u_int32_t
#define CL_MAP_PAL_0__READ                                          0xffffffffU
#define CL_MAP_PAL_0__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_0_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_0_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_0_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */
#ifndef __CL_MAP_PAL_1_MACRO__
#define __CL_MAP_PAL_1_MACRO__

/* macros for field cl_map_1 */
#define CL_MAP_PAL_1__CL_MAP_1__SHIFT                                         0
#define CL_MAP_PAL_1__CL_MAP_1__WIDTH                                        32
#define CL_MAP_PAL_1__CL_MAP_1__MASK                                0xffffffffU
#define CL_MAP_PAL_1__CL_MAP_1__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_1__TYPE                                            u_int32_t
#define CL_MAP_PAL_1__READ                                          0xffffffffU
#define CL_MAP_PAL_1__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_1_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_1_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */
#ifndef __CL_MAP_PAL_2_MACRO__
#define __CL_MAP_PAL_2_MACRO__

/* macros for field cl_map_2 */
#define CL_MAP_PAL_2__CL_MAP_2__SHIFT                                         0
#define CL_MAP_PAL_2__CL_MAP_2__WIDTH                                        32
#define CL_MAP_PAL_2__CL_MAP_2__MASK                                0xffffffffU
#define CL_MAP_PAL_2__CL_MAP_2__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_2__TYPE                                            u_int32_t
#define CL_MAP_PAL_2__READ                                          0xffffffffU
#define CL_MAP_PAL_2__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_2_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_2_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_2_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */
#ifndef __CL_MAP_PAL_3_MACRO__
#define __CL_MAP_PAL_3_MACRO__

/* macros for field cl_map_3 */
#define CL_MAP_PAL_3__CL_MAP_3__SHIFT                                         0
#define CL_MAP_PAL_3__CL_MAP_3__WIDTH                                        32
#define CL_MAP_PAL_3__CL_MAP_3__MASK                                0xffffffffU
#define CL_MAP_PAL_3__CL_MAP_3__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_3__TYPE                                            u_int32_t
#define CL_MAP_PAL_3__READ                                          0xffffffffU
#define CL_MAP_PAL_3__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_3_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_3_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_3_B1__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_tab */
#ifndef __CL_TAB_MACRO__
#define __CL_TAB_MACRO__

/* macros for field cl_gain_mod */
#define CL_TAB__CL_GAIN_MOD__SHIFT                                            0
#define CL_TAB__CL_GAIN_MOD__WIDTH                                            5
#define CL_TAB__CL_GAIN_MOD__MASK                                   0x0000001fU
#define CL_TAB__CL_GAIN_MOD__READ(src)           (u_int32_t)(src) & 0x0000001fU
#define CL_TAB__CL_GAIN_MOD__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))

/* macros for field carr_lk_dc_add_Q */
#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT                                       5
#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH                                      11
#define CL_TAB__CARR_LK_DC_ADD_Q__MASK                              0x0000ffe0U
#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ffe0U) >> 5)
#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x0000ffe0U)
#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffe0U) | (((u_int32_t)(src) <<\
                    5) & 0x0000ffe0U)
#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x0000ffe0U)))

/* macros for field carr_lk_dc_add_I */
#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT                                      16
#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH                                      11
#define CL_TAB__CARR_LK_DC_ADD_I__MASK                              0x07ff0000U
#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x07ff0000U)
#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x07ff0000U)
#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x07ff0000U)))

/* macros for field bb_gain */
#define CL_TAB__BB_GAIN__SHIFT                                               27
#define CL_TAB__BB_GAIN__WIDTH                                                4
#define CL_TAB__BB_GAIN__MASK                                       0x78000000U
#define CL_TAB__BB_GAIN__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
#define CL_TAB__BB_GAIN__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
#define CL_TAB__BB_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define CL_TAB__BB_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))
#define CL_TAB__TYPE                                                  u_int32_t
#define CL_TAB__READ                                                0x7fffffffU
#define CL_TAB__WRITE                                               0x7fffffffU

#endif /* __CL_TAB_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_tab_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_TAB_B1__NUM                   16

/* macros for BlueprintGlobalNameSpace::chan_info_gain_b1 */
#ifndef __CHAN_INFO_GAIN_B1_MACRO__
#define __CHAN_INFO_GAIN_B1_MACRO__

/* macros for field chan_info_rssi_1 */
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__SHIFT                            0
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__WIDTH                            8
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__MASK                   0x000000ffU
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU

/* macros for field chan_info_rf_gain_1 */
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__SHIFT                         8
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__WIDTH                         8
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__MASK                0x0000ff00U
#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field chan_info_mb_gain_1 */
#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__SHIFT                        16
#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__WIDTH                         7
#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__MASK                0x007f0000U
#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)

/* macros for field chan_info_xatten1_sw_1 */
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SHIFT                     23
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__WIDTH                      1
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__MASK             0x00800000U
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field chan_info_xatten2_sw_1 */
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SHIFT                     24
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__WIDTH                      1
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__MASK             0x01000000U
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define CHAN_INFO_GAIN_B1__TYPE                                       u_int32_t
#define CHAN_INFO_GAIN_B1__READ                                     0x01ffffffU

#endif /* __CHAN_INFO_GAIN_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_chan_info_gain_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CHAN_INFO_GAIN_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::tpc_4_b1 */
#ifndef __TPC_4_B1_MACRO__
#define __TPC_4_B1_MACRO__

/* macros for field pd_avg_valid_1 */
#define TPC_4_B1__PD_AVG_VALID_1__SHIFT                                       0
#define TPC_4_B1__PD_AVG_VALID_1__WIDTH                                       1
#define TPC_4_B1__PD_AVG_VALID_1__MASK                              0x00000001U
#define TPC_4_B1__PD_AVG_VALID_1__READ(src)      (u_int32_t)(src) & 0x00000001U
#define TPC_4_B1__PD_AVG_VALID_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TPC_4_B1__PD_AVG_VALID_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field pd_avg_out_1 */
#define TPC_4_B1__PD_AVG_OUT_1__SHIFT                                         1
#define TPC_4_B1__PD_AVG_OUT_1__WIDTH                                         8
#define TPC_4_B1__PD_AVG_OUT_1__MASK                                0x000001feU
#define TPC_4_B1__PD_AVG_OUT_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)

/* macros for field dac_gain_1 */
#define TPC_4_B1__DAC_GAIN_1__SHIFT                                           9
#define TPC_4_B1__DAC_GAIN_1__WIDTH                                           5
#define TPC_4_B1__DAC_GAIN_1__MASK                                  0x00003e00U
#define TPC_4_B1__DAC_GAIN_1__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)

/* macros for field tx_gain_setting_1 */
#define TPC_4_B1__TX_GAIN_SETTING_1__SHIFT                                   14
#define TPC_4_B1__TX_GAIN_SETTING_1__WIDTH                                    6
#define TPC_4_B1__TX_GAIN_SETTING_1__MASK                           0x000fc000U
#define TPC_4_B1__TX_GAIN_SETTING_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fc000U) >> 14)

/* macros for field rate_sent_1 */
#define TPC_4_B1__RATE_SENT_1__SHIFT                                         20
#define TPC_4_B1__RATE_SENT_1__WIDTH                                          5
#define TPC_4_B1__RATE_SENT_1__MASK                                 0x01f00000U
#define TPC_4_B1__RATE_SENT_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_4_B1__TYPE                                                u_int32_t
#define TPC_4_B1__READ                                              0x01ffffffU

#endif /* __TPC_4_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_4_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_4_B1__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_5_b1 */
#ifndef __TPC_5_B1_MACRO__
#define __TPC_5_B1_MACRO__

/* macros for field pd_gain_boundary_1_1 */
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__SHIFT                                 4
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WIDTH                                 6
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MASK                        0x000003f0U
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field pd_gain_boundary_2_1 */
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__SHIFT                                10
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WIDTH                                 6
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MASK                        0x0000fc00U
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fc00U) >> 10)
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0000fc00U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0000fc00U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0000fc00U)))

/* macros for field pd_gain_boundary_3_1 */
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__SHIFT                                16
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WIDTH                                 6
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MASK                        0x003f0000U
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field pd_gain_boundary_4_1 */
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__SHIFT                                22
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WIDTH                                 6
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MASK                        0x0fc00000U
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fc00000U) >> 22)
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x0fc00000U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x0fc00000U)
#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x0fc00000U)))
#define TPC_5_B1__TYPE                                                u_int32_t
#define TPC_5_B1__READ                                              0x0ffffff0U
#define TPC_5_B1__WRITE                                             0x0ffffff0U

#endif /* __TPC_5_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_5_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_5_B1__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_6_b1 */
#ifndef __TPC_6_B1_MACRO__
#define __TPC_6_B1_MACRO__

/* macros for field pd_dac_setting_1_1 */
#define TPC_6_B1__PD_DAC_SETTING_1_1__SHIFT                                   0
#define TPC_6_B1__PD_DAC_SETTING_1_1__WIDTH                                   6
#define TPC_6_B1__PD_DAC_SETTING_1_1__MASK                          0x0000003fU
#define TPC_6_B1__PD_DAC_SETTING_1_1__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define TPC_6_B1__PD_DAC_SETTING_1_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define TPC_6_B1__PD_DAC_SETTING_1_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field pd_dac_setting_2_1 */
#define TPC_6_B1__PD_DAC_SETTING_2_1__SHIFT                                   6
#define TPC_6_B1__PD_DAC_SETTING_2_1__WIDTH                                   6
#define TPC_6_B1__PD_DAC_SETTING_2_1__MASK                          0x00000fc0U
#define TPC_6_B1__PD_DAC_SETTING_2_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define TPC_6_B1__PD_DAC_SETTING_2_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define TPC_6_B1__PD_DAC_SETTING_2_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field pd_dac_setting_3_1 */
#define TPC_6_B1__PD_DAC_SETTING_3_1__SHIFT                                  12
#define TPC_6_B1__PD_DAC_SETTING_3_1__WIDTH                                   6
#define TPC_6_B1__PD_DAC_SETTING_3_1__MASK                          0x0003f000U
#define TPC_6_B1__PD_DAC_SETTING_3_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define TPC_6_B1__PD_DAC_SETTING_3_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define TPC_6_B1__PD_DAC_SETTING_3_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field pd_dac_setting_4_1 */
#define TPC_6_B1__PD_DAC_SETTING_4_1__SHIFT                                  18
#define TPC_6_B1__PD_DAC_SETTING_4_1__WIDTH                                   6
#define TPC_6_B1__PD_DAC_SETTING_4_1__MASK                          0x00fc0000U
#define TPC_6_B1__PD_DAC_SETTING_4_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define TPC_6_B1__PD_DAC_SETTING_4_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00fc0000U)
#define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define TPC_6_B1__PD_DAC_SETTING_4_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field error_est_mode */
#define TPC_6_B1__ERROR_EST_MODE__SHIFT                                      24
#define TPC_6_B1__ERROR_EST_MODE__WIDTH                                       2
#define TPC_6_B1__ERROR_EST_MODE__MASK                              0x03000000U
#define TPC_6_B1__ERROR_EST_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03000000U) >> 24)
#define TPC_6_B1__ERROR_EST_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x03000000U)
#define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define TPC_6_B1__ERROR_EST_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field error_est_filter_coeff */
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__SHIFT                              26
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WIDTH                               3
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MASK                      0x1c000000U
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define TPC_6_B1__ERROR_EST_FILTER_COEFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))
#define TPC_6_B1__TYPE                                                u_int32_t
#define TPC_6_B1__READ                                              0x1fffffffU
#define TPC_6_B1__WRITE                                             0x1fffffffU

#endif /* __TPC_6_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_6_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_6_B1__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_11_b1 */
#ifndef __TPC_11_B1_MACRO__
#define __TPC_11_B1_MACRO__

/* macros for field olpc_gain_delta_1 */
#define TPC_11_B1__OLPC_GAIN_DELTA_1__SHIFT                                  16
#define TPC_11_B1__OLPC_GAIN_DELTA_1__WIDTH                                   8
#define TPC_11_B1__OLPC_GAIN_DELTA_1__MASK                          0x00ff0000U
#define TPC_11_B1__OLPC_GAIN_DELTA_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TPC_11_B1__OLPC_GAIN_DELTA_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TPC_11_B1__OLPC_GAIN_DELTA_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field olpc_gain_delta_1_pal_on */
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__SHIFT                           24
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WIDTH                            8
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MASK                   0xff000000U
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define TPC_11_B1__TYPE                                               u_int32_t
#define TPC_11_B1__READ                                             0xffff0000U
#define TPC_11_B1__WRITE                                            0xffff0000U

#endif /* __TPC_11_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_11_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_11_B1__NUM                    1

/* macros for BlueprintGlobalNameSpace::tpc_19_b1 */
#ifndef __TPC_19_B1_MACRO__
#define __TPC_19_B1_MACRO__

/* macros for field alpha_therm_1 */
#define TPC_19_B1__ALPHA_THERM_1__SHIFT                                       0
#define TPC_19_B1__ALPHA_THERM_1__WIDTH                                       8
#define TPC_19_B1__ALPHA_THERM_1__MASK                              0x000000ffU
#define TPC_19_B1__ALPHA_THERM_1__READ(src)      (u_int32_t)(src) & 0x000000ffU
#define TPC_19_B1__ALPHA_THERM_1__WRITE(src)   ((u_int32_t)(src) & 0x000000ffU)
#define TPC_19_B1__ALPHA_THERM_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TPC_19_B1__ALPHA_THERM_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field alpha_therm_pal_on_1 */
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__SHIFT                                8
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WIDTH                                8
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MASK                       0x0000ff00U
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field alpha_volt_1 */
#define TPC_19_B1__ALPHA_VOLT_1__SHIFT                                       16
#define TPC_19_B1__ALPHA_VOLT_1__WIDTH                                        7
#define TPC_19_B1__ALPHA_VOLT_1__MASK                               0x007f0000U
#define TPC_19_B1__ALPHA_VOLT_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)
#define TPC_19_B1__ALPHA_VOLT_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x007f0000U)
#define TPC_19_B1__ALPHA_VOLT_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x007f0000U)
#define TPC_19_B1__ALPHA_VOLT_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x007f0000U)))

/* macros for field alpha_volt_pal_on_1 */
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__SHIFT                                23
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WIDTH                                 7
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MASK                        0x3f800000U
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f800000U) >> 23)
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x3f800000U)
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))
#define TPC_19_B1__TYPE                                               u_int32_t
#define TPC_19_B1__READ                                             0x3fffffffU
#define TPC_19_B1__WRITE                                            0x3fffffffU

#endif /* __TPC_19_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_19_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_19_B1__NUM                    1

/* macros for BlueprintGlobalNameSpace::pdadc_tab */
#ifndef __PDADC_TAB_MACRO__
#define __PDADC_TAB_MACRO__

/* macros for field tab_entry */
#define PDADC_TAB__TAB_ENTRY__SHIFT                                           0
#define PDADC_TAB__TAB_ENTRY__WIDTH                                          32
#define PDADC_TAB__TAB_ENTRY__MASK                                  0xffffffffU
#define PDADC_TAB__TAB_ENTRY__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define PDADC_TAB__TYPE                                               u_int32_t
#define PDADC_TAB__WRITE                                            0x00000000U

#endif /* __PDADC_TAB_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_pdadc_tab_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_PDADC_TAB_B1__NUM                32

/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b1 */
#ifndef __RTT_TABLE_SW_INTF_B1_MACRO__
#define __RTT_TABLE_SW_INTF_B1_MACRO__

/* macros for field sw_rtt_table_access_1 */
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__SHIFT                    0
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WIDTH                    1
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MASK           0x00000001U
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field sw_rtt_table_write_1 */
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__SHIFT                     1
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WIDTH                     1
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MASK            0x00000002U
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field sw_rtt_table_addr_1 */
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__SHIFT                      2
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WIDTH                      3
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MASK             0x0000001cU
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))
#define RTT_TABLE_SW_INTF_B1__TYPE                                    u_int32_t
#define RTT_TABLE_SW_INTF_B1__READ                                  0x0000001fU
#define RTT_TABLE_SW_INTF_B1__WRITE                                 0x0000001fU

#endif /* __RTT_TABLE_SW_INTF_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_rtt_table_sw_intf_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_RTT_TABLE_SW_INTF_B1__NUM         1

/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b1 */
#ifndef __RTT_TABLE_SW_INTF_1_B1_MACRO__
#define __RTT_TABLE_SW_INTF_1_B1_MACRO__

/* macros for field sw_rtt_table_data_1 */
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__SHIFT                    4
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WIDTH                   28
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MASK           0xfffffff0U
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfffffff0U) >> 4)
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0xfffffff0U)
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffff0U) | (((u_int32_t)(src) <<\
                    4) & 0xfffffff0U)
#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0xfffffff0U)))
#define RTT_TABLE_SW_INTF_1_B1__TYPE                                  u_int32_t
#define RTT_TABLE_SW_INTF_1_B1__READ                                0xfffffff0U
#define RTT_TABLE_SW_INTF_1_B1__WRITE                               0xfffffff0U

#endif /* __RTT_TABLE_SW_INTF_1_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_rtt_table_sw_intf_1_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B1__NUM       1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b1 */
#ifndef __TXIQ_CORR_COEFF_01_B1_MACRO__
#define __TXIQ_CORR_COEFF_01_B1_MACRO__

/* macros for field iqc_coeff_table_0_1 */
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__SHIFT                     0
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WIDTH                    14
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_1_1 */
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__SHIFT                    14
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WIDTH                    14
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_01_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_01_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_01_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_01_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_01_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_01_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b1 */
#ifndef __TXIQ_CORR_COEFF_23_B1_MACRO__
#define __TXIQ_CORR_COEFF_23_B1_MACRO__

/* macros for field iqc_coeff_table_2_1 */
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__SHIFT                     0
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WIDTH                    14
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_3_1 */
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__SHIFT                    14
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WIDTH                    14
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_23_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_23_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_23_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_23_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_23_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_23_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b1 */
#ifndef __TXIQ_CORR_COEFF_45_B1_MACRO__
#define __TXIQ_CORR_COEFF_45_B1_MACRO__

/* macros for field iqc_coeff_table_4_1 */
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__SHIFT                     0
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WIDTH                    14
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_5_1 */
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__SHIFT                    14
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WIDTH                    14
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_45_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_45_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_45_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_45_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_45_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_45_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b1 */
#ifndef __TXIQ_CORR_COEFF_67_B1_MACRO__
#define __TXIQ_CORR_COEFF_67_B1_MACRO__

/* macros for field iqc_coeff_table_6_1 */
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__SHIFT                     0
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WIDTH                    14
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_7_1 */
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__SHIFT                    14
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WIDTH                    14
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_67_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_67_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_67_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_67_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_67_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_67_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b1 */
#ifndef __TXIQ_CORR_COEFF_89_B1_MACRO__
#define __TXIQ_CORR_COEFF_89_B1_MACRO__

/* macros for field iqc_coeff_table_8_1 */
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__SHIFT                     0
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WIDTH                    14
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_9_1 */
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__SHIFT                    14
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WIDTH                    14
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_89_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_89_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_89_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_89_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_89_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_89_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b1 */
#ifndef __TXIQ_CORR_COEFF_AB_B1_MACRO__
#define __TXIQ_CORR_COEFF_AB_B1_MACRO__

/* macros for field iqc_coeff_table_a_1 */
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__SHIFT                     0
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WIDTH                    14
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_b_1 */
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__SHIFT                    14
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WIDTH                    14
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_AB_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_AB_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_AB_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_AB_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_ab_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b1 */
#ifndef __TXIQ_CORR_COEFF_CD_B1_MACRO__
#define __TXIQ_CORR_COEFF_CD_B1_MACRO__

/* macros for field iqc_coeff_table_c_1 */
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__SHIFT                     0
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WIDTH                    14
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_d_1 */
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__SHIFT                    14
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WIDTH                    14
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_CD_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_CD_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_CD_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_CD_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_cd_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b1 */
#ifndef __TXIQ_CORR_COEFF_EF_B1_MACRO__
#define __TXIQ_CORR_COEFF_EF_B1_MACRO__

/* macros for field iqc_coeff_table_e_1 */
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__SHIFT                     0
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WIDTH                    14
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_f_1 */
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__SHIFT                    14
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WIDTH                    14
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_EF_B1__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_EF_B1__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_EF_B1__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_EF_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_ef_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B1__NUM        1

/* macros for BlueprintGlobalNameSpace::txiqcal_status_b1 */
#ifndef __TXIQCAL_STATUS_B1_MACRO__
#define __TXIQCAL_STATUS_B1_MACRO__

/* macros for field txiqcal_failed_1 */
#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SHIFT                            0
#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__WIDTH                            1
#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__MASK                   0x00000001U
#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field calibrated_gains_1 */
#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__SHIFT                          1
#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__WIDTH                          5
#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__MASK                 0x0000003eU
#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003eU) >> 1)

/* macros for field tone_gain_used_1 */
#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__SHIFT                            6
#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__WIDTH                            6
#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__MASK                   0x00000fc0U
#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)

/* macros for field rx_gain_used_1 */
#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__SHIFT                             12
#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__WIDTH                              6
#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__MASK                     0x0003f000U
#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)

/* macros for field last_meas_addr_1 */
#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__SHIFT                           18
#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__WIDTH                            6
#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__MASK                   0x00fc0000U
#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define TXIQCAL_STATUS_B1__TYPE                                       u_int32_t
#define TXIQCAL_STATUS_B1__READ                                     0x00ffffffU

#endif /* __TXIQCAL_STATUS_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiqcal_status_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQCAL_STATUS_B1__NUM            1

/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b1 */
#ifndef __TABLES_INTF_ADDR_B1_MACRO__
#define __TABLES_INTF_ADDR_B1_MACRO__

/* macros for field tables_addr_1 */
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__SHIFT                             2
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WIDTH                            16
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MASK                    0x0003fffcU
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field addr_auto_incr_1 */
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__SHIFT                         31
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WIDTH                          1
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MASK                 0x80000000U
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TABLES_INTF_ADDR_B1__TYPE                                     u_int32_t
#define TABLES_INTF_ADDR_B1__READ                                   0x8003fffcU
#define TABLES_INTF_ADDR_B1__WRITE                                  0x8003fffcU

#endif /* __TABLES_INTF_ADDR_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tables_intf_addr_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TABLES_INTF_ADDR_B1__NUM          1

/* macros for BlueprintGlobalNameSpace::tables_intf_data_b1 */
#ifndef __TABLES_INTF_DATA_B1_MACRO__
#define __TABLES_INTF_DATA_B1_MACRO__

/* macros for field tables_data_1 */
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__SHIFT                             0
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__WIDTH                            32
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__MASK                    0xffffffffU
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TABLES_INTF_DATA_B1__TABLES_DATA_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TABLES_INTF_DATA_B1__TYPE                                     u_int32_t
#define TABLES_INTF_DATA_B1__READ                                   0xffffffffU
#define TABLES_INTF_DATA_B1__WRITE                                  0xffffffffU

#endif /* __TABLES_INTF_DATA_B1_MACRO__ */


/* macros for bb_reg_map.bb_sm1_reg_map.BB_tables_intf_data_b1 */
#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TABLES_INTF_DATA_B1__NUM          1

/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b2 */
#ifndef __EXT_CHAN_PWR_THR_2_B2_MACRO__
#define __EXT_CHAN_PWR_THR_2_B2_MACRO__

/* macros for field cf_maxCCApwr_ext_2 */
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__SHIFT                      0
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WIDTH                      9
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MASK             0x000001ffU
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field minCCApwr_ext_2 */
#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__SHIFT                        16
#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__WIDTH                         9
#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__MASK                0x01ff0000U
#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01ff0000U) >> 16)
#define EXT_CHAN_PWR_THR_2_B2__TYPE                                   u_int32_t
#define EXT_CHAN_PWR_THR_2_B2__READ                                 0x01ff01ffU
#define EXT_CHAN_PWR_THR_2_B2__WRITE                                0x01ff01ffU

#endif /* __EXT_CHAN_PWR_THR_2_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_ext_chan_pwr_thr_2_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B2__NUM       1

/* macros for BlueprintGlobalNameSpace::spur_report_b2 */
#ifndef __SPUR_REPORT_B2_MACRO__
#define __SPUR_REPORT_B2_MACRO__

/* macros for field spur_est_i_2 */
#define SPUR_REPORT_B2__SPUR_EST_I_2__SHIFT                                   0
#define SPUR_REPORT_B2__SPUR_EST_I_2__WIDTH                                   8
#define SPUR_REPORT_B2__SPUR_EST_I_2__MASK                          0x000000ffU
#define SPUR_REPORT_B2__SPUR_EST_I_2__READ(src)  (u_int32_t)(src) & 0x000000ffU

/* macros for field spur_est_q_2 */
#define SPUR_REPORT_B2__SPUR_EST_Q_2__SHIFT                                   8
#define SPUR_REPORT_B2__SPUR_EST_Q_2__WIDTH                                   8
#define SPUR_REPORT_B2__SPUR_EST_Q_2__MASK                          0x0000ff00U
#define SPUR_REPORT_B2__SPUR_EST_Q_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field power_with_spur_removed_2 */
#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__SHIFT                     16
#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__WIDTH                     16
#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__MASK             0xffff0000U
#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xffff0000U) >> 16)
#define SPUR_REPORT_B2__TYPE                                          u_int32_t
#define SPUR_REPORT_B2__READ                                        0xffffffffU

#endif /* __SPUR_REPORT_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_spur_report_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_SPUR_REPORT_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b2 */
#ifndef __IQ_ADC_MEAS_0_B2_MACRO__
#define __IQ_ADC_MEAS_0_B2_MACRO__

/* macros for field gain_dc_iq_cal_meas_0_2 */
#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__SHIFT                      0
#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__WIDTH                     32
#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__MASK             0xffffffffU
#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_0_B2__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_0_B2__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_0_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_0_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_0_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b2 */
#ifndef __IQ_ADC_MEAS_1_B2_MACRO__
#define __IQ_ADC_MEAS_1_B2_MACRO__

/* macros for field gain_dc_iq_cal_meas_1_2 */
#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__SHIFT                      0
#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__WIDTH                     32
#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__MASK             0xffffffffU
#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_1_B2__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_1_B2__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_1_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_1_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_1_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b2 */
#ifndef __IQ_ADC_MEAS_2_B2_MACRO__
#define __IQ_ADC_MEAS_2_B2_MACRO__

/* macros for field gain_dc_iq_cal_meas_2_2 */
#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__SHIFT                      0
#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__WIDTH                     32
#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__MASK             0xffffffffU
#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_2_B2__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_2_B2__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_2_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_2_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_2_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b2 */
#ifndef __IQ_ADC_MEAS_3_B2_MACRO__
#define __IQ_ADC_MEAS_3_B2_MACRO__

/* macros for field gain_dc_iq_cal_meas_3_2 */
#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__SHIFT                      0
#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__WIDTH                     32
#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__MASK             0xffffffffU
#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define IQ_ADC_MEAS_3_B2__TYPE                                        u_int32_t
#define IQ_ADC_MEAS_3_B2__READ                                      0xffffffffU

#endif /* __IQ_ADC_MEAS_3_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_3_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_3_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b2 */
#ifndef __TX_PHASE_RAMP_B2_MACRO__
#define __TX_PHASE_RAMP_B2_MACRO__

/* macros for field cf_phase_ramp_enable_2 */
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SHIFT                       0
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WIDTH                       1
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MASK              0x00000001U
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field cf_phase_ramp_bias_2 */
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__SHIFT                         1
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WIDTH                         6
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MASK                0x0000007eU
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000007eU) >> 1)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000007eU)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000007eU)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000007eU)))

/* macros for field cf_phase_ramp_init_2 */
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__SHIFT                         7
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WIDTH                        10
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MASK                0x0001ff80U
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001ff80U) >> 7)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x0001ff80U)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ff80U) | (((u_int32_t)(src) <<\
                    7) & 0x0001ff80U)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x0001ff80U)))

/* macros for field cf_phase_ramp_alpha_2 */
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__SHIFT                       17
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WIDTH                        8
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MASK               0x01fe0000U
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fe0000U) >> 17)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x01fe0000U)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x01fe0000U)
#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x01fe0000U)))
#define TX_PHASE_RAMP_B2__TYPE                                        u_int32_t
#define TX_PHASE_RAMP_B2__READ                                      0x01ffffffU
#define TX_PHASE_RAMP_B2__WRITE                                     0x01ffffffU

#endif /* __TX_PHASE_RAMP_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_tx_phase_ramp_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_TX_PHASE_RAMP_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b2 */
#ifndef __ADC_GAIN_DC_CORR_B2_MACRO__
#define __ADC_GAIN_DC_CORR_B2_MACRO__

/* macros for field adc_gain_corr_q_coeff_2 */
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__SHIFT                   0
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WIDTH                   6
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MASK          0x0000003fU
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field adc_gain_corr_i_coeff_2 */
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__SHIFT                   6
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WIDTH                   6
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MASK          0x00000fc0U
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field adc_dc_corr_q_coeff_2 */
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__SHIFT                    12
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WIDTH                     9
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MASK            0x001ff000U
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001ff000U) >> 12)
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x001ff000U)
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x001ff000U)
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x001ff000U)))

/* macros for field adc_dc_corr_i_coeff_2 */
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__SHIFT                    21
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WIDTH                     9
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MASK            0x3fe00000U
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3fe00000U) >> 21)
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x3fe00000U)
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fe00000U) | (((u_int32_t)(src) <<\
                    21) & 0x3fe00000U)
#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x3fe00000U)))
#define ADC_GAIN_DC_CORR_B2__TYPE                                     u_int32_t
#define ADC_GAIN_DC_CORR_B2__READ                                   0x3fffffffU
#define ADC_GAIN_DC_CORR_B2__WRITE                                  0x3fffffffU

#endif /* __ADC_GAIN_DC_CORR_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_adc_gain_dc_corr_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_ADC_GAIN_DC_CORR_B2__NUM         1

/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b2 */
#ifndef __RX_IQ_CORR_B2_MACRO__
#define __RX_IQ_CORR_B2_MACRO__

/* macros for field rx_iqcorr_q_q_coff_2 */
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__SHIFT                            0
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WIDTH                            7
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MASK                   0x0000007fU
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field rx_iqcorr_q_i_coff_2 */
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__SHIFT                            7
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WIDTH                            7
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MASK                   0x00003f80U
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f80U) >> 7)
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00003f80U)
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00003f80U)
#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00003f80U)))

/* macros for field loopback_iqcorr_q_q_coff_2 */
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__SHIFT                     15
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WIDTH                      7
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MASK             0x003f8000U
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f8000U) >> 15)
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x003f8000U)
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f8000U) | (((u_int32_t)(src) <<\
                    15) & 0x003f8000U)
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x003f8000U)))

/* macros for field loopback_iqcorr_q_i_coff_2 */
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__SHIFT                     22
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WIDTH                      7
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MASK             0x1fc00000U
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1fc00000U) >> 22)
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x1fc00000U)
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x1fc00000U)
#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x1fc00000U)))
#define RX_IQ_CORR_B2__TYPE                                           u_int32_t
#define RX_IQ_CORR_B2__READ                                         0x1fffbfffU
#define RX_IQ_CORR_B2__WRITE                                        0x1fffbfffU

#endif /* __RX_IQ_CORR_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_rx_iq_corr_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_RX_IQ_CORR_B2__NUM               1

/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b2 */
#ifndef __PAPRD_CTRL0_B2_MACRO__
#define __PAPRD_CTRL0_B2_MACRO__

/* macros for field paprd_enable_2 */
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SHIFT                                 0
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WIDTH                                 1
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MASK                        0x00000001U
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_adaptive_use_single_table_2 */
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SHIFT              1
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WIDTH              1
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MASK     0x00000002U
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_valid_gain_2 */
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__SHIFT                             2
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WIDTH                            25
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MASK                    0x07fffffcU
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fffffcU) >> 2)
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x07fffffcU)
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fffffcU) | (((u_int32_t)(src) <<\
                    2) & 0x07fffffcU)
#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x07fffffcU)))

/* macros for field paprd_mag_thrsh_2 */
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__SHIFT                             27
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WIDTH                              5
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MASK                     0xf8000000U
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf8000000U) >> 27)
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0xf8000000U)
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define PAPRD_CTRL0_B2__TYPE                                          u_int32_t
#define PAPRD_CTRL0_B2__READ                                        0xffffffffU
#define PAPRD_CTRL0_B2__WRITE                                       0xffffffffU

#endif /* __PAPRD_CTRL0_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_ctrl0_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_CTRL0_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b2 */
#ifndef __PAPRD_CTRL1_B2_MACRO__
#define __PAPRD_CTRL1_B2_MACRO__

/* macros for field paprd_adaptive_scaling_enable_2 */
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SHIFT                0
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WIDTH                1
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MASK       0x00000001U
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field paprd_adaptive_am2am_enable_2 */
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SHIFT                  1
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WIDTH                  1
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MASK         0x00000002U
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field paprd_adaptive_am2pm_enable_2 */
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SHIFT                  2
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WIDTH                  1
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MASK         0x00000004U
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field paprd_power_at_am2am_cal_2 */
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__SHIFT                     3
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WIDTH                     6
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MASK            0x000001f8U
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001f8U) >> 3)
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000001f8U)
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000001f8U)
#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000001f8U)))

/* macros for field pa_gain_scale_factor_2 */
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__SHIFT                         9
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WIDTH                         8
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MASK                0x0001fe00U
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001fe00U) >> 9)
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x0001fe00U)
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001fe00U) | (((u_int32_t)(src) <<\
                    9) & 0x0001fe00U)
#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x0001fe00U)))

/* macros for field paprd_mag_scale_factor_2 */
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__SHIFT                      17
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WIDTH                      10
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MASK              0x07fe0000U
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fe0000U) >> 17)
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x07fe0000U)
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x07fe0000U)
#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x07fe0000U)))

/* macros for field paprd_trainer_iandq_sel_2 */
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SHIFT                     27
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WIDTH                      1
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MASK             0x08000000U
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)
#define PAPRD_CTRL1_B2__TYPE                                          u_int32_t
#define PAPRD_CTRL1_B2__READ                                        0x0fffffffU
#define PAPRD_CTRL1_B2__WRITE                                       0x0fffffffU

#endif /* __PAPRD_CTRL1_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_ctrl1_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_CTRL1_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::pa_gain123_b2 */
#ifndef __PA_GAIN123_B2_MACRO__
#define __PA_GAIN123_B2_MACRO__

/* macros for field pa_gain1_2 */
#define PA_GAIN123_B2__PA_GAIN1_2__SHIFT                                      0
#define PA_GAIN123_B2__PA_GAIN1_2__WIDTH                                     10
#define PA_GAIN123_B2__PA_GAIN1_2__MASK                             0x000003ffU
#define PA_GAIN123_B2__PA_GAIN1_2__READ(src)     (u_int32_t)(src) & 0x000003ffU
#define PA_GAIN123_B2__PA_GAIN1_2__WRITE(src)  ((u_int32_t)(src) & 0x000003ffU)
#define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PA_GAIN123_B2__PA_GAIN1_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field pa_gain2_2 */
#define PA_GAIN123_B2__PA_GAIN2_2__SHIFT                                     10
#define PA_GAIN123_B2__PA_GAIN2_2__WIDTH                                     10
#define PA_GAIN123_B2__PA_GAIN2_2__MASK                             0x000ffc00U
#define PA_GAIN123_B2__PA_GAIN2_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define PA_GAIN123_B2__PA_GAIN2_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define PA_GAIN123_B2__PA_GAIN2_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field pa_gain3_2 */
#define PA_GAIN123_B2__PA_GAIN3_2__SHIFT                                     20
#define PA_GAIN123_B2__PA_GAIN3_2__WIDTH                                     10
#define PA_GAIN123_B2__PA_GAIN3_2__MASK                             0x3ff00000U
#define PA_GAIN123_B2__PA_GAIN3_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3ff00000U) >> 20)
#define PA_GAIN123_B2__PA_GAIN3_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x3ff00000U)
#define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
                    20) & 0x3ff00000U)
#define PA_GAIN123_B2__PA_GAIN3_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x3ff00000U)))
#define PA_GAIN123_B2__TYPE                                           u_int32_t
#define PA_GAIN123_B2__READ                                         0x3fffffffU
#define PA_GAIN123_B2__WRITE                                        0x3fffffffU

#endif /* __PA_GAIN123_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_pa_gain123_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PA_GAIN123_B2__NUM               1

/* macros for BlueprintGlobalNameSpace::pa_gain45_b2 */
#ifndef __PA_GAIN45_B2_MACRO__
#define __PA_GAIN45_B2_MACRO__

/* macros for field pa_gain4_2 */
#define PA_GAIN45_B2__PA_GAIN4_2__SHIFT                                       0
#define PA_GAIN45_B2__PA_GAIN4_2__WIDTH                                      10
#define PA_GAIN45_B2__PA_GAIN4_2__MASK                              0x000003ffU
#define PA_GAIN45_B2__PA_GAIN4_2__READ(src)      (u_int32_t)(src) & 0x000003ffU
#define PA_GAIN45_B2__PA_GAIN4_2__WRITE(src)   ((u_int32_t)(src) & 0x000003ffU)
#define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define PA_GAIN45_B2__PA_GAIN4_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field pa_gain5_2 */
#define PA_GAIN45_B2__PA_GAIN5_2__SHIFT                                      10
#define PA_GAIN45_B2__PA_GAIN5_2__WIDTH                                      10
#define PA_GAIN45_B2__PA_GAIN5_2__MASK                              0x000ffc00U
#define PA_GAIN45_B2__PA_GAIN5_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000ffc00U) >> 10)
#define PA_GAIN45_B2__PA_GAIN5_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x000ffc00U)
#define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
                    10) & 0x000ffc00U)
#define PA_GAIN45_B2__PA_GAIN5_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x000ffc00U)))

/* macros for field paprd_adaptive_table_valid_2 */
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__SHIFT                    20
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WIDTH                     5
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MASK            0x01f00000U
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x01f00000U)
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x01f00000U)
#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x01f00000U)))
#define PA_GAIN45_B2__TYPE                                            u_int32_t
#define PA_GAIN45_B2__READ                                          0x01ffffffU
#define PA_GAIN45_B2__WRITE                                         0x01ffffffU

#endif /* __PA_GAIN45_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_pa_gain45_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PA_GAIN45_B2__NUM                1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_0_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_0_B2_MACRO__

/* macros for field paprd_pre_post_scaling_0_2 */
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_0_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_0_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_0_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_0_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_1_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_1_B2_MACRO__

/* macros for field paprd_pre_post_scaling_1_2 */
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_1_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_1_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_1_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_1_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_2_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_2_B2_MACRO__

/* macros for field paprd_pre_post_scaling_2_2 */
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_2_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_2_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_2_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_2_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_3_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_3_B2_MACRO__

/* macros for field paprd_pre_post_scaling_3_2 */
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_3_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_3_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_3_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_3_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_4_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_4_B2_MACRO__

/* macros for field paprd_pre_post_scaling_4_2 */
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_4_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_4_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_4_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_4_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_5_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_5_B2_MACRO__

/* macros for field paprd_pre_post_scaling_5_2 */
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_5_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_5_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_5_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_5_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_6_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_6_B2_MACRO__

/* macros for field paprd_pre_post_scaling_6_2 */
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_6_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_6_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_6_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_6_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b2 */
#ifndef __PAPRD_PRE_POST_SCALE_7_B2_MACRO__
#define __PAPRD_PRE_POST_SCALE_7_B2_MACRO__

/* macros for field paprd_pre_post_scaling_7_2 */
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__SHIFT          0
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WIDTH         18
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MASK 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0003ffffU)))
#define PAPRD_PRE_POST_SCALE_7_B2__TYPE                               u_int32_t
#define PAPRD_PRE_POST_SCALE_7_B2__READ                             0x0003ffffU
#define PAPRD_PRE_POST_SCALE_7_B2__WRITE                            0x0003ffffU

#endif /* __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_7_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B2__NUM   1

/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */
#ifndef __PAPRD_MEM_TAB_MACRO__
#define __PAPRD_MEM_TAB_MACRO__

/* macros for field paprd_mem */
#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT                                       0
#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH                                      22
#define PAPRD_MEM_TAB__PAPRD_MEM__MASK                              0x003fffffU
#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src)      (u_int32_t)(src) & 0x003fffffU
#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src)   ((u_int32_t)(src) & 0x003fffffU)
#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003fffffU) | ((u_int32_t)(src) &\
                    0x003fffffU)
#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x003fffffU)))
#define PAPRD_MEM_TAB__TYPE                                           u_int32_t
#define PAPRD_MEM_TAB__READ                                         0x003fffffU
#define PAPRD_MEM_TAB__WRITE                                        0x003fffffU

#endif /* __PAPRD_MEM_TAB_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_mem_tab_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_MEM_TAB_B2__NUM          120

/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */
#ifndef __CHAN_INFO_CHAN_TAB_MACRO__
#define __CHAN_INFO_CHAN_TAB_MACRO__

/* macros for field chaninfo_word */
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT                              0
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH                             32
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK                     0xffffffffU
#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CHAN_INFO_CHAN_TAB__TYPE                                      u_int32_t
#define CHAN_INFO_CHAN_TAB__READ                                    0xffffffffU

#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_chan_info_chan_tab_b2 */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B2__NUM      60

/* macros for BlueprintGlobalNameSpace::chn2_tables_intf_addr */
#ifndef __CHN2_TABLES_INTF_ADDR_MACRO__
#define __CHN2_TABLES_INTF_ADDR_MACRO__

/* macros for field chn2_tables_addr */
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__SHIFT                        2
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WIDTH                       16
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MASK               0x0003fffcU
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field chn2_addr_auto_incr */
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__SHIFT                    31
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WIDTH                     1
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MASK            0x80000000U
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define CHN2_TABLES_INTF_ADDR__TYPE                                   u_int32_t
#define CHN2_TABLES_INTF_ADDR__READ                                 0x8003fffcU
#define CHN2_TABLES_INTF_ADDR__WRITE                                0x8003fffcU

#endif /* __CHN2_TABLES_INTF_ADDR_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_chn2_tables_intf_addr */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHN2_TABLES_INTF_ADDR__NUM       1

/* macros for BlueprintGlobalNameSpace::chn2_tables_intf_data */
#ifndef __CHN2_TABLES_INTF_DATA_MACRO__
#define __CHN2_TABLES_INTF_DATA_MACRO__

/* macros for field chn2_tables_data */
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__SHIFT                        0
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WIDTH                       32
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MASK               0xffffffffU
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CHN2_TABLES_INTF_DATA__TYPE                                   u_int32_t
#define CHN2_TABLES_INTF_DATA__READ                                 0xffffffffU
#define CHN2_TABLES_INTF_DATA__WRITE                                0xffffffffU

#endif /* __CHN2_TABLES_INTF_DATA_MACRO__ */


/* macros for bb_reg_map.bb_chn2_reg_map.BB_chn2_tables_intf_data */
#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHN2_TABLES_INTF_DATA__NUM       1

/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b2 */
#ifndef __GAIN_FORCE_MAX_GAINS_B2_MACRO__
#define __GAIN_FORCE_MAX_GAINS_B2_MACRO__

/* macros for field rf_gain_f_2 */
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__SHIFT                           0
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WIDTH                           8
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MASK                  0x000000ffU
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000000ffU)
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field mb_gain_f_2 */
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__SHIFT                           8
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WIDTH                           8
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MASK                  0x0000ff00U
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field xatten1_sw_f_2 */
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SHIFT                       16
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WIDTH                        1
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MASK               0x00010000U
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field xatten2_sw_f_2 */
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SHIFT                       17
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WIDTH                        1
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MASK               0x00020000U
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field xatten1_hyst_margin_2 */
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__SHIFT                18
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WIDTH                 7
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MASK        0x01fc0000U
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01fc0000U) >> 18)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x01fc0000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x01fc0000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x01fc0000U)))

/* macros for field xatten2_hyst_margin_2 */
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__SHIFT                25
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WIDTH                 7
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MASK        0xfe000000U
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfe000000U) >> 25)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0xfe000000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfe000000U) | (((u_int32_t)(src) <<\
                    25) & 0xfe000000U)
#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0xfe000000U)))
#define GAIN_FORCE_MAX_GAINS_B2__TYPE                                 u_int32_t
#define GAIN_FORCE_MAX_GAINS_B2__READ                               0xffffffffU
#define GAIN_FORCE_MAX_GAINS_B2__WRITE                              0xffffffffU

#endif /* __GAIN_FORCE_MAX_GAINS_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_gain_force_max_gains_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B2__NUM     1

/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b2 */
#ifndef __EXT_ATTEN_SWITCH_CTL_B2_MACRO__
#define __EXT_ATTEN_SWITCH_CTL_B2_MACRO__

/* macros for field xatten1_db_2 */
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__SHIFT                          0
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WIDTH                          6
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MASK                 0x0000003fU
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000003fU
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field xatten2_db_2 */
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__SHIFT                          6
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WIDTH                          6
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MASK                 0x00000fc0U
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field xatten1_margin_2 */
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__SHIFT                     12
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WIDTH                      5
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MASK             0x0001f000U
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field xatten2_margin_2 */
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__SHIFT                     17
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WIDTH                      5
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MASK             0x003e0000U
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003e0000U) >> 17)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x003e0000U)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field xlna_gain_db_2 */
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__SHIFT                       22
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WIDTH                        5
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MASK               0x07c00000U
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))
#define EXT_ATTEN_SWITCH_CTL_B2__TYPE                                 u_int32_t
#define EXT_ATTEN_SWITCH_CTL_B2__READ                               0x07ffffffU
#define EXT_ATTEN_SWITCH_CTL_B2__WRITE                              0x07ffffffU

#endif /* __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_ext_atten_switch_ctl_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B2__NUM     1

/* macros for BlueprintGlobalNameSpace::cca_b2 */
#ifndef __CCA_B2_MACRO__
#define __CCA_B2_MACRO__

/* macros for field cf_maxCCApwr_2 */
#define CCA_B2__CF_MAXCCAPWR_2__SHIFT                                         0
#define CCA_B2__CF_MAXCCAPWR_2__WIDTH                                         9
#define CCA_B2__CF_MAXCCAPWR_2__MASK                                0x000001ffU
#define CCA_B2__CF_MAXCCAPWR_2__READ(src)        (u_int32_t)(src) & 0x000001ffU
#define CCA_B2__CF_MAXCCAPWR_2__WRITE(src)     ((u_int32_t)(src) & 0x000001ffU)
#define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define CCA_B2__CF_MAXCCAPWR_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field minCCApwr_2 */
#define CCA_B2__MINCCAPWR_2__SHIFT                                           20
#define CCA_B2__MINCCAPWR_2__WIDTH                                            9
#define CCA_B2__MINCCAPWR_2__MASK                                   0x1ff00000U
#define CCA_B2__MINCCAPWR_2__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
#define CCA_B2__TYPE                                                  u_int32_t
#define CCA_B2__READ                                                0x1ff001ffU
#define CCA_B2__WRITE                                               0x1ff001ffU

#endif /* __CCA_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_cca_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_CCA_B2__NUM                      1

/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b2 */
#ifndef __CCA_CTRL_2_B2_MACRO__
#define __CCA_CTRL_2_B2_MACRO__

/* macros for field minCCApwr_thr_2 */
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__SHIFT                                 0
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WIDTH                                 9
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MASK                        0x000001ffU
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000001ffU)
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001ffU) | ((u_int32_t)(src) &\
                    0x000001ffU)
#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000001ffU)))

/* macros for field NF_gain_comp_2 */
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__SHIFT                                 10
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WIDTH                                  8
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MASK                         0x0003fc00U
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fc00U) >> 10)
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0003fc00U)
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0003fc00U)
#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0003fc00U)))
#define CCA_CTRL_2_B2__TYPE                                           u_int32_t
#define CCA_CTRL_2_B2__READ                                         0x0003fdffU
#define CCA_CTRL_2_B2__WRITE                                        0x0003fdffU

#endif /* __CCA_CTRL_2_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_cca_ctrl_2_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_CCA_CTRL_2_B2__NUM               1

/* macros for BlueprintGlobalNameSpace::rssi_b2 */
#ifndef __RSSI_B2_MACRO__
#define __RSSI_B2_MACRO__

/* macros for field rssi_2 */
#define RSSI_B2__RSSI_2__SHIFT                                                0
#define RSSI_B2__RSSI_2__WIDTH                                                8
#define RSSI_B2__RSSI_2__MASK                                       0x000000ffU
#define RSSI_B2__RSSI_2__READ(src)               (u_int32_t)(src) & 0x000000ffU

/* macros for field rssi_ext_2 */
#define RSSI_B2__RSSI_EXT_2__SHIFT                                            8
#define RSSI_B2__RSSI_EXT_2__WIDTH                                            8
#define RSSI_B2__RSSI_EXT_2__MASK                                   0x0000ff00U
#define RSSI_B2__RSSI_EXT_2__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define RSSI_B2__TYPE                                                 u_int32_t
#define RSSI_B2__READ                                               0x0000ffffU

#endif /* __RSSI_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_rssi_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_RSSI_B2__NUM                     1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b2 */
#ifndef __AGC_DIG_DC_STATUS_I_B2_MACRO__
#define __AGC_DIG_DC_STATUS_I_B2_MACRO__

/* macros for field dig_dc_C1_res_i_2 */
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__SHIFT                      0
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__MASK             0x000001ffU
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU

/* macros for field dig_dc_C2_res_i_2 */
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__SHIFT                      9
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__MASK             0x0003fe00U
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fe00U) >> 9)

/* macros for field dig_dc_C3_res_i_2 */
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__SHIFT                     18
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__WIDTH                      9
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__MASK             0x07fc0000U
#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fc0000U) >> 18)
#define AGC_DIG_DC_STATUS_I_B2__TYPE                                  u_int32_t
#define AGC_DIG_DC_STATUS_I_B2__READ                                0x07ffffffU

#endif /* __AGC_DIG_DC_STATUS_I_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_agc_dig_dc_status_i_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B2__NUM      1

/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b2 */
#ifndef __AGC_DIG_DC_STATUS_Q_B2_MACRO__
#define __AGC_DIG_DC_STATUS_Q_B2_MACRO__

/* macros for field dig_dc_C1_res_q_2 */
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__SHIFT                      0
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__MASK             0x000001ffU
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000001ffU

/* macros for field dig_dc_C2_res_q_2 */
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__SHIFT                      9
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__MASK             0x0003fe00U
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fe00U) >> 9)

/* macros for field dig_dc_C3_res_q_2 */
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__SHIFT                     18
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__WIDTH                      9
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__MASK             0x07fc0000U
#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07fc0000U) >> 18)
#define AGC_DIG_DC_STATUS_Q_B2__TYPE                                  u_int32_t
#define AGC_DIG_DC_STATUS_Q_B2__READ                                0x07ffffffU

#endif /* __AGC_DIG_DC_STATUS_Q_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_agc_dig_dc_status_q_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B2__NUM      1

/* macros for BlueprintGlobalNameSpace::dc_cal_status_b2 */
#ifndef __DC_CAL_STATUS_B2_MACRO__
#define __DC_CAL_STATUS_B2_MACRO__

/* macros for field offsetC1I_2 */
#define DC_CAL_STATUS_B2__OFFSETC1I_2__SHIFT                                  0
#define DC_CAL_STATUS_B2__OFFSETC1I_2__WIDTH                                  5
#define DC_CAL_STATUS_B2__OFFSETC1I_2__MASK                         0x0000001fU
#define DC_CAL_STATUS_B2__OFFSETC1I_2__READ(src) (u_int32_t)(src) & 0x0000001fU

/* macros for field offsetC1Q_2 */
#define DC_CAL_STATUS_B2__OFFSETC1Q_2__SHIFT                                  5
#define DC_CAL_STATUS_B2__OFFSETC1Q_2__WIDTH                                  5
#define DC_CAL_STATUS_B2__OFFSETC1Q_2__MASK                         0x000003e0U
#define DC_CAL_STATUS_B2__OFFSETC1Q_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003e0U) >> 5)

/* macros for field offsetC2I_2 */
#define DC_CAL_STATUS_B2__OFFSETC2I_2__SHIFT                                 10
#define DC_CAL_STATUS_B2__OFFSETC2I_2__WIDTH                                  5
#define DC_CAL_STATUS_B2__OFFSETC2I_2__MASK                         0x00007c00U
#define DC_CAL_STATUS_B2__OFFSETC2I_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007c00U) >> 10)

/* macros for field offsetC2Q_2 */
#define DC_CAL_STATUS_B2__OFFSETC2Q_2__SHIFT                                 15
#define DC_CAL_STATUS_B2__OFFSETC2Q_2__WIDTH                                  5
#define DC_CAL_STATUS_B2__OFFSETC2Q_2__MASK                         0x000f8000U
#define DC_CAL_STATUS_B2__OFFSETC2Q_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f8000U) >> 15)

/* macros for field offsetC3I_2 */
#define DC_CAL_STATUS_B2__OFFSETC3I_2__SHIFT                                 20
#define DC_CAL_STATUS_B2__OFFSETC3I_2__WIDTH                                  5
#define DC_CAL_STATUS_B2__OFFSETC3I_2__MASK                         0x01f00000U
#define DC_CAL_STATUS_B2__OFFSETC3I_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)

/* macros for field offsetC3Q_2 */
#define DC_CAL_STATUS_B2__OFFSETC3Q_2__SHIFT                                 25
#define DC_CAL_STATUS_B2__OFFSETC3Q_2__WIDTH                                  5
#define DC_CAL_STATUS_B2__OFFSETC3Q_2__MASK                         0x3e000000U
#define DC_CAL_STATUS_B2__OFFSETC3Q_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3e000000U) >> 25)
#define DC_CAL_STATUS_B2__TYPE                                        u_int32_t
#define DC_CAL_STATUS_B2__READ                                      0x3fffffffU

#endif /* __DC_CAL_STATUS_B2_MACRO__ */


/* macros for bb_reg_map.bb_agc2_reg_map.BB_dc_cal_status_b2 */
#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_DC_CAL_STATUS_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::switch_table_chn_b2 */
#ifndef __SWITCH_TABLE_CHN_B2_MACRO__
#define __SWITCH_TABLE_CHN_B2_MACRO__

/* macros for field switch_table_idle_2 */
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__SHIFT                       0
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WIDTH                       2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MASK              0x00000003U
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field switch_table_t_2 */
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__SHIFT                          2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WIDTH                          2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MASK                 0x0000000cU
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field switch_table_r_2 */
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__SHIFT                          4
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WIDTH                          2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MASK                 0x00000030U
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field switch_table_rx1_2 */
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__SHIFT                        6
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WIDTH                        2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MASK               0x000000c0U
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field switch_table_rx12_2 */
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__SHIFT                       8
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WIDTH                       2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MASK              0x00000300U
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field switch_table_b_2 */
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__SHIFT                         10
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WIDTH                          2
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MASK                 0x00000c00U
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000c00U) >> 10)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000c00U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00000c00U)
#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000c00U)))
#define SWITCH_TABLE_CHN_B2__TYPE                                     u_int32_t
#define SWITCH_TABLE_CHN_B2__READ                                   0x00000fffU
#define SWITCH_TABLE_CHN_B2__WRITE                                  0x00000fffU

#endif /* __SWITCH_TABLE_CHN_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_switch_table_chn_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_SWITCH_TABLE_CHN_B2__NUM          1

/* macros for BlueprintGlobalNameSpace::fcal_2_b2 */
#ifndef __FCAL_2_B2_MACRO__
#define __FCAL_2_B2_MACRO__

/* macros for field flc_sw_cap_val_2 */
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__SHIFT                                    3
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WIDTH                                    5
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MASK                           0x000000f8U
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f8U) >> 3)
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x000000f8U)
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f8U) | (((u_int32_t)(src) <<\
                    3) & 0x000000f8U)
#define FCAL_2_B2__FLC_SW_CAP_VAL_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x000000f8U)))

/* macros for field flc_cap_val_status_2 */
#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__SHIFT                               20
#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__WIDTH                                5
#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__MASK                       0x01f00000U
#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define FCAL_2_B2__TYPE                                               u_int32_t
#define FCAL_2_B2__READ                                             0x01f000f8U
#define FCAL_2_B2__WRITE                                            0x01f000f8U

#endif /* __FCAL_2_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_fcal_2_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_FCAL_2_B2__NUM                    1

/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b2 */
#ifndef __DFT_TONE_CTRL_B2_MACRO__
#define __DFT_TONE_CTRL_B2_MACRO__

/* macros for field dft_tone_en_2 */
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SHIFT                                0
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WIDTH                                1
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MASK                       0x00000001U
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field dft_tone_amp_sel_2 */
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__SHIFT                           2
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WIDTH                           2
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MASK                  0x0000000cU
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field dft_tone_freq_ang_2 */
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__SHIFT                          4
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WIDTH                          9
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MASK                 0x00001ff0U
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001ff0U) >> 4)
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00001ff0U)
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001ff0U) | (((u_int32_t)(src) <<\
                    4) & 0x00001ff0U)
#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00001ff0U)))
#define DFT_TONE_CTRL_B2__TYPE                                        u_int32_t
#define DFT_TONE_CTRL_B2__READ                                      0x00001ffdU
#define DFT_TONE_CTRL_B2__WRITE                                     0x00001ffdU

#endif /* __DFT_TONE_CTRL_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_dft_tone_ctrl_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_DFT_TONE_CTRL_B2__NUM             1

/* macros for BlueprintGlobalNameSpace::cl_map_0 */
#ifndef __CL_MAP_0_MACRO__
#define __CL_MAP_0_MACRO__

/* macros for field cl_map_0 */
#define CL_MAP_0__CL_MAP_0__SHIFT                                             0
#define CL_MAP_0__CL_MAP_0__WIDTH                                            32
#define CL_MAP_0__CL_MAP_0__MASK                                    0xffffffffU
#define CL_MAP_0__CL_MAP_0__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_0__CL_MAP_0__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_0__CL_MAP_0__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_0__TYPE                                                u_int32_t
#define CL_MAP_0__READ                                              0xffffffffU
#define CL_MAP_0__WRITE                                             0xffffffffU

#endif /* __CL_MAP_0_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_0_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_0_B2__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_1 */
#ifndef __CL_MAP_1_MACRO__
#define __CL_MAP_1_MACRO__

/* macros for field cl_map_1 */
#define CL_MAP_1__CL_MAP_1__SHIFT                                             0
#define CL_MAP_1__CL_MAP_1__WIDTH                                            32
#define CL_MAP_1__CL_MAP_1__MASK                                    0xffffffffU
#define CL_MAP_1__CL_MAP_1__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_1__CL_MAP_1__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_1__CL_MAP_1__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_1__TYPE                                                u_int32_t
#define CL_MAP_1__READ                                              0xffffffffU
#define CL_MAP_1__WRITE                                             0xffffffffU

#endif /* __CL_MAP_1_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_1_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_1_B2__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_2 */
#ifndef __CL_MAP_2_MACRO__
#define __CL_MAP_2_MACRO__

/* macros for field cl_map_2 */
#define CL_MAP_2__CL_MAP_2__SHIFT                                             0
#define CL_MAP_2__CL_MAP_2__WIDTH                                            32
#define CL_MAP_2__CL_MAP_2__MASK                                    0xffffffffU
#define CL_MAP_2__CL_MAP_2__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_2__CL_MAP_2__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_2__CL_MAP_2__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_2__TYPE                                                u_int32_t
#define CL_MAP_2__READ                                              0xffffffffU
#define CL_MAP_2__WRITE                                             0xffffffffU

#endif /* __CL_MAP_2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_2_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_2_B2__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_3 */
#ifndef __CL_MAP_3_MACRO__
#define __CL_MAP_3_MACRO__

/* macros for field cl_map_3 */
#define CL_MAP_3__CL_MAP_3__SHIFT                                             0
#define CL_MAP_3__CL_MAP_3__WIDTH                                            32
#define CL_MAP_3__CL_MAP_3__MASK                                    0xffffffffU
#define CL_MAP_3__CL_MAP_3__READ(src)            (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_3__CL_MAP_3__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_3__CL_MAP_3__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CL_MAP_3__TYPE                                                u_int32_t
#define CL_MAP_3__READ                                              0xffffffffU
#define CL_MAP_3__WRITE                                             0xffffffffU

#endif /* __CL_MAP_3_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_3_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_3_B2__NUM                  1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */
#ifndef __CL_MAP_PAL_0_MACRO__
#define __CL_MAP_PAL_0_MACRO__

/* macros for field cl_map_0 */
#define CL_MAP_PAL_0__CL_MAP_0__SHIFT                                         0
#define CL_MAP_PAL_0__CL_MAP_0__WIDTH                                        32
#define CL_MAP_PAL_0__CL_MAP_0__MASK                                0xffffffffU
#define CL_MAP_PAL_0__CL_MAP_0__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_0__TYPE                                            u_int32_t
#define CL_MAP_PAL_0__READ                                          0xffffffffU
#define CL_MAP_PAL_0__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_0_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_0_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_0_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */
#ifndef __CL_MAP_PAL_1_MACRO__
#define __CL_MAP_PAL_1_MACRO__

/* macros for field cl_map_1 */
#define CL_MAP_PAL_1__CL_MAP_1__SHIFT                                         0
#define CL_MAP_PAL_1__CL_MAP_1__WIDTH                                        32
#define CL_MAP_PAL_1__CL_MAP_1__MASK                                0xffffffffU
#define CL_MAP_PAL_1__CL_MAP_1__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_1__TYPE                                            u_int32_t
#define CL_MAP_PAL_1__READ                                          0xffffffffU
#define CL_MAP_PAL_1__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_1_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_1_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_1_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */
#ifndef __CL_MAP_PAL_2_MACRO__
#define __CL_MAP_PAL_2_MACRO__

/* macros for field cl_map_2 */
#define CL_MAP_PAL_2__CL_MAP_2__SHIFT                                         0
#define CL_MAP_PAL_2__CL_MAP_2__WIDTH                                        32
#define CL_MAP_PAL_2__CL_MAP_2__MASK                                0xffffffffU
#define CL_MAP_PAL_2__CL_MAP_2__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_2__TYPE                                            u_int32_t
#define CL_MAP_PAL_2__READ                                          0xffffffffU
#define CL_MAP_PAL_2__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_2_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_2_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */
#ifndef __CL_MAP_PAL_3_MACRO__
#define __CL_MAP_PAL_3_MACRO__

/* macros for field cl_map_3 */
#define CL_MAP_PAL_3__CL_MAP_3__SHIFT                                         0
#define CL_MAP_PAL_3__CL_MAP_3__WIDTH                                        32
#define CL_MAP_PAL_3__CL_MAP_3__MASK                                0xffffffffU
#define CL_MAP_PAL_3__CL_MAP_3__READ(src)        (u_int32_t)(src) & 0xffffffffU
#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CL_MAP_PAL_3__TYPE                                            u_int32_t
#define CL_MAP_PAL_3__READ                                          0xffffffffU
#define CL_MAP_PAL_3__WRITE                                         0xffffffffU

#endif /* __CL_MAP_PAL_3_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_3_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_3_B2__NUM              1

/* macros for BlueprintGlobalNameSpace::cl_tab */
#ifndef __CL_TAB_MACRO__
#define __CL_TAB_MACRO__

/* macros for field cl_gain_mod */
#define CL_TAB__CL_GAIN_MOD__SHIFT                                            0
#define CL_TAB__CL_GAIN_MOD__WIDTH                                            5
#define CL_TAB__CL_GAIN_MOD__MASK                                   0x0000001fU
#define CL_TAB__CL_GAIN_MOD__READ(src)           (u_int32_t)(src) & 0x0000001fU
#define CL_TAB__CL_GAIN_MOD__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))

/* macros for field carr_lk_dc_add_Q */
#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT                                       5
#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH                                      11
#define CL_TAB__CARR_LK_DC_ADD_Q__MASK                              0x0000ffe0U
#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ffe0U) >> 5)
#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x0000ffe0U)
#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffe0U) | (((u_int32_t)(src) <<\
                    5) & 0x0000ffe0U)
#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x0000ffe0U)))

/* macros for field carr_lk_dc_add_I */
#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT                                      16
#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH                                      11
#define CL_TAB__CARR_LK_DC_ADD_I__MASK                              0x07ff0000U
#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x07ff0000U)
#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x07ff0000U)
#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x07ff0000U)))

/* macros for field bb_gain */
#define CL_TAB__BB_GAIN__SHIFT                                               27
#define CL_TAB__BB_GAIN__WIDTH                                                4
#define CL_TAB__BB_GAIN__MASK                                       0x78000000U
#define CL_TAB__BB_GAIN__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
#define CL_TAB__BB_GAIN__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
#define CL_TAB__BB_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define CL_TAB__BB_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))
#define CL_TAB__TYPE                                                  u_int32_t
#define CL_TAB__READ                                                0x7fffffffU
#define CL_TAB__WRITE                                               0x7fffffffU

#endif /* __CL_TAB_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_tab_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_TAB_B2__NUM                   16

/* macros for BlueprintGlobalNameSpace::chan_info_gain_b2 */
#ifndef __CHAN_INFO_GAIN_B2_MACRO__
#define __CHAN_INFO_GAIN_B2_MACRO__

/* macros for field chan_info_rssi_2 */
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__SHIFT                            0
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__WIDTH                            8
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__MASK                   0x000000ffU
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000000ffU

/* macros for field chan_info_rf_gain_2 */
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__SHIFT                         8
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__WIDTH                         8
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__MASK                0x0000ff00U
#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field chan_info_mb_gain_2 */
#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__SHIFT                        16
#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__WIDTH                         7
#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__MASK                0x007f0000U
#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)

/* macros for field chan_info_xatten1_sw_2 */
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SHIFT                     23
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__WIDTH                      1
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__MASK             0x00800000U
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field chan_info_xatten2_sw_2 */
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SHIFT                     24
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__WIDTH                      1
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__MASK             0x01000000U
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define CHAN_INFO_GAIN_B2__TYPE                                       u_int32_t
#define CHAN_INFO_GAIN_B2__READ                                     0x01ffffffU

#endif /* __CHAN_INFO_GAIN_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_chan_info_gain_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CHAN_INFO_GAIN_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::tpc_4_b2 */
#ifndef __TPC_4_B2_MACRO__
#define __TPC_4_B2_MACRO__

/* macros for field pd_avg_valid_2 */
#define TPC_4_B2__PD_AVG_VALID_2__SHIFT                                       0
#define TPC_4_B2__PD_AVG_VALID_2__WIDTH                                       1
#define TPC_4_B2__PD_AVG_VALID_2__MASK                              0x00000001U
#define TPC_4_B2__PD_AVG_VALID_2__READ(src)      (u_int32_t)(src) & 0x00000001U
#define TPC_4_B2__PD_AVG_VALID_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TPC_4_B2__PD_AVG_VALID_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field pd_avg_out_2 */
#define TPC_4_B2__PD_AVG_OUT_2__SHIFT                                         1
#define TPC_4_B2__PD_AVG_OUT_2__WIDTH                                         8
#define TPC_4_B2__PD_AVG_OUT_2__MASK                                0x000001feU
#define TPC_4_B2__PD_AVG_OUT_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)

/* macros for field dac_gain_2 */
#define TPC_4_B2__DAC_GAIN_2__SHIFT                                           9
#define TPC_4_B2__DAC_GAIN_2__WIDTH                                           5
#define TPC_4_B2__DAC_GAIN_2__MASK                                  0x00003e00U
#define TPC_4_B2__DAC_GAIN_2__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)

/* macros for field tx_gain_setting_2 */
#define TPC_4_B2__TX_GAIN_SETTING_2__SHIFT                                   14
#define TPC_4_B2__TX_GAIN_SETTING_2__WIDTH                                    6
#define TPC_4_B2__TX_GAIN_SETTING_2__MASK                           0x000fc000U
#define TPC_4_B2__TX_GAIN_SETTING_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000fc000U) >> 14)

/* macros for field rate_sent_2 */
#define TPC_4_B2__RATE_SENT_2__SHIFT                                         20
#define TPC_4_B2__RATE_SENT_2__WIDTH                                          5
#define TPC_4_B2__RATE_SENT_2__MASK                                 0x01f00000U
#define TPC_4_B2__RATE_SENT_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f00000U) >> 20)
#define TPC_4_B2__TYPE                                                u_int32_t
#define TPC_4_B2__READ                                              0x01ffffffU

#endif /* __TPC_4_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_4_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_4_B2__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_5_b2 */
#ifndef __TPC_5_B2_MACRO__
#define __TPC_5_B2_MACRO__

/* macros for field pd_gain_boundary_1_2 */
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__SHIFT                                 4
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WIDTH                                 6
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MASK                        0x000003f0U
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000003f0U) >> 4)
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000003f0U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000003f0U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000003f0U)))

/* macros for field pd_gain_boundary_2_2 */
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__SHIFT                                10
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WIDTH                                 6
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MASK                        0x0000fc00U
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000fc00U) >> 10)
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x0000fc00U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
                    10) & 0x0000fc00U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x0000fc00U)))

/* macros for field pd_gain_boundary_3_2 */
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__SHIFT                                16
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WIDTH                                 6
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MASK                        0x003f0000U
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003f0000U) >> 16)
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x003f0000U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x003f0000U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x003f0000U)))

/* macros for field pd_gain_boundary_4_2 */
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__SHIFT                                22
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WIDTH                                 6
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MASK                        0x0fc00000U
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fc00000U) >> 22)
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x0fc00000U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x0fc00000U)
#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x0fc00000U)))
#define TPC_5_B2__TYPE                                                u_int32_t
#define TPC_5_B2__READ                                              0x0ffffff0U
#define TPC_5_B2__WRITE                                             0x0ffffff0U

#endif /* __TPC_5_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_5_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_5_B2__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_6_b2 */
#ifndef __TPC_6_B2_MACRO__
#define __TPC_6_B2_MACRO__

/* macros for field pd_dac_setting_1_2 */
#define TPC_6_B2__PD_DAC_SETTING_1_2__SHIFT                                   0
#define TPC_6_B2__PD_DAC_SETTING_1_2__WIDTH                                   6
#define TPC_6_B2__PD_DAC_SETTING_1_2__MASK                          0x0000003fU
#define TPC_6_B2__PD_DAC_SETTING_1_2__READ(src)  (u_int32_t)(src) & 0x0000003fU
#define TPC_6_B2__PD_DAC_SETTING_1_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000003fU)
#define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define TPC_6_B2__PD_DAC_SETTING_1_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field pd_dac_setting_2_2 */
#define TPC_6_B2__PD_DAC_SETTING_2_2__SHIFT                                   6
#define TPC_6_B2__PD_DAC_SETTING_2_2__WIDTH                                   6
#define TPC_6_B2__PD_DAC_SETTING_2_2__MASK                          0x00000fc0U
#define TPC_6_B2__PD_DAC_SETTING_2_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)
#define TPC_6_B2__PD_DAC_SETTING_2_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define TPC_6_B2__PD_DAC_SETTING_2_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field pd_dac_setting_3_2 */
#define TPC_6_B2__PD_DAC_SETTING_3_2__SHIFT                                  12
#define TPC_6_B2__PD_DAC_SETTING_3_2__WIDTH                                   6
#define TPC_6_B2__PD_DAC_SETTING_3_2__MASK                          0x0003f000U
#define TPC_6_B2__PD_DAC_SETTING_3_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define TPC_6_B2__PD_DAC_SETTING_3_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define TPC_6_B2__PD_DAC_SETTING_3_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field pd_dac_setting_4_2 */
#define TPC_6_B2__PD_DAC_SETTING_4_2__SHIFT                                  18
#define TPC_6_B2__PD_DAC_SETTING_4_2__WIDTH                                   6
#define TPC_6_B2__PD_DAC_SETTING_4_2__MASK                          0x00fc0000U
#define TPC_6_B2__PD_DAC_SETTING_4_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define TPC_6_B2__PD_DAC_SETTING_4_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00fc0000U)
#define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define TPC_6_B2__PD_DAC_SETTING_4_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field error_est_mode */
#define TPC_6_B2__ERROR_EST_MODE__SHIFT                                      24
#define TPC_6_B2__ERROR_EST_MODE__WIDTH                                       2
#define TPC_6_B2__ERROR_EST_MODE__MASK                              0x03000000U
#define TPC_6_B2__ERROR_EST_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03000000U) >> 24)
#define TPC_6_B2__ERROR_EST_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x03000000U)
#define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define TPC_6_B2__ERROR_EST_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field error_est_filter_coeff */
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__SHIFT                              26
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WIDTH                               3
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MASK                      0x1c000000U
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define TPC_6_B2__ERROR_EST_FILTER_COEFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))
#define TPC_6_B2__TYPE                                                u_int32_t
#define TPC_6_B2__READ                                              0x1fffffffU
#define TPC_6_B2__WRITE                                             0x1fffffffU

#endif /* __TPC_6_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_6_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_6_B2__NUM                     1

/* macros for BlueprintGlobalNameSpace::tpc_11_b2 */
#ifndef __TPC_11_B2_MACRO__
#define __TPC_11_B2_MACRO__

/* macros for field olpc_gain_delta_2 */
#define TPC_11_B2__OLPC_GAIN_DELTA_2__SHIFT                                  16
#define TPC_11_B2__OLPC_GAIN_DELTA_2__WIDTH                                   8
#define TPC_11_B2__OLPC_GAIN_DELTA_2__MASK                          0x00ff0000U
#define TPC_11_B2__OLPC_GAIN_DELTA_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TPC_11_B2__OLPC_GAIN_DELTA_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TPC_11_B2__OLPC_GAIN_DELTA_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field olpc_gain_delta_2_pal_on */
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__SHIFT                           24
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WIDTH                            8
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MASK                   0xff000000U
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xff000000U) >> 24)
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0xff000000U)
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define TPC_11_B2__TYPE                                               u_int32_t
#define TPC_11_B2__READ                                             0xffff0000U
#define TPC_11_B2__WRITE                                            0xffff0000U

#endif /* __TPC_11_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_11_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_11_B2__NUM                    1

/* macros for BlueprintGlobalNameSpace::tpc_19_b2 */
#ifndef __TPC_19_B2_MACRO__
#define __TPC_19_B2_MACRO__

/* macros for field alpha_therm_2 */
#define TPC_19_B2__ALPHA_THERM_2__SHIFT                                       0
#define TPC_19_B2__ALPHA_THERM_2__WIDTH                                       8
#define TPC_19_B2__ALPHA_THERM_2__MASK                              0x000000ffU
#define TPC_19_B2__ALPHA_THERM_2__READ(src)      (u_int32_t)(src) & 0x000000ffU
#define TPC_19_B2__ALPHA_THERM_2__WRITE(src)   ((u_int32_t)(src) & 0x000000ffU)
#define TPC_19_B2__ALPHA_THERM_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TPC_19_B2__ALPHA_THERM_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field alpha_therm_pal_on_2 */
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__SHIFT                                8
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WIDTH                                8
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MASK                       0x0000ff00U
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field alpha_volt_2 */
#define TPC_19_B2__ALPHA_VOLT_2__SHIFT                                       16
#define TPC_19_B2__ALPHA_VOLT_2__WIDTH                                        7
#define TPC_19_B2__ALPHA_VOLT_2__MASK                               0x007f0000U
#define TPC_19_B2__ALPHA_VOLT_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x007f0000U) >> 16)
#define TPC_19_B2__ALPHA_VOLT_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x007f0000U)
#define TPC_19_B2__ALPHA_VOLT_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x007f0000U)
#define TPC_19_B2__ALPHA_VOLT_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x007f0000U)))

/* macros for field alpha_volt_pal_on_2 */
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__SHIFT                                23
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WIDTH                                 7
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MASK                        0x3f800000U
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f800000U) >> 23)
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x3f800000U)
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))
#define TPC_19_B2__TYPE                                               u_int32_t
#define TPC_19_B2__READ                                             0x3fffffffU
#define TPC_19_B2__WRITE                                            0x3fffffffU

#endif /* __TPC_19_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_19_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_19_B2__NUM                    1

/* macros for BlueprintGlobalNameSpace::pdadc_tab */
#ifndef __PDADC_TAB_MACRO__
#define __PDADC_TAB_MACRO__

/* macros for field tab_entry */
#define PDADC_TAB__TAB_ENTRY__SHIFT                                           0
#define PDADC_TAB__TAB_ENTRY__WIDTH                                          32
#define PDADC_TAB__TAB_ENTRY__MASK                                  0xffffffffU
#define PDADC_TAB__TAB_ENTRY__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define PDADC_TAB__TYPE                                               u_int32_t
#define PDADC_TAB__WRITE                                            0x00000000U

#endif /* __PDADC_TAB_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_pdadc_tab_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_PDADC_TAB_B2__NUM                32

/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b2 */
#ifndef __RTT_TABLE_SW_INTF_B2_MACRO__
#define __RTT_TABLE_SW_INTF_B2_MACRO__

/* macros for field sw_rtt_table_access_2 */
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__SHIFT                    0
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WIDTH                    1
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MASK           0x00000001U
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field sw_rtt_table_write_2 */
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__SHIFT                     1
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WIDTH                     1
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MASK            0x00000002U
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field sw_rtt_table_addr_2 */
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__SHIFT                      2
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WIDTH                      3
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MASK             0x0000001cU
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))
#define RTT_TABLE_SW_INTF_B2__TYPE                                    u_int32_t
#define RTT_TABLE_SW_INTF_B2__READ                                  0x0000001fU
#define RTT_TABLE_SW_INTF_B2__WRITE                                 0x0000001fU

#endif /* __RTT_TABLE_SW_INTF_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_rtt_table_sw_intf_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_RTT_TABLE_SW_INTF_B2__NUM         1

/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b2 */
#ifndef __RTT_TABLE_SW_INTF_1_B2_MACRO__
#define __RTT_TABLE_SW_INTF_1_B2_MACRO__

/* macros for field sw_rtt_table_data_2 */
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__SHIFT                    4
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WIDTH                   28
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MASK           0xfffffff0U
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xfffffff0U) >> 4)
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0xfffffff0U)
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffff0U) | (((u_int32_t)(src) <<\
                    4) & 0xfffffff0U)
#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0xfffffff0U)))
#define RTT_TABLE_SW_INTF_1_B2__TYPE                                  u_int32_t
#define RTT_TABLE_SW_INTF_1_B2__READ                                0xfffffff0U
#define RTT_TABLE_SW_INTF_1_B2__WRITE                               0xfffffff0U

#endif /* __RTT_TABLE_SW_INTF_1_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_rtt_table_sw_intf_1_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B2__NUM       1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b2 */
#ifndef __TXIQ_CORR_COEFF_01_B2_MACRO__
#define __TXIQ_CORR_COEFF_01_B2_MACRO__

/* macros for field iqc_coeff_table_0_2 */
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__SHIFT                     0
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WIDTH                    14
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_1_2 */
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__SHIFT                    14
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WIDTH                    14
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_01_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_01_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_01_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_01_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_01_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_01_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b2 */
#ifndef __TXIQ_CORR_COEFF_23_B2_MACRO__
#define __TXIQ_CORR_COEFF_23_B2_MACRO__

/* macros for field iqc_coeff_table_2_2 */
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__SHIFT                     0
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WIDTH                    14
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_3_2 */
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__SHIFT                    14
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WIDTH                    14
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_23_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_23_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_23_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_23_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_23_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_23_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b2 */
#ifndef __TXIQ_CORR_COEFF_45_B2_MACRO__
#define __TXIQ_CORR_COEFF_45_B2_MACRO__

/* macros for field iqc_coeff_table_4_2 */
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__SHIFT                     0
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WIDTH                    14
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_5_2 */
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__SHIFT                    14
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WIDTH                    14
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_45_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_45_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_45_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_45_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_45_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_45_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b2 */
#ifndef __TXIQ_CORR_COEFF_67_B2_MACRO__
#define __TXIQ_CORR_COEFF_67_B2_MACRO__

/* macros for field iqc_coeff_table_6_2 */
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__SHIFT                     0
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WIDTH                    14
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_7_2 */
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__SHIFT                    14
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WIDTH                    14
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_67_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_67_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_67_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_67_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_67_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_67_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b2 */
#ifndef __TXIQ_CORR_COEFF_89_B2_MACRO__
#define __TXIQ_CORR_COEFF_89_B2_MACRO__

/* macros for field iqc_coeff_table_8_2 */
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__SHIFT                     0
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WIDTH                    14
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_9_2 */
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__SHIFT                    14
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WIDTH                    14
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_89_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_89_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_89_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_89_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_89_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_89_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b2 */
#ifndef __TXIQ_CORR_COEFF_AB_B2_MACRO__
#define __TXIQ_CORR_COEFF_AB_B2_MACRO__

/* macros for field iqc_coeff_table_a_2 */
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__SHIFT                     0
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WIDTH                    14
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_b_2 */
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__SHIFT                    14
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WIDTH                    14
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_AB_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_AB_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_AB_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_AB_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_ab_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b2 */
#ifndef __TXIQ_CORR_COEFF_CD_B2_MACRO__
#define __TXIQ_CORR_COEFF_CD_B2_MACRO__

/* macros for field iqc_coeff_table_c_2 */
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__SHIFT                     0
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WIDTH                    14
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_d_2 */
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__SHIFT                    14
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WIDTH                    14
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_CD_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_CD_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_CD_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_CD_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_cd_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b2 */
#ifndef __TXIQ_CORR_COEFF_EF_B2_MACRO__
#define __TXIQ_CORR_COEFF_EF_B2_MACRO__

/* macros for field iqc_coeff_table_e_2 */
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__SHIFT                     0
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WIDTH                    14
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MASK            0x00003fffU
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00003fffU
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00003fffU)
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field iqc_coeff_table_f_2 */
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__SHIFT                    14
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WIDTH                    14
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MASK            0x0fffc000U
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0fffc000U) >> 14)
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
                    14) & 0x0fffc000U)
#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0fffc000U)))
#define TXIQ_CORR_COEFF_EF_B2__TYPE                                   u_int32_t
#define TXIQ_CORR_COEFF_EF_B2__READ                                 0x0fffffffU
#define TXIQ_CORR_COEFF_EF_B2__WRITE                                0x0fffffffU

#endif /* __TXIQ_CORR_COEFF_EF_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_ef_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B2__NUM        1

/* macros for BlueprintGlobalNameSpace::txiqcal_status_b2 */
#ifndef __TXIQCAL_STATUS_B2_MACRO__
#define __TXIQCAL_STATUS_B2_MACRO__

/* macros for field txiqcal_failed_2 */
#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SHIFT                            0
#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__WIDTH                            1
#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__MASK                   0x00000001U
#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field calibrated_gains_2 */
#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__SHIFT                          1
#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__WIDTH                          5
#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__MASK                 0x0000003eU
#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000003eU) >> 1)

/* macros for field tone_gain_used_2 */
#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__SHIFT                            6
#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__WIDTH                            6
#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__MASK                   0x00000fc0U
#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000fc0U) >> 6)

/* macros for field rx_gain_used_2 */
#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__SHIFT                             12
#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__WIDTH                              6
#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__MASK                     0x0003f000U
#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)

/* macros for field last_meas_addr_2 */
#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__SHIFT                           18
#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__WIDTH                            6
#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__MASK                   0x00fc0000U
#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fc0000U) >> 18)
#define TXIQCAL_STATUS_B2__TYPE                                       u_int32_t
#define TXIQCAL_STATUS_B2__READ                                     0x00ffffffU

#endif /* __TXIQCAL_STATUS_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiqcal_status_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQCAL_STATUS_B2__NUM            1

/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b2 */
#ifndef __TABLES_INTF_ADDR_B2_MACRO__
#define __TABLES_INTF_ADDR_B2_MACRO__

/* macros for field tables_addr_2 */
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__SHIFT                             2
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WIDTH                            16
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MASK                    0x0003fffcU
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field addr_auto_incr_2 */
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__SHIFT                         31
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WIDTH                          1
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MASK                 0x80000000U
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TABLES_INTF_ADDR_B2__TYPE                                     u_int32_t
#define TABLES_INTF_ADDR_B2__READ                                   0x8003fffcU
#define TABLES_INTF_ADDR_B2__WRITE                                  0x8003fffcU

#endif /* __TABLES_INTF_ADDR_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tables_intf_addr_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TABLES_INTF_ADDR_B2__NUM          1

/* macros for BlueprintGlobalNameSpace::tables_intf_data_b2 */
#ifndef __TABLES_INTF_DATA_B2_MACRO__
#define __TABLES_INTF_DATA_B2_MACRO__

/* macros for field tables_data_2 */
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__SHIFT                             0
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__WIDTH                            32
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__MASK                    0xffffffffU
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define TABLES_INTF_DATA_B2__TABLES_DATA_2__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define TABLES_INTF_DATA_B2__TYPE                                     u_int32_t
#define TABLES_INTF_DATA_B2__READ                                   0xffffffffU
#define TABLES_INTF_DATA_B2__WRITE                                  0xffffffffU

#endif /* __TABLES_INTF_DATA_B2_MACRO__ */


/* macros for bb_reg_map.bb_sm2_reg_map.BB_tables_intf_data_b2 */
#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TABLES_INTF_DATA_B2__NUM          1

/* macros for BlueprintGlobalNameSpace::dummy */
#ifndef __DUMMY_MACRO__
#define __DUMMY_MACRO__

/* macros for field dummy */
#define DUMMY__DUMMY__SHIFT                                                   0
#define DUMMY__DUMMY__WIDTH                                                   1
#define DUMMY__DUMMY__MASK                                          0x00000001U
#define DUMMY__DUMMY__READ(src)                  (u_int32_t)(src) & 0x00000001U
#define DUMMY__DUMMY__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
#define DUMMY__DUMMY__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
#define DUMMY__TYPE                                                   u_int32_t
#define DUMMY__READ                                                 0x00000001U

#endif /* __DUMMY_MACRO__ */


/* macros for bb_reg_map.bb_chn3_reg_map.BB_dummy1 */
#define INST_BB_REG_MAP__BB_CHN3_REG_MAP__BB_DUMMY1__NUM                    256

/* macros for BlueprintGlobalNameSpace::dummy */
#ifndef __DUMMY_MACRO__
#define __DUMMY_MACRO__

/* macros for field dummy */
#define DUMMY__DUMMY__SHIFT                                                   0
#define DUMMY__DUMMY__WIDTH                                                   1
#define DUMMY__DUMMY__MASK                                          0x00000001U
#define DUMMY__DUMMY__READ(src)                  (u_int32_t)(src) & 0x00000001U
#define DUMMY__DUMMY__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
#define DUMMY__DUMMY__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
#define DUMMY__TYPE                                                   u_int32_t
#define DUMMY__READ                                                 0x00000001U

#endif /* __DUMMY_MACRO__ */


/* macros for bb_reg_map.bb_agc3_reg_map.BB_dummy */
#define INST_BB_REG_MAP__BB_AGC3_REG_MAP__BB_DUMMY__NUM                       1

/* macros for BlueprintGlobalNameSpace::rssi_b3 */
#ifndef __RSSI_B3_MACRO__
#define __RSSI_B3_MACRO__

/* macros for field rssi_3 */
#define RSSI_B3__RSSI_3__SHIFT                                                0
#define RSSI_B3__RSSI_3__WIDTH                                                8
#define RSSI_B3__RSSI_3__MASK                                       0x000000ffU
#define RSSI_B3__RSSI_3__READ(src)               (u_int32_t)(src) & 0x000000ffU

/* macros for field rssi_ext_3 */
#define RSSI_B3__RSSI_EXT_3__SHIFT                                            8
#define RSSI_B3__RSSI_EXT_3__WIDTH                                            8
#define RSSI_B3__RSSI_EXT_3__MASK                                   0x0000ff00U
#define RSSI_B3__RSSI_EXT_3__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define RSSI_B3__TYPE                                                 u_int32_t
#define RSSI_B3__READ                                               0x0000ffffU

#endif /* __RSSI_B3_MACRO__ */


/* macros for bb_reg_map.bb_agc3_reg_map.BB_rssi_b3 */
#define INST_BB_REG_MAP__BB_AGC3_REG_MAP__BB_RSSI_B3__NUM                     1

/* macros for BlueprintGlobalNameSpace::dummy */
#ifndef __DUMMY_MACRO__
#define __DUMMY_MACRO__

/* macros for field dummy */
#define DUMMY__DUMMY__SHIFT                                                   0
#define DUMMY__DUMMY__WIDTH                                                   1
#define DUMMY__DUMMY__MASK                                          0x00000001U
#define DUMMY__DUMMY__READ(src)                  (u_int32_t)(src) & 0x00000001U
#define DUMMY__DUMMY__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
#define DUMMY__DUMMY__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
#define DUMMY__TYPE                                                   u_int32_t
#define DUMMY__READ                                                 0x00000001U

#endif /* __DUMMY_MACRO__ */


/* macros for bb_reg_map.bb_sm3_reg_map.BB_dummy2 */
#define INST_BB_REG_MAP__BB_SM3_REG_MAP__BB_DUMMY2__NUM                     384
#define RFILE_INST_BB_REG_MAP__BB_CHN_REG_MAP__NUM                            1
#define RFILE_INST_BB_REG_MAP__BB_MRC_REG_MAP__NUM                            1
#define RFILE_INST_BB_REG_MAP__BB_BBB_REG_MAP__NUM                            1
#define RFILE_INST_BB_REG_MAP__BB_AGC_REG_MAP__NUM                            1
#define RFILE_INST_BB_REG_MAP__BB_SM_REG_MAP__NUM                             1
#define RFILE_INST_BB_REG_MAP__BB_CHN1_REG_MAP__NUM                           1
#define RFILE_INST_BB_REG_MAP__BB_AGC1_REG_MAP__NUM                           1
#define RFILE_INST_BB_REG_MAP__BB_SM1_REG_MAP__NUM                            1
#define RFILE_INST_BB_REG_MAP__BB_CHN2_REG_MAP__NUM                           1
#define RFILE_INST_BB_REG_MAP__BB_AGC2_REG_MAP__NUM                           1
#define RFILE_INST_BB_REG_MAP__BB_SM2_REG_MAP__NUM                            1
#define RFILE_INST_BB_REG_MAP__BB_CHN3_REG_MAP__NUM                           1
#define RFILE_INST_BB_REG_MAP__BB_AGC3_REG_MAP__NUM                           1
#define RFILE_INST_BB_REG_MAP__BB_SM3_REG_MAP__NUM                            1

/* macros for BlueprintGlobalNameSpace::MAC_PCU_BUF */
#ifndef __MAC_PCU_BUF_MACRO__
#define __MAC_PCU_BUF_MACRO__

/* macros for field DATA */
#define MAC_PCU_BUF__DATA__SHIFT                                              0
#define MAC_PCU_BUF__DATA__WIDTH                                             32
#define MAC_PCU_BUF__DATA__MASK                                     0xffffffffU
#define MAC_PCU_BUF__DATA__READ(src)             (u_int32_t)(src) & 0xffffffffU
#define MAC_PCU_BUF__DATA__WRITE(src)          ((u_int32_t)(src) & 0xffffffffU)
#define MAC_PCU_BUF__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define MAC_PCU_BUF__DATA__VERIFY(src)   (!(((u_int32_t)(src) & ~0xffffffffU)))
#define MAC_PCU_BUF__TYPE                                             u_int32_t
#define MAC_PCU_BUF__READ                                           0xffffffffU
#define MAC_PCU_BUF__WRITE                                          0xffffffffU

#endif /* __MAC_PCU_BUF_MACRO__ */


/* macros for mac_pcu_buf_reg_map.MAC_PCU_BUF */
#define INST_MAC_PCU_BUF_REG_MAP__MAC_PCU_BUF__NUM                         2048

/* macros for BlueprintGlobalNameSpace::TXBF_DBG */
#ifndef __TXBF_DBG_MACRO__
#define __TXBF_DBG_MACRO__

/* macros for field MODE */
#define TXBF_DBG__MODE__SHIFT                                                 0
#define TXBF_DBG__MODE__WIDTH                                                 2
#define TXBF_DBG__MODE__MASK                                        0x00000003U
#define TXBF_DBG__MODE__READ(src)                (u_int32_t)(src) & 0x00000003U
#define TXBF_DBG__MODE__WRITE(src)             ((u_int32_t)(src) & 0x00000003U)
#define TXBF_DBG__MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define TXBF_DBG__MODE__VERIFY(src)      (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field CLIENT_TABLE */
#define TXBF_DBG__CLIENT_TABLE__SHIFT                                         2
#define TXBF_DBG__CLIENT_TABLE__WIDTH                                        16
#define TXBF_DBG__CLIENT_TABLE__MASK                                0x0003fffcU
#define TXBF_DBG__CLIENT_TABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003fffcU) >> 2)
#define TXBF_DBG__CLIENT_TABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0003fffcU)
#define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0003fffcU)
#define TXBF_DBG__CLIENT_TABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0003fffcU)))

/* macros for field SW_WR_V_DONE */
#define TXBF_DBG__SW_WR_V_DONE__SHIFT                                        18
#define TXBF_DBG__SW_WR_V_DONE__WIDTH                                         1
#define TXBF_DBG__SW_WR_V_DONE__MASK                                0x00040000U
#define TXBF_DBG__SW_WR_V_DONE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define TXBF_DBG__SW_WR_V_DONE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define TXBF_DBG__SW_WR_V_DONE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define TXBF_DBG__SW_WR_V_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define TXBF_DBG__SW_WR_V_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field DBG_IM */
#define TXBF_DBG__DBG_IM__SHIFT                                              19
#define TXBF_DBG__DBG_IM__WIDTH                                               1
#define TXBF_DBG__DBG_IM__MASK                                      0x00080000U
#define TXBF_DBG__DBG_IM__READ(src)    (((u_int32_t)(src) & 0x00080000U) >> 19)
#define TXBF_DBG__DBG_IM__WRITE(src)   (((u_int32_t)(src) << 19) & 0x00080000U)
#define TXBF_DBG__DBG_IM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define TXBF_DBG__DBG_IM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define TXBF_DBG__DBG_IM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define TXBF_DBG__DBG_IM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field DBG_BW */
#define TXBF_DBG__DBG_BW__SHIFT                                              20
#define TXBF_DBG__DBG_BW__WIDTH                                               1
#define TXBF_DBG__DBG_BW__MASK                                      0x00100000U
#define TXBF_DBG__DBG_BW__READ(src)    (((u_int32_t)(src) & 0x00100000U) >> 20)
#define TXBF_DBG__DBG_BW__WRITE(src)   (((u_int32_t)(src) << 20) & 0x00100000U)
#define TXBF_DBG__DBG_BW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define TXBF_DBG__DBG_BW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define TXBF_DBG__DBG_BW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define TXBF_DBG__DBG_BW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field CLK_CNTL */
#define TXBF_DBG__CLK_CNTL__SHIFT                                            21
#define TXBF_DBG__CLK_CNTL__WIDTH                                             1
#define TXBF_DBG__CLK_CNTL__MASK                                    0x00200000U
#define TXBF_DBG__CLK_CNTL__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U)
#define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define TXBF_DBG__CLK_CNTL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define TXBF_DBG__CLK_CNTL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define TXBF_DBG__CLK_CNTL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field REGULAR_SOUNDING */
#define TXBF_DBG__REGULAR_SOUNDING__SHIFT                                    22
#define TXBF_DBG__REGULAR_SOUNDING__WIDTH                                     1
#define TXBF_DBG__REGULAR_SOUNDING__MASK                            0x00400000U
#define TXBF_DBG__REGULAR_SOUNDING__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define TXBF_DBG__REGULAR_SOUNDING__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define TXBF_DBG__REGULAR_SOUNDING__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define TXBF_DBG__REGULAR_SOUNDING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define TXBF_DBG__REGULAR_SOUNDING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field DBG_NO_WALSH */
#define TXBF_DBG__DBG_NO_WALSH__SHIFT                                        23
#define TXBF_DBG__DBG_NO_WALSH__WIDTH                                         1
#define TXBF_DBG__DBG_NO_WALSH__MASK                                0x00800000U
#define TXBF_DBG__DBG_NO_WALSH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define TXBF_DBG__DBG_NO_WALSH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TXBF_DBG__DBG_NO_WALSH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TXBF_DBG__DBG_NO_WALSH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TXBF_DBG__DBG_NO_WALSH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field DBG_NO_CSD */
#define TXBF_DBG__DBG_NO_CSD__SHIFT                                          24
#define TXBF_DBG__DBG_NO_CSD__WIDTH                                           1
#define TXBF_DBG__DBG_NO_CSD__MASK                                  0x01000000U
#define TXBF_DBG__DBG_NO_CSD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define TXBF_DBG__DBG_NO_CSD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TXBF_DBG__DBG_NO_CSD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TXBF_DBG__DBG_NO_CSD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TXBF_DBG__DBG_NO_CSD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)
#define TXBF_DBG__TYPE                                                u_int32_t
#define TXBF_DBG__READ                                              0x01dfffffU
#define TXBF_DBG__WRITE                                             0x01dfffffU

#endif /* __TXBF_DBG_MACRO__ */


/* macros for svd_reg_map.TXBF_DBG */
#define INST_SVD_REG_MAP__TXBF_DBG__NUM                                       1

/* macros for BlueprintGlobalNameSpace::TXBF */
#ifndef __TXBF_MACRO__
#define __TXBF_MACRO__

/* macros for field CB_TX */
#define TXBF__CB_TX__SHIFT                                                    0
#define TXBF__CB_TX__WIDTH                                                    2
#define TXBF__CB_TX__MASK                                           0x00000003U
#define TXBF__CB_TX__READ(src)                   (u_int32_t)(src) & 0x00000003U
#define TXBF__CB_TX__WRITE(src)                ((u_int32_t)(src) & 0x00000003U)
#define TXBF__CB_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define TXBF__CB_TX__VERIFY(src)         (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field NB_TX */
#define TXBF__NB_TX__SHIFT                                                    2
#define TXBF__NB_TX__WIDTH                                                    2
#define TXBF__NB_TX__MASK                                           0x0000000cU
#define TXBF__NB_TX__READ(src)          (((u_int32_t)(src) & 0x0000000cU) >> 2)
#define TXBF__NB_TX__WRITE(src)         (((u_int32_t)(src) << 2) & 0x0000000cU)
#define TXBF__NB_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define TXBF__NB_TX__VERIFY(src)  (!((((u_int32_t)(src) << 2) & ~0x0000000cU)))

/* macros for field NG_RPT_TX */
#define TXBF__NG_RPT_TX__SHIFT                                                4
#define TXBF__NG_RPT_TX__WIDTH                                                2
#define TXBF__NG_RPT_TX__MASK                                       0x00000030U
#define TXBF__NG_RPT_TX__READ(src)      (((u_int32_t)(src) & 0x00000030U) >> 4)
#define TXBF__NG_RPT_TX__WRITE(src)     (((u_int32_t)(src) << 4) & 0x00000030U)
#define TXBF__NG_RPT_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define TXBF__NG_RPT_TX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field NG_CVCACHE */
#define TXBF__NG_CVCACHE__SHIFT                                               6
#define TXBF__NG_CVCACHE__WIDTH                                               2
#define TXBF__NG_CVCACHE__MASK                                      0x000000c0U
#define TXBF__NG_CVCACHE__READ(src)     (((u_int32_t)(src) & 0x000000c0U) >> 6)
#define TXBF__NG_CVCACHE__WRITE(src)    (((u_int32_t)(src) << 6) & 0x000000c0U)
#define TXBF__NG_CVCACHE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define TXBF__NG_CVCACHE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field TXCV_BFWEIGHT_METHOD */
#define TXBF__TXCV_BFWEIGHT_METHOD__SHIFT                                     9
#define TXBF__TXCV_BFWEIGHT_METHOD__WIDTH                                     2
#define TXBF__TXCV_BFWEIGHT_METHOD__MASK                            0x00000600U
#define TXBF__TXCV_BFWEIGHT_METHOD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000600U) >> 9)
#define TXBF__TXCV_BFWEIGHT_METHOD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000600U)
#define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000600U) | (((u_int32_t)(src) <<\
                    9) & 0x00000600U)
#define TXBF__TXCV_BFWEIGHT_METHOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000600U)))

/* macros for field RLR_EN */
#define TXBF__RLR_EN__SHIFT                                                  11
#define TXBF__RLR_EN__WIDTH                                                   1
#define TXBF__RLR_EN__MASK                                          0x00000800U
#define TXBF__RLR_EN__READ(src)        (((u_int32_t)(src) & 0x00000800U) >> 11)
#define TXBF__RLR_EN__WRITE(src)       (((u_int32_t)(src) << 11) & 0x00000800U)
#define TXBF__RLR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define TXBF__RLR_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define TXBF__RLR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define TXBF__RLR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field RC_20_U_DONE */
#define TXBF__RC_20_U_DONE__SHIFT                                            12
#define TXBF__RC_20_U_DONE__WIDTH                                             1
#define TXBF__RC_20_U_DONE__MASK                                    0x00001000U
#define TXBF__RC_20_U_DONE__READ(src)  (((u_int32_t)(src) & 0x00001000U) >> 12)
#define TXBF__RC_20_U_DONE__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
#define TXBF__RC_20_U_DONE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define TXBF__RC_20_U_DONE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define TXBF__RC_20_U_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define TXBF__RC_20_U_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field RC_20_L_DONE */
#define TXBF__RC_20_L_DONE__SHIFT                                            13
#define TXBF__RC_20_L_DONE__WIDTH                                             1
#define TXBF__RC_20_L_DONE__MASK                                    0x00002000U
#define TXBF__RC_20_L_DONE__READ(src)  (((u_int32_t)(src) & 0x00002000U) >> 13)
#define TXBF__RC_20_L_DONE__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
#define TXBF__RC_20_L_DONE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TXBF__RC_20_L_DONE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TXBF__RC_20_L_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TXBF__RC_20_L_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field RC_40_DONE */
#define TXBF__RC_40_DONE__SHIFT                                              14
#define TXBF__RC_40_DONE__WIDTH                                               1
#define TXBF__RC_40_DONE__MASK                                      0x00004000U
#define TXBF__RC_40_DONE__READ(src)    (((u_int32_t)(src) & 0x00004000U) >> 14)
#define TXBF__RC_40_DONE__WRITE(src)   (((u_int32_t)(src) << 14) & 0x00004000U)
#define TXBF__RC_40_DONE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define TXBF__RC_40_DONE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define TXBF__RC_40_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define TXBF__RC_40_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)
#define TXBF__TYPE                                                    u_int32_t
#define TXBF__READ                                                  0x00007effU
#define TXBF__WRITE                                                 0x00007effU

#endif /* __TXBF_MACRO__ */


/* macros for svd_reg_map.TXBF */
#define INST_SVD_REG_MAP__TXBF__NUM                                           1

/* macros for BlueprintGlobalNameSpace::TXBF_TIMER */
#ifndef __TXBF_TIMER_MACRO__
#define __TXBF_TIMER_MACRO__

/* macros for field TIMEOUT */
#define TXBF_TIMER__TIMEOUT__SHIFT                                            0
#define TXBF_TIMER__TIMEOUT__WIDTH                                            8
#define TXBF_TIMER__TIMEOUT__MASK                                   0x000000ffU
#define TXBF_TIMER__TIMEOUT__READ(src)           (u_int32_t)(src) & 0x000000ffU
#define TXBF_TIMER__TIMEOUT__WRITE(src)        ((u_int32_t)(src) & 0x000000ffU)
#define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define TXBF_TIMER__TIMEOUT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field ATIMEOUT */
#define TXBF_TIMER__ATIMEOUT__SHIFT                                           8
#define TXBF_TIMER__ATIMEOUT__WIDTH                                           8
#define TXBF_TIMER__ATIMEOUT__MASK                                  0x0000ff00U
#define TXBF_TIMER__ATIMEOUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
#define TXBF_TIMER__ATIMEOUT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x0000ff00U)
#define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
                    8) & 0x0000ff00U)
#define TXBF_TIMER__ATIMEOUT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x0000ff00U)))
#define TXBF_TIMER__TYPE                                              u_int32_t
#define TXBF_TIMER__READ                                            0x0000ffffU
#define TXBF_TIMER__WRITE                                           0x0000ffffU

#endif /* __TXBF_TIMER_MACRO__ */


/* macros for svd_reg_map.TXBF_TIMER */
#define INST_SVD_REG_MAP__TXBF_TIMER__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF_SW */
#ifndef __TXBF_SW_MACRO__
#define __TXBF_SW_MACRO__

/* macros for field LRU_ACK */
#define TXBF_SW__LRU_ACK__SHIFT                                               0
#define TXBF_SW__LRU_ACK__WIDTH                                               1
#define TXBF_SW__LRU_ACK__MASK                                      0x00000001U
#define TXBF_SW__LRU_ACK__READ(src)              (u_int32_t)(src) & 0x00000001U
#define TXBF_SW__LRU_ACK__WRITE(src)           ((u_int32_t)(src) & 0x00000001U)
#define TXBF_SW__LRU_ACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TXBF_SW__LRU_ACK__VERIFY(src)    (!(((u_int32_t)(src) & ~0x00000001U)))
#define TXBF_SW__LRU_ACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXBF_SW__LRU_ACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field LRU_ADDR */
#define TXBF_SW__LRU_ADDR__SHIFT                                              1
#define TXBF_SW__LRU_ADDR__WIDTH                                              9
#define TXBF_SW__LRU_ADDR__MASK                                     0x000003feU
#define TXBF_SW__LRU_ADDR__READ(src)    (((u_int32_t)(src) & 0x000003feU) >> 1)

/* macros for field LRU_EN */
#define TXBF_SW__LRU_EN__SHIFT                                               11
#define TXBF_SW__LRU_EN__WIDTH                                                1
#define TXBF_SW__LRU_EN__MASK                                       0x00000800U
#define TXBF_SW__LRU_EN__READ(src)     (((u_int32_t)(src) & 0x00000800U) >> 11)
#define TXBF_SW__LRU_EN__WRITE(src)    (((u_int32_t)(src) << 11) & 0x00000800U)
#define TXBF_SW__LRU_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define TXBF_SW__LRU_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define TXBF_SW__LRU_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define TXBF_SW__LRU_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field DEST_IDX */
#define TXBF_SW__DEST_IDX__SHIFT                                             12
#define TXBF_SW__DEST_IDX__WIDTH                                              7
#define TXBF_SW__DEST_IDX__MASK                                     0x0007f000U
#define TXBF_SW__DEST_IDX__READ(src)   (((u_int32_t)(src) & 0x0007f000U) >> 12)
#define TXBF_SW__DEST_IDX__WRITE(src)  (((u_int32_t)(src) << 12) & 0x0007f000U)
#define TXBF_SW__DEST_IDX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0007f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0007f000U)
#define TXBF_SW__DEST_IDX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0007f000U)))

/* macros for field LRU_WR_ACK */
#define TXBF_SW__LRU_WR_ACK__SHIFT                                           19
#define TXBF_SW__LRU_WR_ACK__WIDTH                                            1
#define TXBF_SW__LRU_WR_ACK__MASK                                   0x00080000U
#define TXBF_SW__LRU_WR_ACK__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
#define TXBF_SW__LRU_WR_ACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00080000U)
#define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define TXBF_SW__LRU_WR_ACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define TXBF_SW__LRU_WR_ACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define TXBF_SW__LRU_WR_ACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field LRU_RD_ACK */
#define TXBF_SW__LRU_RD_ACK__SHIFT                                           20
#define TXBF_SW__LRU_RD_ACK__WIDTH                                            1
#define TXBF_SW__LRU_RD_ACK__MASK                                   0x00100000U
#define TXBF_SW__LRU_RD_ACK__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
#define TXBF_SW__LRU_RD_ACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define TXBF_SW__LRU_RD_ACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define TXBF_SW__LRU_RD_ACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define TXBF_SW__LRU_RD_ACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field WALSH_CSD_MODE */
#define TXBF_SW__WALSH_CSD_MODE__SHIFT                                       21
#define TXBF_SW__WALSH_CSD_MODE__WIDTH                                        1
#define TXBF_SW__WALSH_CSD_MODE__MASK                               0x00200000U
#define TXBF_SW__WALSH_CSD_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define TXBF_SW__WALSH_CSD_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define TXBF_SW__WALSH_CSD_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define TXBF_SW__WALSH_CSD_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define TXBF_SW__WALSH_CSD_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field CONDITION_NUMBER */
#define TXBF_SW__CONDITION_NUMBER__SHIFT                                     22
#define TXBF_SW__CONDITION_NUMBER__WIDTH                                      5
#define TXBF_SW__CONDITION_NUMBER__MASK                             0x07c00000U
#define TXBF_SW__CONDITION_NUMBER__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define TXBF_SW__CONDITION_NUMBER__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define TXBF_SW__CONDITION_NUMBER__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))
#define TXBF_SW__TYPE                                                 u_int32_t
#define TXBF_SW__READ                                               0x07fffbffU
#define TXBF_SW__WRITE                                              0x07fffbffU

#endif /* __TXBF_SW_MACRO__ */


/* macros for svd_reg_map.TXBF_SW */
#define INST_SVD_REG_MAP__TXBF_SW__NUM                                        1

/* macros for BlueprintGlobalNameSpace::TXBF_SM */
#ifndef __TXBF_SM_MACRO__
#define __TXBF_SM_MACRO__

/* macros for field OBS */
#define TXBF_SM__OBS__SHIFT                                                   0
#define TXBF_SM__OBS__WIDTH                                                  32
#define TXBF_SM__OBS__MASK                                          0xffffffffU
#define TXBF_SM__OBS__READ(src)                  (u_int32_t)(src) & 0xffffffffU
#define TXBF_SM__TYPE                                                 u_int32_t
#define TXBF_SM__READ                                               0xffffffffU

#endif /* __TXBF_SM_MACRO__ */


/* macros for svd_reg_map.TXBF_SM */
#define INST_SVD_REG_MAP__TXBF_SM__NUM                                        1

/* macros for BlueprintGlobalNameSpace::TXBF1_CNTL */
#ifndef __TXBF1_CNTL_MACRO__
#define __TXBF1_CNTL_MACRO__

/* macros for field OBS */
#define TXBF1_CNTL__OBS__SHIFT                                                0
#define TXBF1_CNTL__OBS__WIDTH                                               32
#define TXBF1_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF1_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF1_CNTL__TYPE                                              u_int32_t
#define TXBF1_CNTL__READ                                            0xffffffffU

#endif /* __TXBF1_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF1_CNTL */
#define INST_SVD_REG_MAP__TXBF1_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF2_CNTL */
#ifndef __TXBF2_CNTL_MACRO__
#define __TXBF2_CNTL_MACRO__

/* macros for field OBS */
#define TXBF2_CNTL__OBS__SHIFT                                                0
#define TXBF2_CNTL__OBS__WIDTH                                               32
#define TXBF2_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF2_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF2_CNTL__TYPE                                              u_int32_t
#define TXBF2_CNTL__READ                                            0xffffffffU

#endif /* __TXBF2_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF2_CNTL */
#define INST_SVD_REG_MAP__TXBF2_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF3_CNTL */
#ifndef __TXBF3_CNTL_MACRO__
#define __TXBF3_CNTL_MACRO__

/* macros for field OBS */
#define TXBF3_CNTL__OBS__SHIFT                                                0
#define TXBF3_CNTL__OBS__WIDTH                                               32
#define TXBF3_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF3_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF3_CNTL__TYPE                                              u_int32_t
#define TXBF3_CNTL__READ                                            0xffffffffU

#endif /* __TXBF3_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF3_CNTL */
#define INST_SVD_REG_MAP__TXBF3_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF4_CNTL */
#ifndef __TXBF4_CNTL_MACRO__
#define __TXBF4_CNTL_MACRO__

/* macros for field OBS */
#define TXBF4_CNTL__OBS__SHIFT                                                0
#define TXBF4_CNTL__OBS__WIDTH                                               32
#define TXBF4_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF4_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF4_CNTL__TYPE                                              u_int32_t
#define TXBF4_CNTL__READ                                            0xffffffffU

#endif /* __TXBF4_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF4_CNTL */
#define INST_SVD_REG_MAP__TXBF4_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF5_CNTL */
#ifndef __TXBF5_CNTL_MACRO__
#define __TXBF5_CNTL_MACRO__

/* macros for field OBS */
#define TXBF5_CNTL__OBS__SHIFT                                                0
#define TXBF5_CNTL__OBS__WIDTH                                               32
#define TXBF5_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF5_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF5_CNTL__TYPE                                              u_int32_t
#define TXBF5_CNTL__READ                                            0xffffffffU

#endif /* __TXBF5_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF5_CNTL */
#define INST_SVD_REG_MAP__TXBF5_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF6_CNTL */
#ifndef __TXBF6_CNTL_MACRO__
#define __TXBF6_CNTL_MACRO__

/* macros for field OBS */
#define TXBF6_CNTL__OBS__SHIFT                                                0
#define TXBF6_CNTL__OBS__WIDTH                                               32
#define TXBF6_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF6_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF6_CNTL__TYPE                                              u_int32_t
#define TXBF6_CNTL__READ                                            0xffffffffU

#endif /* __TXBF6_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF6_CNTL */
#define INST_SVD_REG_MAP__TXBF6_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF7_CNTL */
#ifndef __TXBF7_CNTL_MACRO__
#define __TXBF7_CNTL_MACRO__

/* macros for field OBS */
#define TXBF7_CNTL__OBS__SHIFT                                                0
#define TXBF7_CNTL__OBS__WIDTH                                               32
#define TXBF7_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF7_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF7_CNTL__TYPE                                              u_int32_t
#define TXBF7_CNTL__READ                                            0xffffffffU

#endif /* __TXBF7_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF7_CNTL */
#define INST_SVD_REG_MAP__TXBF7_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::TXBF8_CNTL */
#ifndef __TXBF8_CNTL_MACRO__
#define __TXBF8_CNTL_MACRO__

/* macros for field OBS */
#define TXBF8_CNTL__OBS__SHIFT                                                0
#define TXBF8_CNTL__OBS__WIDTH                                               32
#define TXBF8_CNTL__OBS__MASK                                       0xffffffffU
#define TXBF8_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
#define TXBF8_CNTL__TYPE                                              u_int32_t
#define TXBF8_CNTL__READ                                            0xffffffffU

#endif /* __TXBF8_CNTL_MACRO__ */


/* macros for svd_reg_map.TXBF8_CNTL */
#define INST_SVD_REG_MAP__TXBF8_CNTL__NUM                                     1

/* macros for BlueprintGlobalNameSpace::RC0 */
#ifndef __RC0_MACRO__
#define __RC0_MACRO__

/* macros for field DATA */
#define RC0__DATA__SHIFT                                                      0
#define RC0__DATA__WIDTH                                                     32
#define RC0__DATA__MASK                                             0xffffffffU
#define RC0__DATA__READ(src)                     (u_int32_t)(src) & 0xffffffffU
#define RC0__DATA__WRITE(src)                  ((u_int32_t)(src) & 0xffffffffU)
#define RC0__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define RC0__DATA__VERIFY(src)           (!(((u_int32_t)(src) & ~0xffffffffU)))
#define RC0__TYPE                                                     u_int32_t
#define RC0__READ                                                   0xffffffffU
#define RC0__WRITE                                                  0xffffffffU

#endif /* __RC0_MACRO__ */


/* macros for svd_reg_map.RC0 */
#define INST_SVD_REG_MAP__RC0__NUM                                          118

/* macros for BlueprintGlobalNameSpace::RC1 */
#ifndef __RC1_MACRO__
#define __RC1_MACRO__

/* macros for field DATA */
#define RC1__DATA__SHIFT                                                      0
#define RC1__DATA__WIDTH                                                     32
#define RC1__DATA__MASK                                             0xffffffffU
#define RC1__DATA__READ(src)                     (u_int32_t)(src) & 0xffffffffU
#define RC1__DATA__WRITE(src)                  ((u_int32_t)(src) & 0xffffffffU)
#define RC1__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define RC1__DATA__VERIFY(src)           (!(((u_int32_t)(src) & ~0xffffffffU)))
#define RC1__TYPE                                                     u_int32_t
#define RC1__READ                                                   0xffffffffU
#define RC1__WRITE                                                  0xffffffffU

#endif /* __RC1_MACRO__ */


/* macros for svd_reg_map.RC1 */
#define INST_SVD_REG_MAP__RC1__NUM                                          118

/* macros for BlueprintGlobalNameSpace::SVD_MEM0 */
#ifndef __SVD_MEM0_MACRO__
#define __SVD_MEM0_MACRO__

/* macros for field DATA */
#define SVD_MEM0__DATA__SHIFT                                                 0
#define SVD_MEM0__DATA__WIDTH                                                32
#define SVD_MEM0__DATA__MASK                                        0xffffffffU
#define SVD_MEM0__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
#define SVD_MEM0__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
#define SVD_MEM0__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SVD_MEM0__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
#define SVD_MEM0__TYPE                                                u_int32_t
#define SVD_MEM0__READ                                              0xffffffffU
#define SVD_MEM0__WRITE                                             0xffffffffU

#endif /* __SVD_MEM0_MACRO__ */


/* macros for svd_reg_map.SVD_MEM0 */
#define INST_SVD_REG_MAP__SVD_MEM0__NUM                                     114

/* macros for BlueprintGlobalNameSpace::SVD_MEM1 */
#ifndef __SVD_MEM1_MACRO__
#define __SVD_MEM1_MACRO__

/* macros for field DATA */
#define SVD_MEM1__DATA__SHIFT                                                 0
#define SVD_MEM1__DATA__WIDTH                                                32
#define SVD_MEM1__DATA__MASK                                        0xffffffffU
#define SVD_MEM1__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
#define SVD_MEM1__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
#define SVD_MEM1__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SVD_MEM1__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
#define SVD_MEM1__TYPE                                                u_int32_t
#define SVD_MEM1__READ                                              0xffffffffU
#define SVD_MEM1__WRITE                                             0xffffffffU

#endif /* __SVD_MEM1_MACRO__ */


/* macros for svd_reg_map.SVD_MEM1 */
#define INST_SVD_REG_MAP__SVD_MEM1__NUM                                     114

/* macros for BlueprintGlobalNameSpace::SVD_MEM2 */
#ifndef __SVD_MEM2_MACRO__
#define __SVD_MEM2_MACRO__

/* macros for field DATA */
#define SVD_MEM2__DATA__SHIFT                                                 0
#define SVD_MEM2__DATA__WIDTH                                                32
#define SVD_MEM2__DATA__MASK                                        0xffffffffU
#define SVD_MEM2__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
#define SVD_MEM2__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
#define SVD_MEM2__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SVD_MEM2__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
#define SVD_MEM2__TYPE                                                u_int32_t
#define SVD_MEM2__READ                                              0xffffffffU
#define SVD_MEM2__WRITE                                             0xffffffffU

#endif /* __SVD_MEM2_MACRO__ */


/* macros for svd_reg_map.SVD_MEM2 */
#define INST_SVD_REG_MAP__SVD_MEM2__NUM                                     114

/* macros for BlueprintGlobalNameSpace::SVD_MEM3 */
#ifndef __SVD_MEM3_MACRO__
#define __SVD_MEM3_MACRO__

/* macros for field DATA */
#define SVD_MEM3__DATA__SHIFT                                                 0
#define SVD_MEM3__DATA__WIDTH                                                32
#define SVD_MEM3__DATA__MASK                                        0xffffffffU
#define SVD_MEM3__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
#define SVD_MEM3__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
#define SVD_MEM3__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SVD_MEM3__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
#define SVD_MEM3__TYPE                                                u_int32_t
#define SVD_MEM3__READ                                              0xffffffffU
#define SVD_MEM3__WRITE                                             0xffffffffU

#endif /* __SVD_MEM3_MACRO__ */


/* macros for svd_reg_map.SVD_MEM3 */
#define INST_SVD_REG_MAP__SVD_MEM3__NUM                                     114

/* macros for BlueprintGlobalNameSpace::SVD_MEM4 */
#ifndef __SVD_MEM4_MACRO__
#define __SVD_MEM4_MACRO__

/* macros for field DATA */
#define SVD_MEM4__DATA__SHIFT                                                 0
#define SVD_MEM4__DATA__WIDTH                                                32
#define SVD_MEM4__DATA__MASK                                        0xffffffffU
#define SVD_MEM4__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
#define SVD_MEM4__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
#define SVD_MEM4__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define SVD_MEM4__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
#define SVD_MEM4__TYPE                                                u_int32_t
#define SVD_MEM4__READ                                              0xffffffffU
#define SVD_MEM4__WRITE                                             0xffffffffU

#endif /* __SVD_MEM4_MACRO__ */


/* macros for svd_reg_map.SVD_MEM4 */
#define INST_SVD_REG_MAP__SVD_MEM4__NUM                                     114

/* macros for BlueprintGlobalNameSpace::CVCACHE */
#ifndef __CVCACHE_MACRO__
#define __CVCACHE_MACRO__

/* macros for field DATA */
#define CVCACHE__DATA__SHIFT                                                  0
#define CVCACHE__DATA__WIDTH                                                 32
#define CVCACHE__DATA__MASK                                         0xffffffffU
#define CVCACHE__DATA__READ(src)                 (u_int32_t)(src) & 0xffffffffU
#define CVCACHE__DATA__WRITE(src)              ((u_int32_t)(src) & 0xffffffffU)
#define CVCACHE__DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CVCACHE__DATA__VERIFY(src)       (!(((u_int32_t)(src) & ~0xffffffffU)))
#define CVCACHE__TYPE                                                 u_int32_t
#define CVCACHE__READ                                               0xffffffffU
#define CVCACHE__WRITE                                              0xffffffffU

#endif /* __CVCACHE_MACRO__ */


/* macros for svd_reg_map.CVCACHE */
#define INST_SVD_REG_MAP__CVCACHE__NUM                                      512

/* macros for BlueprintGlobalNameSpace::RXRF_BIAS1 */
#ifndef __RXRF_BIAS1_MACRO__
#define __RXRF_BIAS1_MACRO__

/* macros for field SPARE */
#define RXRF_BIAS1__SPARE__SHIFT                                              0
#define RXRF_BIAS1__SPARE__WIDTH                                              1
#define RXRF_BIAS1__SPARE__MASK                                     0x00000001U
#define RXRF_BIAS1__SPARE__READ(src)             (u_int32_t)(src) & 0x00000001U
#define RXRF_BIAS1__SPARE__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
#define RXRF_BIAS1__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXRF_BIAS1__SPARE__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
#define RXRF_BIAS1__SPARE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RXRF_BIAS1__SPARE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field PWD_IR25SPARE */
#define RXRF_BIAS1__PWD_IR25SPARE__SHIFT                                      1
#define RXRF_BIAS1__PWD_IR25SPARE__WIDTH                                      3
#define RXRF_BIAS1__PWD_IR25SPARE__MASK                             0x0000000eU
#define RXRF_BIAS1__PWD_IR25SPARE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000eU) >> 1)
#define RXRF_BIAS1__PWD_IR25SPARE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000000eU)
#define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define RXRF_BIAS1__PWD_IR25SPARE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field PWD_IR25LO18 */
#define RXRF_BIAS1__PWD_IR25LO18__SHIFT                                       4
#define RXRF_BIAS1__PWD_IR25LO18__WIDTH                                       3
#define RXRF_BIAS1__PWD_IR25LO18__MASK                              0x00000070U
#define RXRF_BIAS1__PWD_IR25LO18__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000070U) >> 4)
#define RXRF_BIAS1__PWD_IR25LO18__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000070U)
#define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((u_int32_t)(src) <<\
                    4) & 0x00000070U)
#define RXRF_BIAS1__PWD_IR25LO18__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field PWD_IC25LO36 */
#define RXRF_BIAS1__PWD_IC25LO36__SHIFT                                       7
#define RXRF_BIAS1__PWD_IC25LO36__WIDTH                                       3
#define RXRF_BIAS1__PWD_IC25LO36__MASK                              0x00000380U
#define RXRF_BIAS1__PWD_IC25LO36__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000380U) >> 7)
#define RXRF_BIAS1__PWD_IC25LO36__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000380U)
#define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000380U) | (((u_int32_t)(src) <<\
                    7) & 0x00000380U)
#define RXRF_BIAS1__PWD_IC25LO36__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000380U)))

/* macros for field PWD_IC25MXR2_5GH */
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__SHIFT                                  10
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WIDTH                                   3
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MASK                          0x00001c00U
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001c00U) >> 10)
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00001c00U)
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00001c00U)
#define RXRF_BIAS1__PWD_IC25MXR2_5GH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00001c00U)))

/* macros for field PWD_IC25MXR5GH */
#define RXRF_BIAS1__PWD_IC25MXR5GH__SHIFT                                    13
#define RXRF_BIAS1__PWD_IC25MXR5GH__WIDTH                                     3
#define RXRF_BIAS1__PWD_IC25MXR5GH__MASK                            0x0000e000U
#define RXRF_BIAS1__PWD_IC25MXR5GH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000e000U) >> 13)
#define RXRF_BIAS1__PWD_IC25MXR5GH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x0000e000U)
#define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0000e000U)
#define RXRF_BIAS1__PWD_IC25MXR5GH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0000e000U)))

/* macros for field PWD_IC25VGA5G */
#define RXRF_BIAS1__PWD_IC25VGA5G__SHIFT                                     16
#define RXRF_BIAS1__PWD_IC25VGA5G__WIDTH                                      3
#define RXRF_BIAS1__PWD_IC25VGA5G__MASK                             0x00070000U
#define RXRF_BIAS1__PWD_IC25VGA5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00070000U) >> 16)
#define RXRF_BIAS1__PWD_IC25VGA5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00070000U)
#define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((u_int32_t)(src) <<\
                    16) & 0x00070000U)
#define RXRF_BIAS1__PWD_IC25VGA5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field PWD_IC75LNA5G */
#define RXRF_BIAS1__PWD_IC75LNA5G__SHIFT                                     19
#define RXRF_BIAS1__PWD_IC75LNA5G__WIDTH                                      3
#define RXRF_BIAS1__PWD_IC75LNA5G__MASK                             0x00380000U
#define RXRF_BIAS1__PWD_IC75LNA5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00380000U) >> 19)
#define RXRF_BIAS1__PWD_IC75LNA5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00380000U)
#define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00380000U) | (((u_int32_t)(src) <<\
                    19) & 0x00380000U)
#define RXRF_BIAS1__PWD_IC75LNA5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00380000U)))

/* macros for field PWD_IR25LO24 */
#define RXRF_BIAS1__PWD_IR25LO24__SHIFT                                      22
#define RXRF_BIAS1__PWD_IR25LO24__WIDTH                                       3
#define RXRF_BIAS1__PWD_IR25LO24__MASK                              0x01c00000U
#define RXRF_BIAS1__PWD_IR25LO24__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01c00000U) >> 22)
#define RXRF_BIAS1__PWD_IR25LO24__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x01c00000U)
#define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x01c00000U)
#define RXRF_BIAS1__PWD_IR25LO24__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x01c00000U)))

/* macros for field PWD_IC25MXR2GH */
#define RXRF_BIAS1__PWD_IC25MXR2GH__SHIFT                                    25
#define RXRF_BIAS1__PWD_IC25MXR2GH__WIDTH                                     3
#define RXRF_BIAS1__PWD_IC25MXR2GH__MASK                            0x0e000000U
#define RXRF_BIAS1__PWD_IC25MXR2GH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0e000000U) >> 25)
#define RXRF_BIAS1__PWD_IC25MXR2GH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x0e000000U)
#define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x0e000000U)
#define RXRF_BIAS1__PWD_IC25MXR2GH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x0e000000U)))

/* macros for field PWD_IC75LNA2G */
#define RXRF_BIAS1__PWD_IC75LNA2G__SHIFT                                     28
#define RXRF_BIAS1__PWD_IC75LNA2G__WIDTH                                      3
#define RXRF_BIAS1__PWD_IC75LNA2G__MASK                             0x70000000U
#define RXRF_BIAS1__PWD_IC75LNA2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x70000000U) >> 28)
#define RXRF_BIAS1__PWD_IC75LNA2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x70000000U)
#define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x70000000U) | (((u_int32_t)(src) <<\
                    28) & 0x70000000U)
#define RXRF_BIAS1__PWD_IC75LNA2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x70000000U)))

/* macros for field PWD_BIAS */
#define RXRF_BIAS1__PWD_BIAS__SHIFT                                          31
#define RXRF_BIAS1__PWD_BIAS__WIDTH                                           1
#define RXRF_BIAS1__PWD_BIAS__MASK                                  0x80000000U
#define RXRF_BIAS1__PWD_BIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define RXRF_BIAS1__PWD_BIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RXRF_BIAS1__PWD_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RXRF_BIAS1__PWD_BIAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RXRF_BIAS1__PWD_BIAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RXRF_BIAS1__TYPE                                              u_int32_t
#define RXRF_BIAS1__READ                                            0xffffffffU
#define RXRF_BIAS1__WRITE                                           0xffffffffU

#endif /* __RXRF_BIAS1_MACRO__ */


/* macros for radio65_reg_map.ch0_RXRF_BIAS1 */
#define INST_RADIO65_REG_MAP__CH0_RXRF_BIAS1__NUM                             1

/* macros for BlueprintGlobalNameSpace::RXRF_BIAS2 */
#ifndef __RXRF_BIAS2_MACRO__
#define __RXRF_BIAS2_MACRO__

/* macros for field SPARE */
#define RXRF_BIAS2__SPARE__SHIFT                                              0
#define RXRF_BIAS2__SPARE__WIDTH                                              1
#define RXRF_BIAS2__SPARE__MASK                                     0x00000001U
#define RXRF_BIAS2__SPARE__READ(src)             (u_int32_t)(src) & 0x00000001U
#define RXRF_BIAS2__SPARE__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
#define RXRF_BIAS2__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXRF_BIAS2__SPARE__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
#define RXRF_BIAS2__SPARE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RXRF_BIAS2__SPARE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field PKEN */
#define RXRF_BIAS2__PKEN__SHIFT                                               1
#define RXRF_BIAS2__PKEN__WIDTH                                               3
#define RXRF_BIAS2__PKEN__MASK                                      0x0000000eU
#define RXRF_BIAS2__PKEN__READ(src)     (((u_int32_t)(src) & 0x0000000eU) >> 1)
#define RXRF_BIAS2__PKEN__WRITE(src)    (((u_int32_t)(src) << 1) & 0x0000000eU)
#define RXRF_BIAS2__PKEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define RXRF_BIAS2__PKEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field VCMVALUE */
#define RXRF_BIAS2__VCMVALUE__SHIFT                                           4
#define RXRF_BIAS2__VCMVALUE__WIDTH                                           3
#define RXRF_BIAS2__VCMVALUE__MASK                                  0x00000070U
#define RXRF_BIAS2__VCMVALUE__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4)
#define RXRF_BIAS2__VCMVALUE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000070U)
#define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((u_int32_t)(src) <<\
                    4) & 0x00000070U)
#define RXRF_BIAS2__VCMVALUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field PWD_VCMBUF */
#define RXRF_BIAS2__PWD_VCMBUF__SHIFT                                         7
#define RXRF_BIAS2__PWD_VCMBUF__WIDTH                                         1
#define RXRF_BIAS2__PWD_VCMBUF__MASK                                0x00000080U
#define RXRF_BIAS2__PWD_VCMBUF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define RXRF_BIAS2__PWD_VCMBUF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RXRF_BIAS2__PWD_VCMBUF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define RXRF_BIAS2__PWD_VCMBUF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RXRF_BIAS2__PWD_VCMBUF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field PWD_IR25SPAREH */
#define RXRF_BIAS2__PWD_IR25SPAREH__SHIFT                                     8
#define RXRF_BIAS2__PWD_IR25SPAREH__WIDTH                                     3
#define RXRF_BIAS2__PWD_IR25SPAREH__MASK                            0x00000700U
#define RXRF_BIAS2__PWD_IR25SPAREH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)
#define RXRF_BIAS2__PWD_IR25SPAREH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000700U)
#define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define RXRF_BIAS2__PWD_IR25SPAREH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field PWD_IR25SPARE */
#define RXRF_BIAS2__PWD_IR25SPARE__SHIFT                                     11
#define RXRF_BIAS2__PWD_IR25SPARE__WIDTH                                      3
#define RXRF_BIAS2__PWD_IR25SPARE__MASK                             0x00003800U
#define RXRF_BIAS2__PWD_IR25SPARE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003800U) >> 11)
#define RXRF_BIAS2__PWD_IR25SPARE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00003800U)
#define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define RXRF_BIAS2__PWD_IR25SPARE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field PWD_IC25LNABUF */
#define RXRF_BIAS2__PWD_IC25LNABUF__SHIFT                                    14
#define RXRF_BIAS2__PWD_IC25LNABUF__WIDTH                                     3
#define RXRF_BIAS2__PWD_IC25LNABUF__MASK                            0x0001c000U
#define RXRF_BIAS2__PWD_IC25LNABUF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001c000U) >> 14)
#define RXRF_BIAS2__PWD_IC25LNABUF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0001c000U)
#define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define RXRF_BIAS2__PWD_IC25LNABUF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field PWD_IR25AGCH */
#define RXRF_BIAS2__PWD_IR25AGCH__SHIFT                                      17
#define RXRF_BIAS2__PWD_IR25AGCH__WIDTH                                       3
#define RXRF_BIAS2__PWD_IR25AGCH__MASK                              0x000e0000U
#define RXRF_BIAS2__PWD_IR25AGCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000e0000U) >> 17)
#define RXRF_BIAS2__PWD_IR25AGCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x000e0000U)
#define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define RXRF_BIAS2__PWD_IR25AGCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field PWD_IR25AGC */
#define RXRF_BIAS2__PWD_IR25AGC__SHIFT                                       20
#define RXRF_BIAS2__PWD_IR25AGC__WIDTH                                        3
#define RXRF_BIAS2__PWD_IR25AGC__MASK                               0x00700000U
#define RXRF_BIAS2__PWD_IR25AGC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00700000U) >> 20)
#define RXRF_BIAS2__PWD_IR25AGC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00700000U)
#define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define RXRF_BIAS2__PWD_IR25AGC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field PWD_IC25AGC */
#define RXRF_BIAS2__PWD_IC25AGC__SHIFT                                       23
#define RXRF_BIAS2__PWD_IC25AGC__WIDTH                                        3
#define RXRF_BIAS2__PWD_IC25AGC__MASK                               0x03800000U
#define RXRF_BIAS2__PWD_IC25AGC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03800000U) >> 23)
#define RXRF_BIAS2__PWD_IC25AGC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x03800000U)
#define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define RXRF_BIAS2__PWD_IC25AGC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field PWD_IC25VCMBUF */
#define RXRF_BIAS2__PWD_IC25VCMBUF__SHIFT                                    26
#define RXRF_BIAS2__PWD_IC25VCMBUF__WIDTH                                     3
#define RXRF_BIAS2__PWD_IC25VCMBUF__MASK                            0x1c000000U
#define RXRF_BIAS2__PWD_IC25VCMBUF__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define RXRF_BIAS2__PWD_IC25VCMBUF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define RXRF_BIAS2__PWD_IC25VCMBUF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field PWD_IR25VCM */
#define RXRF_BIAS2__PWD_IR25VCM__SHIFT                                       29
#define RXRF_BIAS2__PWD_IR25VCM__WIDTH                                        3
#define RXRF_BIAS2__PWD_IR25VCM__MASK                               0xe0000000U
#define RXRF_BIAS2__PWD_IR25VCM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xe0000000U) >> 29)
#define RXRF_BIAS2__PWD_IR25VCM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0xe0000000U)
#define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define RXRF_BIAS2__PWD_IR25VCM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define RXRF_BIAS2__TYPE                                              u_int32_t
#define RXRF_BIAS2__READ                                            0xffffffffU
#define RXRF_BIAS2__WRITE                                           0xffffffffU

#endif /* __RXRF_BIAS2_MACRO__ */


/* macros for radio65_reg_map.ch0_RXRF_BIAS2 */
#define INST_RADIO65_REG_MAP__CH0_RXRF_BIAS2__NUM                             1

/* macros for BlueprintGlobalNameSpace::RXRF_GAINSTAGES */
#ifndef __RXRF_GAINSTAGES_MACRO__
#define __RXRF_GAINSTAGES_MACRO__

/* macros for field SPARE */
#define RXRF_GAINSTAGES__SPARE__SHIFT                                         0
#define RXRF_GAINSTAGES__SPARE__WIDTH                                         1
#define RXRF_GAINSTAGES__SPARE__MASK                                0x00000001U
#define RXRF_GAINSTAGES__SPARE__READ(src)        (u_int32_t)(src) & 0x00000001U
#define RXRF_GAINSTAGES__SPARE__WRITE(src)     ((u_int32_t)(src) & 0x00000001U)
#define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXRF_GAINSTAGES__SPARE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RXRF_GAINSTAGES__SPARE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RXRF_GAINSTAGES__SPARE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field LNAON_CALDC */
#define RXRF_GAINSTAGES__LNAON_CALDC__SHIFT                                   1
#define RXRF_GAINSTAGES__LNAON_CALDC__WIDTH                                   1
#define RXRF_GAINSTAGES__LNAON_CALDC__MASK                          0x00000002U
#define RXRF_GAINSTAGES__LNAON_CALDC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RXRF_GAINSTAGES__LNAON_CALDC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RXRF_GAINSTAGES__LNAON_CALDC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RXRF_GAINSTAGES__LNAON_CALDC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RXRF_GAINSTAGES__LNAON_CALDC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field VGA5G_CAP */
#define RXRF_GAINSTAGES__VGA5G_CAP__SHIFT                                     2
#define RXRF_GAINSTAGES__VGA5G_CAP__WIDTH                                     2
#define RXRF_GAINSTAGES__VGA5G_CAP__MASK                            0x0000000cU
#define RXRF_GAINSTAGES__VGA5G_CAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define RXRF_GAINSTAGES__VGA5G_CAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define RXRF_GAINSTAGES__VGA5G_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field LNA5G_CAP */
#define RXRF_GAINSTAGES__LNA5G_CAP__SHIFT                                     4
#define RXRF_GAINSTAGES__LNA5G_CAP__WIDTH                                     2
#define RXRF_GAINSTAGES__LNA5G_CAP__MASK                            0x00000030U
#define RXRF_GAINSTAGES__LNA5G_CAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define RXRF_GAINSTAGES__LNA5G_CAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define RXRF_GAINSTAGES__LNA5G_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field LNA5G_SHORTINP */
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SHIFT                                6
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WIDTH                                1
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MASK                       0x00000040U
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define RXRF_GAINSTAGES__LNA5G_SHORTINP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field PWD_LO5G */
#define RXRF_GAINSTAGES__PWD_LO5G__SHIFT                                      7
#define RXRF_GAINSTAGES__PWD_LO5G__WIDTH                                      1
#define RXRF_GAINSTAGES__PWD_LO5G__MASK                             0x00000080U
#define RXRF_GAINSTAGES__PWD_LO5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define RXRF_GAINSTAGES__PWD_LO5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RXRF_GAINSTAGES__PWD_LO5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define RXRF_GAINSTAGES__PWD_LO5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RXRF_GAINSTAGES__PWD_LO5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field PWD_VGA5G */
#define RXRF_GAINSTAGES__PWD_VGA5G__SHIFT                                     8
#define RXRF_GAINSTAGES__PWD_VGA5G__WIDTH                                     1
#define RXRF_GAINSTAGES__PWD_VGA5G__MASK                            0x00000100U
#define RXRF_GAINSTAGES__PWD_VGA5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define RXRF_GAINSTAGES__PWD_VGA5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define RXRF_GAINSTAGES__PWD_VGA5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define RXRF_GAINSTAGES__PWD_VGA5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define RXRF_GAINSTAGES__PWD_VGA5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field PWD_MXR5G */
#define RXRF_GAINSTAGES__PWD_MXR5G__SHIFT                                     9
#define RXRF_GAINSTAGES__PWD_MXR5G__WIDTH                                     1
#define RXRF_GAINSTAGES__PWD_MXR5G__MASK                            0x00000200U
#define RXRF_GAINSTAGES__PWD_MXR5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define RXRF_GAINSTAGES__PWD_MXR5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define RXRF_GAINSTAGES__PWD_MXR5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define RXRF_GAINSTAGES__PWD_MXR5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define RXRF_GAINSTAGES__PWD_MXR5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field PWD_LNA5G */
#define RXRF_GAINSTAGES__PWD_LNA5G__SHIFT                                    10
#define RXRF_GAINSTAGES__PWD_LNA5G__WIDTH                                     1
#define RXRF_GAINSTAGES__PWD_LNA5G__MASK                            0x00000400U
#define RXRF_GAINSTAGES__PWD_LNA5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define RXRF_GAINSTAGES__PWD_LNA5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define RXRF_GAINSTAGES__PWD_LNA5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define RXRF_GAINSTAGES__PWD_LNA5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define RXRF_GAINSTAGES__PWD_LNA5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field LNA2G_CAP */
#define RXRF_GAINSTAGES__LNA2G_CAP__SHIFT                                    11
#define RXRF_GAINSTAGES__LNA2G_CAP__WIDTH                                     2
#define RXRF_GAINSTAGES__LNA2G_CAP__MASK                            0x00001800U
#define RXRF_GAINSTAGES__LNA2G_CAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001800U) >> 11)
#define RXRF_GAINSTAGES__LNA2G_CAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00001800U)
#define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001800U) | (((u_int32_t)(src) <<\
                    11) & 0x00001800U)
#define RXRF_GAINSTAGES__LNA2G_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00001800U)))

/* macros for field LNA2G_SHORTINP */
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SHIFT                               13
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WIDTH                                1
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MASK                       0x00002000U
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define RXRF_GAINSTAGES__LNA2G_SHORTINP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field LNA2G_LP */
#define RXRF_GAINSTAGES__LNA2G_LP__SHIFT                                     14
#define RXRF_GAINSTAGES__LNA2G_LP__WIDTH                                      1
#define RXRF_GAINSTAGES__LNA2G_LP__MASK                             0x00004000U
#define RXRF_GAINSTAGES__LNA2G_LP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define RXRF_GAINSTAGES__LNA2G_LP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define RXRF_GAINSTAGES__LNA2G_LP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define RXRF_GAINSTAGES__LNA2G_LP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define RXRF_GAINSTAGES__LNA2G_LP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field PWD_LO2G */
#define RXRF_GAINSTAGES__PWD_LO2G__SHIFT                                     15
#define RXRF_GAINSTAGES__PWD_LO2G__WIDTH                                      1
#define RXRF_GAINSTAGES__PWD_LO2G__MASK                             0x00008000U
#define RXRF_GAINSTAGES__PWD_LO2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define RXRF_GAINSTAGES__PWD_LO2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define RXRF_GAINSTAGES__PWD_LO2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define RXRF_GAINSTAGES__PWD_LO2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define RXRF_GAINSTAGES__PWD_LO2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field PWD_MXR2G */
#define RXRF_GAINSTAGES__PWD_MXR2G__SHIFT                                    16
#define RXRF_GAINSTAGES__PWD_MXR2G__WIDTH                                     1
#define RXRF_GAINSTAGES__PWD_MXR2G__MASK                            0x00010000U
#define RXRF_GAINSTAGES__PWD_MXR2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define RXRF_GAINSTAGES__PWD_MXR2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define RXRF_GAINSTAGES__PWD_MXR2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define RXRF_GAINSTAGES__PWD_MXR2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define RXRF_GAINSTAGES__PWD_MXR2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field PWD_LNA2G */
#define RXRF_GAINSTAGES__PWD_LNA2G__SHIFT                                    17
#define RXRF_GAINSTAGES__PWD_LNA2G__WIDTH                                     1
#define RXRF_GAINSTAGES__PWD_LNA2G__MASK                            0x00020000U
#define RXRF_GAINSTAGES__PWD_LNA2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define RXRF_GAINSTAGES__PWD_LNA2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define RXRF_GAINSTAGES__PWD_LNA2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define RXRF_GAINSTAGES__PWD_LNA2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define RXRF_GAINSTAGES__PWD_LNA2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field MXR5G_GAIN_OVR */
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__SHIFT                               18
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WIDTH                                2
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MASK                       0x000c0000U
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000c0000U) >> 18)
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x000c0000U)
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x000c0000U)
#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x000c0000U)))

/* macros for field VGA5G_GAIN_OVR */
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__SHIFT                               20
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WIDTH                                3
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MASK                       0x00700000U
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00700000U) >> 20)
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00700000U)
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field LNA5G_GAIN_OVR */
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__SHIFT                               23
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WIDTH                                3
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MASK                       0x03800000U
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03800000U) >> 23)
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x03800000U)
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field MXR2G_GAIN_OVR */
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__SHIFT                               26
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WIDTH                                2
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MASK                       0x0c000000U
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0c000000U) >> 26)
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x0c000000U)
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x0c000000U)
#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x0c000000U)))

/* macros for field LNA2G_GAIN_OVR */
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__SHIFT                               28
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WIDTH                                3
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MASK                       0x70000000U
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x70000000U) >> 28)
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x70000000U)
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x70000000U) | (((u_int32_t)(src) <<\
                    28) & 0x70000000U)
#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x70000000U)))

/* macros for field RX_OVERRIDE */
#define RXRF_GAINSTAGES__RX_OVERRIDE__SHIFT                                  31
#define RXRF_GAINSTAGES__RX_OVERRIDE__WIDTH                                   1
#define RXRF_GAINSTAGES__RX_OVERRIDE__MASK                          0x80000000U
#define RXRF_GAINSTAGES__RX_OVERRIDE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define RXRF_GAINSTAGES__RX_OVERRIDE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RXRF_GAINSTAGES__RX_OVERRIDE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RXRF_GAINSTAGES__RX_OVERRIDE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RXRF_GAINSTAGES__RX_OVERRIDE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RXRF_GAINSTAGES__TYPE                                         u_int32_t
#define RXRF_GAINSTAGES__READ                                       0xffffffffU
#define RXRF_GAINSTAGES__WRITE                                      0xffffffffU

#endif /* __RXRF_GAINSTAGES_MACRO__ */


/* macros for radio65_reg_map.ch0_RXRF_GAINSTAGES */
#define INST_RADIO65_REG_MAP__CH0_RXRF_GAINSTAGES__NUM                        1

/* macros for BlueprintGlobalNameSpace::RXRF_AGC */
#ifndef __RXRF_AGC_MACRO__
#define __RXRF_AGC_MACRO__

/* macros for field RF5G_ON_DURING_CALPA */
#define RXRF_AGC__RF5G_ON_DURING_CALPA__SHIFT                                 0
#define RXRF_AGC__RF5G_ON_DURING_CALPA__WIDTH                                 1
#define RXRF_AGC__RF5G_ON_DURING_CALPA__MASK                        0x00000001U
#define RXRF_AGC__RF5G_ON_DURING_CALPA__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RXRF_AGC__RF5G_ON_DURING_CALPA__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXRF_AGC__RF5G_ON_DURING_CALPA__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RXRF_AGC__RF5G_ON_DURING_CALPA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RXRF_AGC__RF5G_ON_DURING_CALPA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field RF2G_ON_DURING_CALPA */
#define RXRF_AGC__RF2G_ON_DURING_CALPA__SHIFT                                 1
#define RXRF_AGC__RF2G_ON_DURING_CALPA__WIDTH                                 1
#define RXRF_AGC__RF2G_ON_DURING_CALPA__MASK                        0x00000002U
#define RXRF_AGC__RF2G_ON_DURING_CALPA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RXRF_AGC__RF2G_ON_DURING_CALPA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RXRF_AGC__RF2G_ON_DURING_CALPA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RXRF_AGC__RF2G_ON_DURING_CALPA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RXRF_AGC__RF2G_ON_DURING_CALPA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field AGC_OUT */
#define RXRF_AGC__AGC_OUT__SHIFT                                              2
#define RXRF_AGC__AGC_OUT__WIDTH                                              1
#define RXRF_AGC__AGC_OUT__MASK                                     0x00000004U
#define RXRF_AGC__AGC_OUT__READ(src)    (((u_int32_t)(src) & 0x00000004U) >> 2)
#define RXRF_AGC__AGC_OUT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RXRF_AGC__AGC_OUT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field LNABUFGAIN2X */
#define RXRF_AGC__LNABUFGAIN2X__SHIFT                                         3
#define RXRF_AGC__LNABUFGAIN2X__WIDTH                                         1
#define RXRF_AGC__LNABUFGAIN2X__MASK                                0x00000008U
#define RXRF_AGC__LNABUFGAIN2X__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RXRF_AGC__LNABUFGAIN2X__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RXRF_AGC__LNABUFGAIN2X__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RXRF_AGC__LNABUFGAIN2X__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RXRF_AGC__LNABUFGAIN2X__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field LNABUF_PWD_OVR */
#define RXRF_AGC__LNABUF_PWD_OVR__SHIFT                                       4
#define RXRF_AGC__LNABUF_PWD_OVR__WIDTH                                       1
#define RXRF_AGC__LNABUF_PWD_OVR__MASK                              0x00000010U
#define RXRF_AGC__LNABUF_PWD_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RXRF_AGC__LNABUF_PWD_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RXRF_AGC__LNABUF_PWD_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RXRF_AGC__LNABUF_PWD_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RXRF_AGC__LNABUF_PWD_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PWD_LNABUF */
#define RXRF_AGC__PWD_LNABUF__SHIFT                                           5
#define RXRF_AGC__PWD_LNABUF__WIDTH                                           1
#define RXRF_AGC__PWD_LNABUF__MASK                                  0x00000020U
#define RXRF_AGC__PWD_LNABUF__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
#define RXRF_AGC__PWD_LNABUF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define RXRF_AGC__PWD_LNABUF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define RXRF_AGC__PWD_LNABUF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RXRF_AGC__PWD_LNABUF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field AGC_FALL_CTRL */
#define RXRF_AGC__AGC_FALL_CTRL__SHIFT                                        6
#define RXRF_AGC__AGC_FALL_CTRL__WIDTH                                        3
#define RXRF_AGC__AGC_FALL_CTRL__MASK                               0x000001c0U
#define RXRF_AGC__AGC_FALL_CTRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001c0U) >> 6)
#define RXRF_AGC__AGC_FALL_CTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000001c0U)
#define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000001c0U)
#define RXRF_AGC__AGC_FALL_CTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000001c0U)))

/* macros for field AGC5G_CALDAC_OVR */
#define RXRF_AGC__AGC5G_CALDAC_OVR__SHIFT                                     9
#define RXRF_AGC__AGC5G_CALDAC_OVR__WIDTH                                     6
#define RXRF_AGC__AGC5G_CALDAC_OVR__MASK                            0x00007e00U
#define RXRF_AGC__AGC5G_CALDAC_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007e00U) >> 9)
#define RXRF_AGC__AGC5G_CALDAC_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00007e00U)
#define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00007e00U)
#define RXRF_AGC__AGC5G_CALDAC_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00007e00U)))

/* macros for field AGC5G_DBDAC_OVR */
#define RXRF_AGC__AGC5G_DBDAC_OVR__SHIFT                                     15
#define RXRF_AGC__AGC5G_DBDAC_OVR__WIDTH                                      4
#define RXRF_AGC__AGC5G_DBDAC_OVR__MASK                             0x00078000U
#define RXRF_AGC__AGC5G_DBDAC_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00078000U) >> 15)
#define RXRF_AGC__AGC5G_DBDAC_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00078000U)
#define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00078000U) | (((u_int32_t)(src) <<\
                    15) & 0x00078000U)
#define RXRF_AGC__AGC5G_DBDAC_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00078000U)))

/* macros for field AGC2G_CALDAC_OVR */
#define RXRF_AGC__AGC2G_CALDAC_OVR__SHIFT                                    19
#define RXRF_AGC__AGC2G_CALDAC_OVR__WIDTH                                     6
#define RXRF_AGC__AGC2G_CALDAC_OVR__MASK                            0x01f80000U
#define RXRF_AGC__AGC2G_CALDAC_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01f80000U) >> 19)
#define RXRF_AGC__AGC2G_CALDAC_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x01f80000U)
#define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01f80000U) | (((u_int32_t)(src) <<\
                    19) & 0x01f80000U)
#define RXRF_AGC__AGC2G_CALDAC_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x01f80000U)))

/* macros for field AGC2G_DBDAC_OVR */
#define RXRF_AGC__AGC2G_DBDAC_OVR__SHIFT                                     25
#define RXRF_AGC__AGC2G_DBDAC_OVR__WIDTH                                      4
#define RXRF_AGC__AGC2G_DBDAC_OVR__MASK                             0x1e000000U
#define RXRF_AGC__AGC2G_DBDAC_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1e000000U) >> 25)
#define RXRF_AGC__AGC2G_DBDAC_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x1e000000U)
#define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x1e000000U)
#define RXRF_AGC__AGC2G_DBDAC_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x1e000000U)))

/* macros for field AGC_CAL_OVR */
#define RXRF_AGC__AGC_CAL_OVR__SHIFT                                         29
#define RXRF_AGC__AGC_CAL_OVR__WIDTH                                          1
#define RXRF_AGC__AGC_CAL_OVR__MASK                                 0x20000000U
#define RXRF_AGC__AGC_CAL_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define RXRF_AGC__AGC_CAL_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define RXRF_AGC__AGC_CAL_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define RXRF_AGC__AGC_CAL_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define RXRF_AGC__AGC_CAL_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field AGC_ON_OVR */
#define RXRF_AGC__AGC_ON_OVR__SHIFT                                          30
#define RXRF_AGC__AGC_ON_OVR__WIDTH                                           1
#define RXRF_AGC__AGC_ON_OVR__MASK                                  0x40000000U
#define RXRF_AGC__AGC_ON_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define RXRF_AGC__AGC_ON_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define RXRF_AGC__AGC_ON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define RXRF_AGC__AGC_ON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define RXRF_AGC__AGC_ON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field AGC_OVERRIDE */
#define RXRF_AGC__AGC_OVERRIDE__SHIFT                                        31
#define RXRF_AGC__AGC_OVERRIDE__WIDTH                                         1
#define RXRF_AGC__AGC_OVERRIDE__MASK                                0x80000000U
#define RXRF_AGC__AGC_OVERRIDE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define RXRF_AGC__AGC_OVERRIDE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RXRF_AGC__AGC_OVERRIDE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RXRF_AGC__AGC_OVERRIDE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RXRF_AGC__AGC_OVERRIDE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RXRF_AGC__TYPE                                                u_int32_t
#define RXRF_AGC__READ                                              0xffffffffU
#define RXRF_AGC__WRITE                                             0xffffffffU

#endif /* __RXRF_AGC_MACRO__ */


/* macros for radio65_reg_map.ch0_RXRF_AGC */
#define INST_RADIO65_REG_MAP__CH0_RXRF_AGC__NUM                               1

/* macros for BlueprintGlobalNameSpace::TXRF1 */
#ifndef __TXRF1_MACRO__
#define __TXRF1_MACRO__

/* macros for field pdlobuf5G */
#define TXRF1__PDLOBUF5G__SHIFT                                               0
#define TXRF1__PDLOBUF5G__WIDTH                                               1
#define TXRF1__PDLOBUF5G__MASK                                      0x00000001U
#define TXRF1__PDLOBUF5G__READ(src)              (u_int32_t)(src) & 0x00000001U
#define TXRF1__PDLOBUF5G__WRITE(src)           ((u_int32_t)(src) & 0x00000001U)
#define TXRF1__PDLOBUF5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TXRF1__PDLOBUF5G__VERIFY(src)    (!(((u_int32_t)(src) & ~0x00000001U)))
#define TXRF1__PDLOBUF5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXRF1__PDLOBUF5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field pdlodiv5G */
#define TXRF1__PDLODIV5G__SHIFT                                               1
#define TXRF1__PDLODIV5G__WIDTH                                               1
#define TXRF1__PDLODIV5G__MASK                                      0x00000002U
#define TXRF1__PDLODIV5G__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
#define TXRF1__PDLODIV5G__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
#define TXRF1__PDLODIV5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define TXRF1__PDLODIV5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define TXRF1__PDLODIV5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TXRF1__PDLODIV5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field LObuf5Gforced */
#define TXRF1__LOBUF5GFORCED__SHIFT                                           2
#define TXRF1__LOBUF5GFORCED__WIDTH                                           1
#define TXRF1__LOBUF5GFORCED__MASK                                  0x00000004U
#define TXRF1__LOBUF5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
#define TXRF1__LOBUF5GFORCED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define TXRF1__LOBUF5GFORCED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define TXRF1__LOBUF5GFORCED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TXRF1__LOBUF5GFORCED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field LOdiv5Gforced */
#define TXRF1__LODIV5GFORCED__SHIFT                                           3
#define TXRF1__LODIV5GFORCED__WIDTH                                           1
#define TXRF1__LODIV5GFORCED__MASK                                  0x00000008U
#define TXRF1__LODIV5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
#define TXRF1__LODIV5GFORCED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define TXRF1__LODIV5GFORCED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define TXRF1__LODIV5GFORCED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TXRF1__LODIV5GFORCED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field padrv2gn5G */
#define TXRF1__PADRV2GN5G__SHIFT                                              4
#define TXRF1__PADRV2GN5G__WIDTH                                              4
#define TXRF1__PADRV2GN5G__MASK                                     0x000000f0U
#define TXRF1__PADRV2GN5G__READ(src)    (((u_int32_t)(src) & 0x000000f0U) >> 4)
#define TXRF1__PADRV2GN5G__WRITE(src)   (((u_int32_t)(src) << 4) & 0x000000f0U)
#define TXRF1__PADRV2GN5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define TXRF1__PADRV2GN5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field padrv3gn5G */
#define TXRF1__PADRV3GN5G__SHIFT                                              8
#define TXRF1__PADRV3GN5G__WIDTH                                              4
#define TXRF1__PADRV3GN5G__MASK                                     0x00000f00U
#define TXRF1__PADRV3GN5G__READ(src)    (((u_int32_t)(src) & 0x00000f00U) >> 8)
#define TXRF1__PADRV3GN5G__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000f00U)
#define TXRF1__PADRV3GN5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define TXRF1__PADRV3GN5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field padrv4gn5G */
#define TXRF1__PADRV4GN5G__SHIFT                                             12
#define TXRF1__PADRV4GN5G__WIDTH                                              4
#define TXRF1__PADRV4GN5G__MASK                                     0x0000f000U
#define TXRF1__PADRV4GN5G__READ(src)   (((u_int32_t)(src) & 0x0000f000U) >> 12)
#define TXRF1__PADRV4GN5G__WRITE(src)  (((u_int32_t)(src) << 12) & 0x0000f000U)
#define TXRF1__PADRV4GN5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define TXRF1__PADRV4GN5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field localtxgain5G */
#define TXRF1__LOCALTXGAIN5G__SHIFT                                          16
#define TXRF1__LOCALTXGAIN5G__WIDTH                                           1
#define TXRF1__LOCALTXGAIN5G__MASK                                  0x00010000U
#define TXRF1__LOCALTXGAIN5G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define TXRF1__LOCALTXGAIN5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define TXRF1__LOCALTXGAIN5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define TXRF1__LOCALTXGAIN5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define TXRF1__LOCALTXGAIN5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field pdout2G */
#define TXRF1__PDOUT2G__SHIFT                                                17
#define TXRF1__PDOUT2G__WIDTH                                                 1
#define TXRF1__PDOUT2G__MASK                                        0x00020000U
#define TXRF1__PDOUT2G__READ(src)      (((u_int32_t)(src) & 0x00020000U) >> 17)
#define TXRF1__PDOUT2G__WRITE(src)     (((u_int32_t)(src) << 17) & 0x00020000U)
#define TXRF1__PDOUT2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define TXRF1__PDOUT2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define TXRF1__PDOUT2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define TXRF1__PDOUT2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field pdDR2G */
#define TXRF1__PDDR2G__SHIFT                                                 18
#define TXRF1__PDDR2G__WIDTH                                                  1
#define TXRF1__PDDR2G__MASK                                         0x00040000U
#define TXRF1__PDDR2G__READ(src)       (((u_int32_t)(src) & 0x00040000U) >> 18)
#define TXRF1__PDDR2G__WRITE(src)      (((u_int32_t)(src) << 18) & 0x00040000U)
#define TXRF1__PDDR2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define TXRF1__PDDR2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define TXRF1__PDDR2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define TXRF1__PDDR2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field pdmxr2G */
#define TXRF1__PDMXR2G__SHIFT                                                19
#define TXRF1__PDMXR2G__WIDTH                                                 1
#define TXRF1__PDMXR2G__MASK                                        0x00080000U
#define TXRF1__PDMXR2G__READ(src)      (((u_int32_t)(src) & 0x00080000U) >> 19)
#define TXRF1__PDMXR2G__WRITE(src)     (((u_int32_t)(src) << 19) & 0x00080000U)
#define TXRF1__PDMXR2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define TXRF1__PDMXR2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define TXRF1__PDMXR2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define TXRF1__PDMXR2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field pdlobuf2G */
#define TXRF1__PDLOBUF2G__SHIFT                                              20
#define TXRF1__PDLOBUF2G__WIDTH                                               1
#define TXRF1__PDLOBUF2G__MASK                                      0x00100000U
#define TXRF1__PDLOBUF2G__READ(src)    (((u_int32_t)(src) & 0x00100000U) >> 20)
#define TXRF1__PDLOBUF2G__WRITE(src)   (((u_int32_t)(src) << 20) & 0x00100000U)
#define TXRF1__PDLOBUF2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define TXRF1__PDLOBUF2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define TXRF1__PDLOBUF2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define TXRF1__PDLOBUF2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field pdlodiv2G */
#define TXRF1__PDLODIV2G__SHIFT                                              21
#define TXRF1__PDLODIV2G__WIDTH                                               1
#define TXRF1__PDLODIV2G__MASK                                      0x00200000U
#define TXRF1__PDLODIV2G__READ(src)    (((u_int32_t)(src) & 0x00200000U) >> 21)
#define TXRF1__PDLODIV2G__WRITE(src)   (((u_int32_t)(src) << 21) & 0x00200000U)
#define TXRF1__PDLODIV2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define TXRF1__PDLODIV2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define TXRF1__PDLODIV2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define TXRF1__PDLODIV2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field LObuf2Gforced */
#define TXRF1__LOBUF2GFORCED__SHIFT                                          22
#define TXRF1__LOBUF2GFORCED__WIDTH                                           1
#define TXRF1__LOBUF2GFORCED__MASK                                  0x00400000U
#define TXRF1__LOBUF2GFORCED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define TXRF1__LOBUF2GFORCED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define TXRF1__LOBUF2GFORCED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define TXRF1__LOBUF2GFORCED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define TXRF1__LOBUF2GFORCED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field LOdiv2Gforced */
#define TXRF1__LODIV2GFORCED__SHIFT                                          23
#define TXRF1__LODIV2GFORCED__WIDTH                                           1
#define TXRF1__LODIV2GFORCED__MASK                                  0x00800000U
#define TXRF1__LODIV2GFORCED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00800000U) >> 23)
#define TXRF1__LODIV2GFORCED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x00800000U)
#define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TXRF1__LODIV2GFORCED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TXRF1__LODIV2GFORCED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TXRF1__LODIV2GFORCED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field padrvgn2G */
#define TXRF1__PADRVGN2G__SHIFT                                              24
#define TXRF1__PADRVGN2G__WIDTH                                               7
#define TXRF1__PADRVGN2G__MASK                                      0x7f000000U
#define TXRF1__PADRVGN2G__READ(src)    (((u_int32_t)(src) & 0x7f000000U) >> 24)
#define TXRF1__PADRVGN2G__WRITE(src)   (((u_int32_t)(src) << 24) & 0x7f000000U)
#define TXRF1__PADRVGN2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define TXRF1__PADRVGN2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))

/* macros for field localtxgain2G */
#define TXRF1__LOCALTXGAIN2G__SHIFT                                          31
#define TXRF1__LOCALTXGAIN2G__WIDTH                                           1
#define TXRF1__LOCALTXGAIN2G__MASK                                  0x80000000U
#define TXRF1__LOCALTXGAIN2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define TXRF1__LOCALTXGAIN2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TXRF1__LOCALTXGAIN2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TXRF1__LOCALTXGAIN2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TXRF1__LOCALTXGAIN2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TXRF1__TYPE                                                   u_int32_t
#define TXRF1__READ                                                 0xffffffffU
#define TXRF1__WRITE                                                0xffffffffU

#endif /* __TXRF1_MACRO__ */


/* macros for radio65_reg_map.ch0_TXRF1 */
#define INST_RADIO65_REG_MAP__CH0_TXRF1__NUM                                  1

/* macros for BlueprintGlobalNameSpace::TXRF2 */
#ifndef __TXRF2_MACRO__
#define __TXRF2_MACRO__

/* macros for field d3b5G */
#define TXRF2__D3B5G__SHIFT                                                   0
#define TXRF2__D3B5G__WIDTH                                                   3
#define TXRF2__D3B5G__MASK                                          0x00000007U
#define TXRF2__D3B5G__READ(src)                  (u_int32_t)(src) & 0x00000007U
#define TXRF2__D3B5G__WRITE(src)               ((u_int32_t)(src) & 0x00000007U)
#define TXRF2__D3B5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define TXRF2__D3B5G__VERIFY(src)        (!(((u_int32_t)(src) & ~0x00000007U)))

/* macros for field d4b5G */
#define TXRF2__D4B5G__SHIFT                                                   3
#define TXRF2__D4B5G__WIDTH                                                   3
#define TXRF2__D4B5G__MASK                                          0x00000038U
#define TXRF2__D4B5G__READ(src)         (((u_int32_t)(src) & 0x00000038U) >> 3)
#define TXRF2__D4B5G__WRITE(src)        (((u_int32_t)(src) << 3) & 0x00000038U)
#define TXRF2__D4B5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000038U) | (((u_int32_t)(src) <<\
                    3) & 0x00000038U)
#define TXRF2__D4B5G__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000038U)))

/* macros for field ocas2G */
#define TXRF2__OCAS2G__SHIFT                                                  6
#define TXRF2__OCAS2G__WIDTH                                                  3
#define TXRF2__OCAS2G__MASK                                         0x000001c0U
#define TXRF2__OCAS2G__READ(src)        (((u_int32_t)(src) & 0x000001c0U) >> 6)
#define TXRF2__OCAS2G__WRITE(src)       (((u_int32_t)(src) << 6) & 0x000001c0U)
#define TXRF2__OCAS2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000001c0U)
#define TXRF2__OCAS2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000001c0U)))

/* macros for field dcas2G */
#define TXRF2__DCAS2G__SHIFT                                                  9
#define TXRF2__DCAS2G__WIDTH                                                  3
#define TXRF2__DCAS2G__MASK                                         0x00000e00U
#define TXRF2__DCAS2G__READ(src)        (((u_int32_t)(src) & 0x00000e00U) >> 9)
#define TXRF2__DCAS2G__WRITE(src)       (((u_int32_t)(src) << 9) & 0x00000e00U)
#define TXRF2__DCAS2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define TXRF2__DCAS2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field ob2G_paloff */
#define TXRF2__OB2G_PALOFF__SHIFT                                            12
#define TXRF2__OB2G_PALOFF__WIDTH                                             3
#define TXRF2__OB2G_PALOFF__MASK                                    0x00007000U
#define TXRF2__OB2G_PALOFF__READ(src)  (((u_int32_t)(src) & 0x00007000U) >> 12)
#define TXRF2__OB2G_PALOFF__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U)
#define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define TXRF2__OB2G_PALOFF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field ob2G_qam */
#define TXRF2__OB2G_QAM__SHIFT                                               15
#define TXRF2__OB2G_QAM__WIDTH                                                3
#define TXRF2__OB2G_QAM__MASK                                       0x00038000U
#define TXRF2__OB2G_QAM__READ(src)     (((u_int32_t)(src) & 0x00038000U) >> 15)
#define TXRF2__OB2G_QAM__WRITE(src)    (((u_int32_t)(src) << 15) & 0x00038000U)
#define TXRF2__OB2G_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define TXRF2__OB2G_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00038000U)))

/* macros for field ob2G_psk */
#define TXRF2__OB2G_PSK__SHIFT                                               18
#define TXRF2__OB2G_PSK__WIDTH                                                3
#define TXRF2__OB2G_PSK__MASK                                       0x001c0000U
#define TXRF2__OB2G_PSK__READ(src)     (((u_int32_t)(src) & 0x001c0000U) >> 18)
#define TXRF2__OB2G_PSK__WRITE(src)    (((u_int32_t)(src) << 18) & 0x001c0000U)
#define TXRF2__OB2G_PSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x001c0000U)
#define TXRF2__OB2G_PSK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x001c0000U)))

/* macros for field ob2G_cck */
#define TXRF2__OB2G_CCK__SHIFT                                               21
#define TXRF2__OB2G_CCK__WIDTH                                                3
#define TXRF2__OB2G_CCK__MASK                                       0x00e00000U
#define TXRF2__OB2G_CCK__READ(src)     (((u_int32_t)(src) & 0x00e00000U) >> 21)
#define TXRF2__OB2G_CCK__WRITE(src)    (((u_int32_t)(src) << 21) & 0x00e00000U)
#define TXRF2__OB2G_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x00e00000U)
#define TXRF2__OB2G_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00e00000U)))

/* macros for field db2G */
#define TXRF2__DB2G__SHIFT                                                   24
#define TXRF2__DB2G__WIDTH                                                    3
#define TXRF2__DB2G__MASK                                           0x07000000U
#define TXRF2__DB2G__READ(src)         (((u_int32_t)(src) & 0x07000000U) >> 24)
#define TXRF2__DB2G__WRITE(src)        (((u_int32_t)(src) << 24) & 0x07000000U)
#define TXRF2__DB2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((u_int32_t)(src) <<\
                    24) & 0x07000000U)
#define TXRF2__DB2G__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x07000000U)))

/* macros for field pdout5G */
#define TXRF2__PDOUT5G__SHIFT                                                27
#define TXRF2__PDOUT5G__WIDTH                                                 4
#define TXRF2__PDOUT5G__MASK                                        0x78000000U
#define TXRF2__PDOUT5G__READ(src)      (((u_int32_t)(src) & 0x78000000U) >> 27)
#define TXRF2__PDOUT5G__WRITE(src)     (((u_int32_t)(src) << 27) & 0x78000000U)
#define TXRF2__PDOUT5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define TXRF2__PDOUT5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))

/* macros for field pdmxr5G */
#define TXRF2__PDMXR5G__SHIFT                                                31
#define TXRF2__PDMXR5G__WIDTH                                                 1
#define TXRF2__PDMXR5G__MASK                                        0x80000000U
#define TXRF2__PDMXR5G__READ(src)      (((u_int32_t)(src) & 0x80000000U) >> 31)
#define TXRF2__PDMXR5G__WRITE(src)     (((u_int32_t)(src) << 31) & 0x80000000U)
#define TXRF2__PDMXR5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TXRF2__PDMXR5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TXRF2__PDMXR5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TXRF2__PDMXR5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TXRF2__TYPE                                                   u_int32_t
#define TXRF2__READ                                                 0xffffffffU
#define TXRF2__WRITE                                                0xffffffffU

#endif /* __TXRF2_MACRO__ */


/* macros for radio65_reg_map.ch0_TXRF2 */
#define INST_RADIO65_REG_MAP__CH0_TXRF2__NUM                                  1

/* macros for BlueprintGlobalNameSpace::TXRF3 */
#ifndef __TXRF3_MACRO__
#define __TXRF3_MACRO__

/* macros for field filtR2G */
#define TXRF3__FILTR2G__SHIFT                                                 0
#define TXRF3__FILTR2G__WIDTH                                                 2
#define TXRF3__FILTR2G__MASK                                        0x00000003U
#define TXRF3__FILTR2G__READ(src)                (u_int32_t)(src) & 0x00000003U
#define TXRF3__FILTR2G__WRITE(src)             ((u_int32_t)(src) & 0x00000003U)
#define TXRF3__FILTR2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define TXRF3__FILTR2G__VERIFY(src)      (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field pwdFB2_2G */
#define TXRF3__PWDFB2_2G__SHIFT                                               2
#define TXRF3__PWDFB2_2G__WIDTH                                               1
#define TXRF3__PWDFB2_2G__MASK                                      0x00000004U
#define TXRF3__PWDFB2_2G__READ(src)     (((u_int32_t)(src) & 0x00000004U) >> 2)
#define TXRF3__PWDFB2_2G__WRITE(src)    (((u_int32_t)(src) << 2) & 0x00000004U)
#define TXRF3__PWDFB2_2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define TXRF3__PWDFB2_2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define TXRF3__PWDFB2_2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TXRF3__PWDFB2_2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field pwdFB1_2G */
#define TXRF3__PWDFB1_2G__SHIFT                                               3
#define TXRF3__PWDFB1_2G__WIDTH                                               1
#define TXRF3__PWDFB1_2G__MASK                                      0x00000008U
#define TXRF3__PWDFB1_2G__READ(src)     (((u_int32_t)(src) & 0x00000008U) >> 3)
#define TXRF3__PWDFB1_2G__WRITE(src)    (((u_int32_t)(src) << 3) & 0x00000008U)
#define TXRF3__PWDFB1_2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define TXRF3__PWDFB1_2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define TXRF3__PWDFB1_2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TXRF3__PWDFB1_2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field pdFB2G */
#define TXRF3__PDFB2G__SHIFT                                                  4
#define TXRF3__PDFB2G__WIDTH                                                  1
#define TXRF3__PDFB2G__MASK                                         0x00000010U
#define TXRF3__PDFB2G__READ(src)        (((u_int32_t)(src) & 0x00000010U) >> 4)
#define TXRF3__PDFB2G__WRITE(src)       (((u_int32_t)(src) << 4) & 0x00000010U)
#define TXRF3__PDFB2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define TXRF3__PDFB2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define TXRF3__PDFB2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define TXRF3__PDFB2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field rdiv5G */
#define TXRF3__RDIV5G__SHIFT                                                  5
#define TXRF3__RDIV5G__WIDTH                                                  2
#define TXRF3__RDIV5G__MASK                                         0x00000060U
#define TXRF3__RDIV5G__READ(src)        (((u_int32_t)(src) & 0x00000060U) >> 5)
#define TXRF3__RDIV5G__WRITE(src)       (((u_int32_t)(src) << 5) & 0x00000060U)
#define TXRF3__RDIV5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000060U) | (((u_int32_t)(src) <<\
                    5) & 0x00000060U)
#define TXRF3__RDIV5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000060U)))

/* macros for field capdiv5G */
#define TXRF3__CAPDIV5G__SHIFT                                                7
#define TXRF3__CAPDIV5G__WIDTH                                                3
#define TXRF3__CAPDIV5G__MASK                                       0x00000380U
#define TXRF3__CAPDIV5G__READ(src)      (((u_int32_t)(src) & 0x00000380U) >> 7)
#define TXRF3__CAPDIV5G__WRITE(src)     (((u_int32_t)(src) << 7) & 0x00000380U)
#define TXRF3__CAPDIV5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000380U) | (((u_int32_t)(src) <<\
                    7) & 0x00000380U)
#define TXRF3__CAPDIV5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000380U)))

/* macros for field pdpredist5G */
#define TXRF3__PDPREDIST5G__SHIFT                                            10
#define TXRF3__PDPREDIST5G__WIDTH                                             1
#define TXRF3__PDPREDIST5G__MASK                                    0x00000400U
#define TXRF3__PDPREDIST5G__READ(src)  (((u_int32_t)(src) & 0x00000400U) >> 10)
#define TXRF3__PDPREDIST5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
#define TXRF3__PDPREDIST5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define TXRF3__PDPREDIST5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define TXRF3__PDPREDIST5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define TXRF3__PDPREDIST5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field rdiv2G */
#define TXRF3__RDIV2G__SHIFT                                                 11
#define TXRF3__RDIV2G__WIDTH                                                  2
#define TXRF3__RDIV2G__MASK                                         0x00001800U
#define TXRF3__RDIV2G__READ(src)       (((u_int32_t)(src) & 0x00001800U) >> 11)
#define TXRF3__RDIV2G__WRITE(src)      (((u_int32_t)(src) << 11) & 0x00001800U)
#define TXRF3__RDIV2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001800U) | (((u_int32_t)(src) <<\
                    11) & 0x00001800U)
#define TXRF3__RDIV2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00001800U)))

/* macros for field pdpredist2G */
#define TXRF3__PDPREDIST2G__SHIFT                                            13
#define TXRF3__PDPREDIST2G__WIDTH                                             1
#define TXRF3__PDPREDIST2G__MASK                                    0x00002000U
#define TXRF3__PDPREDIST2G__READ(src)  (((u_int32_t)(src) & 0x00002000U) >> 13)
#define TXRF3__PDPREDIST2G__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
#define TXRF3__PDPREDIST2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TXRF3__PDPREDIST2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TXRF3__PDPREDIST2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TXRF3__PDPREDIST2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field ocas5G */
#define TXRF3__OCAS5G__SHIFT                                                 14
#define TXRF3__OCAS5G__WIDTH                                                  3
#define TXRF3__OCAS5G__MASK                                         0x0001c000U
#define TXRF3__OCAS5G__READ(src)       (((u_int32_t)(src) & 0x0001c000U) >> 14)
#define TXRF3__OCAS5G__WRITE(src)      (((u_int32_t)(src) << 14) & 0x0001c000U)
#define TXRF3__OCAS5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define TXRF3__OCAS5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field d2cas5G */
#define TXRF3__D2CAS5G__SHIFT                                                17
#define TXRF3__D2CAS5G__WIDTH                                                 3
#define TXRF3__D2CAS5G__MASK                                        0x000e0000U
#define TXRF3__D2CAS5G__READ(src)      (((u_int32_t)(src) & 0x000e0000U) >> 17)
#define TXRF3__D2CAS5G__WRITE(src)     (((u_int32_t)(src) << 17) & 0x000e0000U)
#define TXRF3__D2CAS5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define TXRF3__D2CAS5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field d3cas5G */
#define TXRF3__D3CAS5G__SHIFT                                                20
#define TXRF3__D3CAS5G__WIDTH                                                 3
#define TXRF3__D3CAS5G__MASK                                        0x00700000U
#define TXRF3__D3CAS5G__READ(src)      (((u_int32_t)(src) & 0x00700000U) >> 20)
#define TXRF3__D3CAS5G__WRITE(src)     (((u_int32_t)(src) << 20) & 0x00700000U)
#define TXRF3__D3CAS5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define TXRF3__D3CAS5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field d4cas5G */
#define TXRF3__D4CAS5G__SHIFT                                                23
#define TXRF3__D4CAS5G__WIDTH                                                 3
#define TXRF3__D4CAS5G__MASK                                        0x03800000U
#define TXRF3__D4CAS5G__READ(src)      (((u_int32_t)(src) & 0x03800000U) >> 23)
#define TXRF3__D4CAS5G__WRITE(src)     (((u_int32_t)(src) << 23) & 0x03800000U)
#define TXRF3__D4CAS5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define TXRF3__D4CAS5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field ob5G */
#define TXRF3__OB5G__SHIFT                                                   26
#define TXRF3__OB5G__WIDTH                                                    3
#define TXRF3__OB5G__MASK                                           0x1c000000U
#define TXRF3__OB5G__READ(src)         (((u_int32_t)(src) & 0x1c000000U) >> 26)
#define TXRF3__OB5G__WRITE(src)        (((u_int32_t)(src) << 26) & 0x1c000000U)
#define TXRF3__OB5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define TXRF3__OB5G__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x1c000000U)))

/* macros for field d2b5G */
#define TXRF3__D2B5G__SHIFT                                                  29
#define TXRF3__D2B5G__WIDTH                                                   3
#define TXRF3__D2B5G__MASK                                          0xe0000000U
#define TXRF3__D2B5G__READ(src)        (((u_int32_t)(src) & 0xe0000000U) >> 29)
#define TXRF3__D2B5G__WRITE(src)       (((u_int32_t)(src) << 29) & 0xe0000000U)
#define TXRF3__D2B5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define TXRF3__D2B5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define TXRF3__TYPE                                                   u_int32_t
#define TXRF3__READ                                                 0xffffffffU
#define TXRF3__WRITE                                                0xffffffffU

#endif /* __TXRF3_MACRO__ */


/* macros for radio65_reg_map.ch0_TXRF3 */
#define INST_RADIO65_REG_MAP__CH0_TXRF3__NUM                                  1

/* macros for BlueprintGlobalNameSpace::TXRF4 */
#ifndef __TXRF4_MACRO__
#define __TXRF4_MACRO__

/* macros for field pk1b2G_cck */
#define TXRF4__PK1B2G_CCK__SHIFT                                              0
#define TXRF4__PK1B2G_CCK__WIDTH                                              2
#define TXRF4__PK1B2G_CCK__MASK                                     0x00000003U
#define TXRF4__PK1B2G_CCK__READ(src)             (u_int32_t)(src) & 0x00000003U
#define TXRF4__PK1B2G_CCK__WRITE(src)          ((u_int32_t)(src) & 0x00000003U)
#define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define TXRF4__PK1B2G_CCK__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field miob2G_qam */
#define TXRF4__MIOB2G_QAM__SHIFT                                              2
#define TXRF4__MIOB2G_QAM__WIDTH                                              3
#define TXRF4__MIOB2G_QAM__MASK                                     0x0000001cU
#define TXRF4__MIOB2G_QAM__READ(src)    (((u_int32_t)(src) & 0x0000001cU) >> 2)
#define TXRF4__MIOB2G_QAM__WRITE(src)   (((u_int32_t)(src) << 2) & 0x0000001cU)
#define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define TXRF4__MIOB2G_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))

/* macros for field miob2G_psk */
#define TXRF4__MIOB2G_PSK__SHIFT                                              5
#define TXRF4__MIOB2G_PSK__WIDTH                                              3
#define TXRF4__MIOB2G_PSK__MASK                                     0x000000e0U
#define TXRF4__MIOB2G_PSK__READ(src)    (((u_int32_t)(src) & 0x000000e0U) >> 5)
#define TXRF4__MIOB2G_PSK__WRITE(src)   (((u_int32_t)(src) << 5) & 0x000000e0U)
#define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define TXRF4__MIOB2G_PSK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))

/* macros for field miob2G_cck */
#define TXRF4__MIOB2G_CCK__SHIFT                                              8
#define TXRF4__MIOB2G_CCK__WIDTH                                              3
#define TXRF4__MIOB2G_CCK__MASK                                     0x00000700U
#define TXRF4__MIOB2G_CCK__READ(src)    (((u_int32_t)(src) & 0x00000700U) >> 8)
#define TXRF4__MIOB2G_CCK__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000700U)
#define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define TXRF4__MIOB2G_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field comp2G_qam */
#define TXRF4__COMP2G_QAM__SHIFT                                             11
#define TXRF4__COMP2G_QAM__WIDTH                                              3
#define TXRF4__COMP2G_QAM__MASK                                     0x00003800U
#define TXRF4__COMP2G_QAM__READ(src)   (((u_int32_t)(src) & 0x00003800U) >> 11)
#define TXRF4__COMP2G_QAM__WRITE(src)  (((u_int32_t)(src) << 11) & 0x00003800U)
#define TXRF4__COMP2G_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define TXRF4__COMP2G_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field comp2G_psk */
#define TXRF4__COMP2G_PSK__SHIFT                                             14
#define TXRF4__COMP2G_PSK__WIDTH                                              3
#define TXRF4__COMP2G_PSK__MASK                                     0x0001c000U
#define TXRF4__COMP2G_PSK__READ(src)   (((u_int32_t)(src) & 0x0001c000U) >> 14)
#define TXRF4__COMP2G_PSK__WRITE(src)  (((u_int32_t)(src) << 14) & 0x0001c000U)
#define TXRF4__COMP2G_PSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define TXRF4__COMP2G_PSK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field comp2G_cck */
#define TXRF4__COMP2G_CCK__SHIFT                                             17
#define TXRF4__COMP2G_CCK__WIDTH                                              3
#define TXRF4__COMP2G_CCK__MASK                                     0x000e0000U
#define TXRF4__COMP2G_CCK__READ(src)   (((u_int32_t)(src) & 0x000e0000U) >> 17)
#define TXRF4__COMP2G_CCK__WRITE(src)  (((u_int32_t)(src) << 17) & 0x000e0000U)
#define TXRF4__COMP2G_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define TXRF4__COMP2G_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field amp2b2G_qam */
#define TXRF4__AMP2B2G_QAM__SHIFT                                            20
#define TXRF4__AMP2B2G_QAM__WIDTH                                             3
#define TXRF4__AMP2B2G_QAM__MASK                                    0x00700000U
#define TXRF4__AMP2B2G_QAM__READ(src)  (((u_int32_t)(src) & 0x00700000U) >> 20)
#define TXRF4__AMP2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
#define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define TXRF4__AMP2B2G_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field amp2b2G_psk */
#define TXRF4__AMP2B2G_PSK__SHIFT                                            23
#define TXRF4__AMP2B2G_PSK__WIDTH                                             3
#define TXRF4__AMP2B2G_PSK__MASK                                    0x03800000U
#define TXRF4__AMP2B2G_PSK__READ(src)  (((u_int32_t)(src) & 0x03800000U) >> 23)
#define TXRF4__AMP2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
#define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define TXRF4__AMP2B2G_PSK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field amp2b2G_cck */
#define TXRF4__AMP2B2G_CCK__SHIFT                                            26
#define TXRF4__AMP2B2G_CCK__WIDTH                                             3
#define TXRF4__AMP2B2G_CCK__MASK                                    0x1c000000U
#define TXRF4__AMP2B2G_CCK__READ(src)  (((u_int32_t)(src) & 0x1c000000U) >> 26)
#define TXRF4__AMP2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
#define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define TXRF4__AMP2B2G_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field amp2cas2G */
#define TXRF4__AMP2CAS2G__SHIFT                                              29
#define TXRF4__AMP2CAS2G__WIDTH                                               3
#define TXRF4__AMP2CAS2G__MASK                                      0xe0000000U
#define TXRF4__AMP2CAS2G__READ(src)    (((u_int32_t)(src) & 0xe0000000U) >> 29)
#define TXRF4__AMP2CAS2G__WRITE(src)   (((u_int32_t)(src) << 29) & 0xe0000000U)
#define TXRF4__AMP2CAS2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define TXRF4__AMP2CAS2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define TXRF4__TYPE                                                   u_int32_t
#define TXRF4__READ                                                 0xffffffffU
#define TXRF4__WRITE                                                0xffffffffU

#endif /* __TXRF4_MACRO__ */


/* macros for radio65_reg_map.ch0_TXRF4 */
#define INST_RADIO65_REG_MAP__CH0_TXRF4__NUM                                  1

/* macros for BlueprintGlobalNameSpace::TXRF5 */
#ifndef __TXRF5_MACRO__
#define __TXRF5_MACRO__

/* macros for field txmodPALonly */
#define TXRF5__TXMODPALONLY__SHIFT                                            0
#define TXRF5__TXMODPALONLY__WIDTH                                            1
#define TXRF5__TXMODPALONLY__MASK                                   0x00000001U
#define TXRF5__TXMODPALONLY__READ(src)           (u_int32_t)(src) & 0x00000001U
#define TXRF5__TXMODPALONLY__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
#define TXRF5__TXMODPALONLY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TXRF5__TXMODPALONLY__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
#define TXRF5__TXMODPALONLY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXRF5__TXMODPALONLY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field PAL_locked */
#define TXRF5__PAL_LOCKED__SHIFT                                              1
#define TXRF5__PAL_LOCKED__WIDTH                                              1
#define TXRF5__PAL_LOCKED__MASK                                     0x00000002U
#define TXRF5__PAL_LOCKED__READ(src)    (((u_int32_t)(src) & 0x00000002U) >> 1)
#define TXRF5__PAL_LOCKED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TXRF5__PAL_LOCKED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field fbHi2G */
#define TXRF5__FBHI2G__SHIFT                                                  2
#define TXRF5__FBHI2G__WIDTH                                                  1
#define TXRF5__FBHI2G__MASK                                         0x00000004U
#define TXRF5__FBHI2G__READ(src)        (((u_int32_t)(src) & 0x00000004U) >> 2)
#define TXRF5__FBHI2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TXRF5__FBHI2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field fbLo2G */
#define TXRF5__FBLO2G__SHIFT                                                  3
#define TXRF5__FBLO2G__WIDTH                                                  1
#define TXRF5__FBLO2G__MASK                                         0x00000008U
#define TXRF5__FBLO2G__READ(src)        (((u_int32_t)(src) & 0x00000008U) >> 3)
#define TXRF5__FBLO2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TXRF5__FBLO2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field nopalgain2G */
#define TXRF5__NOPALGAIN2G__SHIFT                                             4
#define TXRF5__NOPALGAIN2G__WIDTH                                             1
#define TXRF5__NOPALGAIN2G__MASK                                    0x00000010U
#define TXRF5__NOPALGAIN2G__READ(src)   (((u_int32_t)(src) & 0x00000010U) >> 4)
#define TXRF5__NOPALGAIN2G__WRITE(src)  (((u_int32_t)(src) << 4) & 0x00000010U)
#define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define TXRF5__NOPALGAIN2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define TXRF5__NOPALGAIN2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define TXRF5__NOPALGAIN2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field enPAcal2G */
#define TXRF5__ENPACAL2G__SHIFT                                               5
#define TXRF5__ENPACAL2G__WIDTH                                               1
#define TXRF5__ENPACAL2G__MASK                                      0x00000020U
#define TXRF5__ENPACAL2G__READ(src)     (((u_int32_t)(src) & 0x00000020U) >> 5)
#define TXRF5__ENPACAL2G__WRITE(src)    (((u_int32_t)(src) << 5) & 0x00000020U)
#define TXRF5__ENPACAL2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define TXRF5__ENPACAL2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define TXRF5__ENPACAL2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define TXRF5__ENPACAL2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field offset2G */
#define TXRF5__OFFSET2G__SHIFT                                                6
#define TXRF5__OFFSET2G__WIDTH                                                7
#define TXRF5__OFFSET2G__MASK                                       0x00001fc0U
#define TXRF5__OFFSET2G__READ(src)      (((u_int32_t)(src) & 0x00001fc0U) >> 6)
#define TXRF5__OFFSET2G__WRITE(src)     (((u_int32_t)(src) << 6) & 0x00001fc0U)
#define TXRF5__OFFSET2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00001fc0U)
#define TXRF5__OFFSET2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00001fc0U)))

/* macros for field enoffsetcal2G */
#define TXRF5__ENOFFSETCAL2G__SHIFT                                          13
#define TXRF5__ENOFFSETCAL2G__WIDTH                                           1
#define TXRF5__ENOFFSETCAL2G__MASK                                  0x00002000U
#define TXRF5__ENOFFSETCAL2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define TXRF5__ENOFFSETCAL2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define TXRF5__ENOFFSETCAL2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define TXRF5__ENOFFSETCAL2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define TXRF5__ENOFFSETCAL2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field refHi2G */
#define TXRF5__REFHI2G__SHIFT                                                14
#define TXRF5__REFHI2G__WIDTH                                                 3
#define TXRF5__REFHI2G__MASK                                        0x0001c000U
#define TXRF5__REFHI2G__READ(src)      (((u_int32_t)(src) & 0x0001c000U) >> 14)
#define TXRF5__REFHI2G__WRITE(src)     (((u_int32_t)(src) << 14) & 0x0001c000U)
#define TXRF5__REFHI2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define TXRF5__REFHI2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field refLo2G */
#define TXRF5__REFLO2G__SHIFT                                                17
#define TXRF5__REFLO2G__WIDTH                                                 3
#define TXRF5__REFLO2G__MASK                                        0x000e0000U
#define TXRF5__REFLO2G__READ(src)      (((u_int32_t)(src) & 0x000e0000U) >> 17)
#define TXRF5__REFLO2G__WRITE(src)     (((u_int32_t)(src) << 17) & 0x000e0000U)
#define TXRF5__REFLO2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define TXRF5__REFLO2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field palclamp2G */
#define TXRF5__PALCLAMP2G__SHIFT                                             20
#define TXRF5__PALCLAMP2G__WIDTH                                              2
#define TXRF5__PALCLAMP2G__MASK                                     0x00300000U
#define TXRF5__PALCLAMP2G__READ(src)   (((u_int32_t)(src) & 0x00300000U) >> 20)
#define TXRF5__PALCLAMP2G__WRITE(src)  (((u_int32_t)(src) << 20) & 0x00300000U)
#define TXRF5__PALCLAMP2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00300000U) | (((u_int32_t)(src) <<\
                    20) & 0x00300000U)
#define TXRF5__PALCLAMP2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00300000U)))

/* macros for field pk2b2G_qam */
#define TXRF5__PK2B2G_QAM__SHIFT                                             22
#define TXRF5__PK2B2G_QAM__WIDTH                                              2
#define TXRF5__PK2B2G_QAM__MASK                                     0x00c00000U
#define TXRF5__PK2B2G_QAM__READ(src)   (((u_int32_t)(src) & 0x00c00000U) >> 22)
#define TXRF5__PK2B2G_QAM__WRITE(src)  (((u_int32_t)(src) << 22) & 0x00c00000U)
#define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x00c00000U)
#define TXRF5__PK2B2G_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00c00000U)))

/* macros for field pk2b2G_psk */
#define TXRF5__PK2B2G_PSK__SHIFT                                             24
#define TXRF5__PK2B2G_PSK__WIDTH                                              2
#define TXRF5__PK2B2G_PSK__MASK                                     0x03000000U
#define TXRF5__PK2B2G_PSK__READ(src)   (((u_int32_t)(src) & 0x03000000U) >> 24)
#define TXRF5__PK2B2G_PSK__WRITE(src)  (((u_int32_t)(src) << 24) & 0x03000000U)
#define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define TXRF5__PK2B2G_PSK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field pk2b2G_cck */
#define TXRF5__PK2B2G_CCK__SHIFT                                             26
#define TXRF5__PK2B2G_CCK__WIDTH                                              2
#define TXRF5__PK2B2G_CCK__MASK                                     0x0c000000U
#define TXRF5__PK2B2G_CCK__READ(src)   (((u_int32_t)(src) & 0x0c000000U) >> 26)
#define TXRF5__PK2B2G_CCK__WRITE(src)  (((u_int32_t)(src) << 26) & 0x0c000000U)
#define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x0c000000U)
#define TXRF5__PK2B2G_CCK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x0c000000U)))

/* macros for field pk1b2G_qam */
#define TXRF5__PK1B2G_QAM__SHIFT                                             28
#define TXRF5__PK1B2G_QAM__WIDTH                                              2
#define TXRF5__PK1B2G_QAM__MASK                                     0x30000000U
#define TXRF5__PK1B2G_QAM__READ(src)   (((u_int32_t)(src) & 0x30000000U) >> 28)
#define TXRF5__PK1B2G_QAM__WRITE(src)  (((u_int32_t)(src) << 28) & 0x30000000U)
#define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((u_int32_t)(src) <<\
                    28) & 0x30000000U)
#define TXRF5__PK1B2G_QAM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field pk1b2G_psk */
#define TXRF5__PK1B2G_PSK__SHIFT                                             30
#define TXRF5__PK1B2G_PSK__WIDTH                                              2
#define TXRF5__PK1B2G_PSK__MASK                                     0xc0000000U
#define TXRF5__PK1B2G_PSK__READ(src)   (((u_int32_t)(src) & 0xc0000000U) >> 30)
#define TXRF5__PK1B2G_PSK__WRITE(src)  (((u_int32_t)(src) << 30) & 0xc0000000U)
#define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define TXRF5__PK1B2G_PSK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define TXRF5__TYPE                                                   u_int32_t
#define TXRF5__READ                                                 0xffffffffU
#define TXRF5__WRITE                                                0xffffffffU

#endif /* __TXRF5_MACRO__ */


/* macros for radio65_reg_map.ch0_TXRF5 */
#define INST_RADIO65_REG_MAP__CH0_TXRF5__NUM                                  1

/* macros for BlueprintGlobalNameSpace::TXRF6 */
#ifndef __TXRF6_MACRO__
#define __TXRF6_MACRO__

/* macros for field palclkgate2G */
#define TXRF6__PALCLKGATE2G__SHIFT                                            0
#define TXRF6__PALCLKGATE2G__WIDTH                                            1
#define TXRF6__PALCLKGATE2G__MASK                                   0x00000001U
#define TXRF6__PALCLKGATE2G__READ(src)           (u_int32_t)(src) & 0x00000001U
#define TXRF6__PALCLKGATE2G__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
#define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TXRF6__PALCLKGATE2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
#define TXRF6__PALCLKGATE2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TXRF6__PALCLKGATE2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field palfluctcount2G */
#define TXRF6__PALFLUCTCOUNT2G__SHIFT                                         1
#define TXRF6__PALFLUCTCOUNT2G__WIDTH                                         8
#define TXRF6__PALFLUCTCOUNT2G__MASK                                0x000001feU
#define TXRF6__PALFLUCTCOUNT2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001feU) >> 1)
#define TXRF6__PALFLUCTCOUNT2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x000001feU)
#define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001feU) | (((u_int32_t)(src) <<\
                    1) & 0x000001feU)
#define TXRF6__PALFLUCTCOUNT2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000001feU)))

/* macros for field palfluctgain2G */
#define TXRF6__PALFLUCTGAIN2G__SHIFT                                          9
#define TXRF6__PALFLUCTGAIN2G__WIDTH                                          2
#define TXRF6__PALFLUCTGAIN2G__MASK                                 0x00000600U
#define TXRF6__PALFLUCTGAIN2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000600U) >> 9)
#define TXRF6__PALFLUCTGAIN2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000600U)
#define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000600U) | (((u_int32_t)(src) <<\
                    9) & 0x00000600U)
#define TXRF6__PALFLUCTGAIN2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000600U)))

/* macros for field palnofluct2G */
#define TXRF6__PALNOFLUCT2G__SHIFT                                           11
#define TXRF6__PALNOFLUCT2G__WIDTH                                            1
#define TXRF6__PALNOFLUCT2G__MASK                                   0x00000800U
#define TXRF6__PALNOFLUCT2G__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
#define TXRF6__PALNOFLUCT2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define TXRF6__PALNOFLUCT2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define TXRF6__PALNOFLUCT2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define TXRF6__PALNOFLUCT2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field gainstep2G */
#define TXRF6__GAINSTEP2G__SHIFT                                             12
#define TXRF6__GAINSTEP2G__WIDTH                                              3
#define TXRF6__GAINSTEP2G__MASK                                     0x00007000U
#define TXRF6__GAINSTEP2G__READ(src)   (((u_int32_t)(src) & 0x00007000U) >> 12)
#define TXRF6__GAINSTEP2G__WRITE(src)  (((u_int32_t)(src) << 12) & 0x00007000U)
#define TXRF6__GAINSTEP2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define TXRF6__GAINSTEP2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field use_gain_delta2G */
#define TXRF6__USE_GAIN_DELTA2G__SHIFT                                       15
#define TXRF6__USE_GAIN_DELTA2G__WIDTH                                        1
#define TXRF6__USE_GAIN_DELTA2G__MASK                               0x00008000U
#define TXRF6__USE_GAIN_DELTA2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define TXRF6__USE_GAIN_DELTA2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define TXRF6__USE_GAIN_DELTA2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define TXRF6__USE_GAIN_DELTA2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define TXRF6__USE_GAIN_DELTA2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field capdiv_I2G */
#define TXRF6__CAPDIV_I2G__SHIFT                                             16
#define TXRF6__CAPDIV_I2G__WIDTH                                              4
#define TXRF6__CAPDIV_I2G__MASK                                     0x000f0000U
#define TXRF6__CAPDIV_I2G__READ(src)   (((u_int32_t)(src) & 0x000f0000U) >> 16)
#define TXRF6__CAPDIV_I2G__WRITE(src)  (((u_int32_t)(src) << 16) & 0x000f0000U)
#define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define TXRF6__CAPDIV_I2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field padrvgn_index_I2G */
#define TXRF6__PADRVGN_INDEX_I2G__SHIFT                                      20
#define TXRF6__PADRVGN_INDEX_I2G__WIDTH                                       4
#define TXRF6__PADRVGN_INDEX_I2G__MASK                              0x00f00000U
#define TXRF6__PADRVGN_INDEX_I2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00f00000U) >> 20)
#define TXRF6__PADRVGN_INDEX_I2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00f00000U)
#define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((u_int32_t)(src) <<\
                    20) & 0x00f00000U)
#define TXRF6__PADRVGN_INDEX_I2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field vcmondelay2G */
#define TXRF6__VCMONDELAY2G__SHIFT                                           24
#define TXRF6__VCMONDELAY2G__WIDTH                                            3
#define TXRF6__VCMONDELAY2G__MASK                                   0x07000000U
#define TXRF6__VCMONDELAY2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24)
#define TXRF6__VCMONDELAY2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x07000000U)
#define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((u_int32_t)(src) <<\
                    24) & 0x07000000U)
#define TXRF6__VCMONDELAY2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x07000000U)))

/* macros for field capdiv2G */
#define TXRF6__CAPDIV2G__SHIFT                                               27
#define TXRF6__CAPDIV2G__WIDTH                                                4
#define TXRF6__CAPDIV2G__MASK                                       0x78000000U
#define TXRF6__CAPDIV2G__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
#define TXRF6__CAPDIV2G__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
#define TXRF6__CAPDIV2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define TXRF6__CAPDIV2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))

/* macros for field capdiv2Govr */
#define TXRF6__CAPDIV2GOVR__SHIFT                                            31
#define TXRF6__CAPDIV2GOVR__WIDTH                                             1
#define TXRF6__CAPDIV2GOVR__MASK                                    0x80000000U
#define TXRF6__CAPDIV2GOVR__READ(src)  (((u_int32_t)(src) & 0x80000000U) >> 31)
#define TXRF6__CAPDIV2GOVR__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
#define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TXRF6__CAPDIV2GOVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TXRF6__CAPDIV2GOVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TXRF6__CAPDIV2GOVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TXRF6__TYPE                                                   u_int32_t
#define TXRF6__READ                                                 0xffffffffU
#define TXRF6__WRITE                                                0xffffffffU

#endif /* __TXRF6_MACRO__ */


/* macros for radio65_reg_map.ch0_TXRF6 */
#define INST_RADIO65_REG_MAP__CH0_TXRF6__NUM                                  1

/* macros for BlueprintGlobalNameSpace::SYNTH1 */
#ifndef __SYNTH1_MACRO__
#define __SYNTH1_MACRO__

/* macros for field SEL_VCMONABUS */
#define SYNTH1__SEL_VCMONABUS__SHIFT                                          0
#define SYNTH1__SEL_VCMONABUS__WIDTH                                          3
#define SYNTH1__SEL_VCMONABUS__MASK                                 0x00000007U
#define SYNTH1__SEL_VCMONABUS__READ(src)         (u_int32_t)(src) & 0x00000007U
#define SYNTH1__SEL_VCMONABUS__WRITE(src)      ((u_int32_t)(src) & 0x00000007U)
#define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define SYNTH1__SEL_VCMONABUS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000007U)))

/* macros for field SEL_VCOABUS */
#define SYNTH1__SEL_VCOABUS__SHIFT                                            3
#define SYNTH1__SEL_VCOABUS__WIDTH                                            3
#define SYNTH1__SEL_VCOABUS__MASK                                   0x00000038U
#define SYNTH1__SEL_VCOABUS__READ(src)  (((u_int32_t)(src) & 0x00000038U) >> 3)
#define SYNTH1__SEL_VCOABUS__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U)
#define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000038U) | (((u_int32_t)(src) <<\
                    3) & 0x00000038U)
#define SYNTH1__SEL_VCOABUS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000038U)))

/* macros for field MONITOR_SYNTHLOCKVCOK */
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SHIFT                                  6
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WIDTH                                  1
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MASK                         0x00000040U
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field MONITOR_VC2LOW */
#define SYNTH1__MONITOR_VC2LOW__SHIFT                                         7
#define SYNTH1__MONITOR_VC2LOW__WIDTH                                         1
#define SYNTH1__MONITOR_VC2LOW__MASK                                0x00000080U
#define SYNTH1__MONITOR_VC2LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define SYNTH1__MONITOR_VC2LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define SYNTH1__MONITOR_VC2LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define SYNTH1__MONITOR_VC2LOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define SYNTH1__MONITOR_VC2LOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field MONITOR_VC2HIGH */
#define SYNTH1__MONITOR_VC2HIGH__SHIFT                                        8
#define SYNTH1__MONITOR_VC2HIGH__WIDTH                                        1
#define SYNTH1__MONITOR_VC2HIGH__MASK                               0x00000100U
#define SYNTH1__MONITOR_VC2HIGH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define SYNTH1__MONITOR_VC2HIGH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define SYNTH1__MONITOR_VC2HIGH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define SYNTH1__MONITOR_VC2HIGH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field MONITOR_FB_DIV2 */
#define SYNTH1__MONITOR_FB_DIV2__SHIFT                                        9
#define SYNTH1__MONITOR_FB_DIV2__WIDTH                                        1
#define SYNTH1__MONITOR_FB_DIV2__MASK                               0x00000200U
#define SYNTH1__MONITOR_FB_DIV2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define SYNTH1__MONITOR_FB_DIV2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define SYNTH1__MONITOR_FB_DIV2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define SYNTH1__MONITOR_FB_DIV2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field MONITOR_REF */
#define SYNTH1__MONITOR_REF__SHIFT                                           10
#define SYNTH1__MONITOR_REF__WIDTH                                            1
#define SYNTH1__MONITOR_REF__MASK                                   0x00000400U
#define SYNTH1__MONITOR_REF__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
#define SYNTH1__MONITOR_REF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define SYNTH1__MONITOR_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define SYNTH1__MONITOR_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define SYNTH1__MONITOR_REF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define SYNTH1__MONITOR_REF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field MONITOR_FB */
#define SYNTH1__MONITOR_FB__SHIFT                                            11
#define SYNTH1__MONITOR_FB__WIDTH                                             1
#define SYNTH1__MONITOR_FB__MASK                                    0x00000800U
#define SYNTH1__MONITOR_FB__READ(src)  (((u_int32_t)(src) & 0x00000800U) >> 11)
#define SYNTH1__MONITOR_FB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
#define SYNTH1__MONITOR_FB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define SYNTH1__MONITOR_FB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define SYNTH1__MONITOR_FB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define SYNTH1__MONITOR_FB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field SEVENBITVCOCAP */
#define SYNTH1__SEVENBITVCOCAP__SHIFT                                        12
#define SYNTH1__SEVENBITVCOCAP__WIDTH                                         1
#define SYNTH1__SEVENBITVCOCAP__MASK                                0x00001000U
#define SYNTH1__SEVENBITVCOCAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define SYNTH1__SEVENBITVCOCAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define SYNTH1__SEVENBITVCOCAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define SYNTH1__SEVENBITVCOCAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define SYNTH1__SEVENBITVCOCAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field PWUP_PD */
#define SYNTH1__PWUP_PD__SHIFT                                               13
#define SYNTH1__PWUP_PD__WIDTH                                                3
#define SYNTH1__PWUP_PD__MASK                                       0x0000e000U
#define SYNTH1__PWUP_PD__READ(src)     (((u_int32_t)(src) & 0x0000e000U) >> 13)
#define SYNTH1__PWUP_PD__WRITE(src)    (((u_int32_t)(src) << 13) & 0x0000e000U)
#define SYNTH1__PWUP_PD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0000e000U)
#define SYNTH1__PWUP_PD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0000e000U)))

/* macros for field PWD_VCOBUF */
#define SYNTH1__PWD_VCOBUF__SHIFT                                            16
#define SYNTH1__PWD_VCOBUF__WIDTH                                             1
#define SYNTH1__PWD_VCOBUF__MASK                                    0x00010000U
#define SYNTH1__PWD_VCOBUF__READ(src)  (((u_int32_t)(src) & 0x00010000U) >> 16)
#define SYNTH1__PWD_VCOBUF__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U)
#define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define SYNTH1__PWD_VCOBUF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define SYNTH1__PWD_VCOBUF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define SYNTH1__PWD_VCOBUF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field VCOBUFGAIN */
#define SYNTH1__VCOBUFGAIN__SHIFT                                            17
#define SYNTH1__VCOBUFGAIN__WIDTH                                             2
#define SYNTH1__VCOBUFGAIN__MASK                                    0x00060000U
#define SYNTH1__VCOBUFGAIN__READ(src)  (((u_int32_t)(src) & 0x00060000U) >> 17)
#define SYNTH1__VCOBUFGAIN__WRITE(src) (((u_int32_t)(src) << 17) & 0x00060000U)
#define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00060000U) | (((u_int32_t)(src) <<\
                    17) & 0x00060000U)
#define SYNTH1__VCOBUFGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00060000U)))

/* macros for field VCOREGLEVEL */
#define SYNTH1__VCOREGLEVEL__SHIFT                                           19
#define SYNTH1__VCOREGLEVEL__WIDTH                                            2
#define SYNTH1__VCOREGLEVEL__MASK                                   0x00180000U
#define SYNTH1__VCOREGLEVEL__READ(src) (((u_int32_t)(src) & 0x00180000U) >> 19)
#define SYNTH1__VCOREGLEVEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00180000U)
#define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00180000U) | (((u_int32_t)(src) <<\
                    19) & 0x00180000U)
#define SYNTH1__VCOREGLEVEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00180000U)))

/* macros for field VCOREGBYPASS */
#define SYNTH1__VCOREGBYPASS__SHIFT                                          21
#define SYNTH1__VCOREGBYPASS__WIDTH                                           1
#define SYNTH1__VCOREGBYPASS__MASK                                  0x00200000U
#define SYNTH1__VCOREGBYPASS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define SYNTH1__VCOREGBYPASS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define SYNTH1__VCOREGBYPASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define SYNTH1__VCOREGBYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define SYNTH1__VCOREGBYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field PWUP_LOREF */
#define SYNTH1__PWUP_LOREF__SHIFT                                            22
#define SYNTH1__PWUP_LOREF__WIDTH                                             1
#define SYNTH1__PWUP_LOREF__MASK                                    0x00400000U
#define SYNTH1__PWUP_LOREF__READ(src)  (((u_int32_t)(src) & 0x00400000U) >> 22)
#define SYNTH1__PWUP_LOREF__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U)
#define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define SYNTH1__PWUP_LOREF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define SYNTH1__PWUP_LOREF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define SYNTH1__PWUP_LOREF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field PWD_LOMIX */
#define SYNTH1__PWD_LOMIX__SHIFT                                             23
#define SYNTH1__PWD_LOMIX__WIDTH                                              1
#define SYNTH1__PWD_LOMIX__MASK                                     0x00800000U
#define SYNTH1__PWD_LOMIX__READ(src)   (((u_int32_t)(src) & 0x00800000U) >> 23)
#define SYNTH1__PWD_LOMIX__WRITE(src)  (((u_int32_t)(src) << 23) & 0x00800000U)
#define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define SYNTH1__PWD_LOMIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define SYNTH1__PWD_LOMIX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define SYNTH1__PWD_LOMIX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field PWD_LODIV */
#define SYNTH1__PWD_LODIV__SHIFT                                             24
#define SYNTH1__PWD_LODIV__WIDTH                                              1
#define SYNTH1__PWD_LODIV__MASK                                     0x01000000U
#define SYNTH1__PWD_LODIV__READ(src)   (((u_int32_t)(src) & 0x01000000U) >> 24)
#define SYNTH1__PWD_LODIV__WRITE(src)  (((u_int32_t)(src) << 24) & 0x01000000U)
#define SYNTH1__PWD_LODIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define SYNTH1__PWD_LODIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define SYNTH1__PWD_LODIV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define SYNTH1__PWD_LODIV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field PWD_LOBUF5G */
#define SYNTH1__PWD_LOBUF5G__SHIFT                                           25
#define SYNTH1__PWD_LOBUF5G__WIDTH                                            1
#define SYNTH1__PWD_LOBUF5G__MASK                                   0x02000000U
#define SYNTH1__PWD_LOBUF5G__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
#define SYNTH1__PWD_LOBUF5G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define SYNTH1__PWD_LOBUF5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define SYNTH1__PWD_LOBUF5G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define SYNTH1__PWD_LOBUF5G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field PWD_LOBUF2G */
#define SYNTH1__PWD_LOBUF2G__SHIFT                                           26
#define SYNTH1__PWD_LOBUF2G__WIDTH                                            1
#define SYNTH1__PWD_LOBUF2G__MASK                                   0x04000000U
#define SYNTH1__PWD_LOBUF2G__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
#define SYNTH1__PWD_LOBUF2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define SYNTH1__PWD_LOBUF2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define SYNTH1__PWD_LOBUF2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define SYNTH1__PWD_LOBUF2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field PWD_PRESC */
#define SYNTH1__PWD_PRESC__SHIFT                                             27
#define SYNTH1__PWD_PRESC__WIDTH                                              1
#define SYNTH1__PWD_PRESC__MASK                                     0x08000000U
#define SYNTH1__PWD_PRESC__READ(src)   (((u_int32_t)(src) & 0x08000000U) >> 27)
#define SYNTH1__PWD_PRESC__WRITE(src)  (((u_int32_t)(src) << 27) & 0x08000000U)
#define SYNTH1__PWD_PRESC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define SYNTH1__PWD_PRESC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define SYNTH1__PWD_PRESC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define SYNTH1__PWD_PRESC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field PWD_VCO */
#define SYNTH1__PWD_VCO__SHIFT                                               28
#define SYNTH1__PWD_VCO__WIDTH                                                1
#define SYNTH1__PWD_VCO__MASK                                       0x10000000U
#define SYNTH1__PWD_VCO__READ(src)     (((u_int32_t)(src) & 0x10000000U) >> 28)
#define SYNTH1__PWD_VCO__WRITE(src)    (((u_int32_t)(src) << 28) & 0x10000000U)
#define SYNTH1__PWD_VCO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define SYNTH1__PWD_VCO__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define SYNTH1__PWD_VCO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define SYNTH1__PWD_VCO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field PWD_VCMON */
#define SYNTH1__PWD_VCMON__SHIFT                                             29
#define SYNTH1__PWD_VCMON__WIDTH                                              1
#define SYNTH1__PWD_VCMON__MASK                                     0x20000000U
#define SYNTH1__PWD_VCMON__READ(src)   (((u_int32_t)(src) & 0x20000000U) >> 29)
#define SYNTH1__PWD_VCMON__WRITE(src)  (((u_int32_t)(src) << 29) & 0x20000000U)
#define SYNTH1__PWD_VCMON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define SYNTH1__PWD_VCMON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define SYNTH1__PWD_VCMON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define SYNTH1__PWD_VCMON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field PWD_CP */
#define SYNTH1__PWD_CP__SHIFT                                                30
#define SYNTH1__PWD_CP__WIDTH                                                 1
#define SYNTH1__PWD_CP__MASK                                        0x40000000U
#define SYNTH1__PWD_CP__READ(src)      (((u_int32_t)(src) & 0x40000000U) >> 30)
#define SYNTH1__PWD_CP__WRITE(src)     (((u_int32_t)(src) << 30) & 0x40000000U)
#define SYNTH1__PWD_CP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define SYNTH1__PWD_CP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define SYNTH1__PWD_CP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define SYNTH1__PWD_CP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field PWD_BIAS */
#define SYNTH1__PWD_BIAS__SHIFT                                              31
#define SYNTH1__PWD_BIAS__WIDTH                                               1
#define SYNTH1__PWD_BIAS__MASK                                      0x80000000U
#define SYNTH1__PWD_BIAS__READ(src)    (((u_int32_t)(src) & 0x80000000U) >> 31)
#define SYNTH1__PWD_BIAS__WRITE(src)   (((u_int32_t)(src) << 31) & 0x80000000U)
#define SYNTH1__PWD_BIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define SYNTH1__PWD_BIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define SYNTH1__PWD_BIAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SYNTH1__PWD_BIAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SYNTH1__TYPE                                                  u_int32_t
#define SYNTH1__READ                                                0xffffffffU
#define SYNTH1__WRITE                                               0xffffffffU

#endif /* __SYNTH1_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH1 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH1__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH2 */
#ifndef __SYNTH2_MACRO__
#define __SYNTH2_MACRO__

/* macros for field CAPRANGE3 */
#define SYNTH2__CAPRANGE3__SHIFT                                              0
#define SYNTH2__CAPRANGE3__WIDTH                                              4
#define SYNTH2__CAPRANGE3__MASK                                     0x0000000fU
#define SYNTH2__CAPRANGE3__READ(src)             (u_int32_t)(src) & 0x0000000fU
#define SYNTH2__CAPRANGE3__WRITE(src)          ((u_int32_t)(src) & 0x0000000fU)
#define SYNTH2__CAPRANGE3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define SYNTH2__CAPRANGE3__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000000fU)))

/* macros for field CAPRANGE2 */
#define SYNTH2__CAPRANGE2__SHIFT                                              4
#define SYNTH2__CAPRANGE2__WIDTH                                              4
#define SYNTH2__CAPRANGE2__MASK                                     0x000000f0U
#define SYNTH2__CAPRANGE2__READ(src)    (((u_int32_t)(src) & 0x000000f0U) >> 4)
#define SYNTH2__CAPRANGE2__WRITE(src)   (((u_int32_t)(src) << 4) & 0x000000f0U)
#define SYNTH2__CAPRANGE2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define SYNTH2__CAPRANGE2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field CAPRANGE1 */
#define SYNTH2__CAPRANGE1__SHIFT                                              8
#define SYNTH2__CAPRANGE1__WIDTH                                              4
#define SYNTH2__CAPRANGE1__MASK                                     0x00000f00U
#define SYNTH2__CAPRANGE1__READ(src)    (((u_int32_t)(src) & 0x00000f00U) >> 8)
#define SYNTH2__CAPRANGE1__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000f00U)
#define SYNTH2__CAPRANGE1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define SYNTH2__CAPRANGE1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field LOOPLEAKCUR_INTN */
#define SYNTH2__LOOPLEAKCUR_INTN__SHIFT                                      12
#define SYNTH2__LOOPLEAKCUR_INTN__WIDTH                                       4
#define SYNTH2__LOOPLEAKCUR_INTN__MASK                              0x0000f000U
#define SYNTH2__LOOPLEAKCUR_INTN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f000U) >> 12)
#define SYNTH2__LOOPLEAKCUR_INTN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0000f000U)
#define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0000f000U)
#define SYNTH2__LOOPLEAKCUR_INTN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field CPLOWLK_INTN */
#define SYNTH2__CPLOWLK_INTN__SHIFT                                          16
#define SYNTH2__CPLOWLK_INTN__WIDTH                                           1
#define SYNTH2__CPLOWLK_INTN__MASK                                  0x00010000U
#define SYNTH2__CPLOWLK_INTN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define SYNTH2__CPLOWLK_INTN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define SYNTH2__CPLOWLK_INTN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define SYNTH2__CPLOWLK_INTN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define SYNTH2__CPLOWLK_INTN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field CPSTEERING_EN_INTN */
#define SYNTH2__CPSTEERING_EN_INTN__SHIFT                                    17
#define SYNTH2__CPSTEERING_EN_INTN__WIDTH                                     1
#define SYNTH2__CPSTEERING_EN_INTN__MASK                            0x00020000U
#define SYNTH2__CPSTEERING_EN_INTN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define SYNTH2__CPSTEERING_EN_INTN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field CPBIAS_INTN */
#define SYNTH2__CPBIAS_INTN__SHIFT                                           18
#define SYNTH2__CPBIAS_INTN__WIDTH                                            2
#define SYNTH2__CPBIAS_INTN__MASK                                   0x000c0000U
#define SYNTH2__CPBIAS_INTN__READ(src) (((u_int32_t)(src) & 0x000c0000U) >> 18)
#define SYNTH2__CPBIAS_INTN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x000c0000U)
#define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x000c0000U)
#define SYNTH2__CPBIAS_INTN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x000c0000U)))

/* macros for field VC_LOW_REF */
#define SYNTH2__VC_LOW_REF__SHIFT                                            20
#define SYNTH2__VC_LOW_REF__WIDTH                                             3
#define SYNTH2__VC_LOW_REF__MASK                                    0x00700000U
#define SYNTH2__VC_LOW_REF__READ(src)  (((u_int32_t)(src) & 0x00700000U) >> 20)
#define SYNTH2__VC_LOW_REF__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
#define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define SYNTH2__VC_LOW_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field VC_MID_REF */
#define SYNTH2__VC_MID_REF__SHIFT                                            23
#define SYNTH2__VC_MID_REF__WIDTH                                             3
#define SYNTH2__VC_MID_REF__MASK                                    0x03800000U
#define SYNTH2__VC_MID_REF__READ(src)  (((u_int32_t)(src) & 0x03800000U) >> 23)
#define SYNTH2__VC_MID_REF__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
#define SYNTH2__VC_MID_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define SYNTH2__VC_MID_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field VC_HI_REF */
#define SYNTH2__VC_HI_REF__SHIFT                                             26
#define SYNTH2__VC_HI_REF__WIDTH                                              3
#define SYNTH2__VC_HI_REF__MASK                                     0x1c000000U
#define SYNTH2__VC_HI_REF__READ(src)   (((u_int32_t)(src) & 0x1c000000U) >> 26)
#define SYNTH2__VC_HI_REF__WRITE(src)  (((u_int32_t)(src) << 26) & 0x1c000000U)
#define SYNTH2__VC_HI_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define SYNTH2__VC_HI_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field VC_CAL_REF */
#define SYNTH2__VC_CAL_REF__SHIFT                                            29
#define SYNTH2__VC_CAL_REF__WIDTH                                             3
#define SYNTH2__VC_CAL_REF__MASK                                    0xe0000000U
#define SYNTH2__VC_CAL_REF__READ(src)  (((u_int32_t)(src) & 0xe0000000U) >> 29)
#define SYNTH2__VC_CAL_REF__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
#define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define SYNTH2__VC_CAL_REF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define SYNTH2__TYPE                                                  u_int32_t
#define SYNTH2__READ                                                0xffffffffU
#define SYNTH2__WRITE                                               0xffffffffU

#endif /* __SYNTH2_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH2 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH2__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH3 */
#ifndef __SYNTH3_MACRO__
#define __SYNTH3_MACRO__

/* macros for field WAIT_VC_CHECK */
#define SYNTH3__WAIT_VC_CHECK__SHIFT                                          0
#define SYNTH3__WAIT_VC_CHECK__WIDTH                                          6
#define SYNTH3__WAIT_VC_CHECK__MASK                                 0x0000003fU
#define SYNTH3__WAIT_VC_CHECK__READ(src)         (u_int32_t)(src) & 0x0000003fU
#define SYNTH3__WAIT_VC_CHECK__WRITE(src)      ((u_int32_t)(src) & 0x0000003fU)
#define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define SYNTH3__WAIT_VC_CHECK__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field WAIT_CAL_LIN */
#define SYNTH3__WAIT_CAL_LIN__SHIFT                                           6
#define SYNTH3__WAIT_CAL_LIN__WIDTH                                           6
#define SYNTH3__WAIT_CAL_LIN__MASK                                  0x00000fc0U
#define SYNTH3__WAIT_CAL_LIN__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6)
#define SYNTH3__WAIT_CAL_LIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000fc0U)
#define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
                    6) & 0x00000fc0U)
#define SYNTH3__WAIT_CAL_LIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000fc0U)))

/* macros for field WAIT_CAL_BIN */
#define SYNTH3__WAIT_CAL_BIN__SHIFT                                          12
#define SYNTH3__WAIT_CAL_BIN__WIDTH                                           6
#define SYNTH3__WAIT_CAL_BIN__MASK                                  0x0003f000U
#define SYNTH3__WAIT_CAL_BIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0003f000U) >> 12)
#define SYNTH3__WAIT_CAL_BIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0003f000U)
#define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0003f000U)
#define SYNTH3__WAIT_CAL_BIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0003f000U)))

/* macros for field WAIT_PWRUP */
#define SYNTH3__WAIT_PWRUP__SHIFT                                            18
#define SYNTH3__WAIT_PWRUP__WIDTH                                             6
#define SYNTH3__WAIT_PWRUP__MASK                                    0x00fc0000U
#define SYNTH3__WAIT_PWRUP__READ(src)  (((u_int32_t)(src) & 0x00fc0000U) >> 18)
#define SYNTH3__WAIT_PWRUP__WRITE(src) (((u_int32_t)(src) << 18) & 0x00fc0000U)
#define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x00fc0000U)
#define SYNTH3__WAIT_PWRUP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00fc0000U)))

/* macros for field WAIT_SHORTR_PWRUP */
#define SYNTH3__WAIT_SHORTR_PWRUP__SHIFT                                     24
#define SYNTH3__WAIT_SHORTR_PWRUP__WIDTH                                      6
#define SYNTH3__WAIT_SHORTR_PWRUP__MASK                             0x3f000000U
#define SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))

/* macros for field SEL_CLK_DIV2 */
#define SYNTH3__SEL_CLK_DIV2__SHIFT                                          30
#define SYNTH3__SEL_CLK_DIV2__WIDTH                                           1
#define SYNTH3__SEL_CLK_DIV2__MASK                                  0x40000000U
#define SYNTH3__SEL_CLK_DIV2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define SYNTH3__SEL_CLK_DIV2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define SYNTH3__SEL_CLK_DIV2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define SYNTH3__SEL_CLK_DIV2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define SYNTH3__SEL_CLK_DIV2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field DIS_CLK_XTAL */
#define SYNTH3__DIS_CLK_XTAL__SHIFT                                          31
#define SYNTH3__DIS_CLK_XTAL__WIDTH                                           1
#define SYNTH3__DIS_CLK_XTAL__MASK                                  0x80000000U
#define SYNTH3__DIS_CLK_XTAL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define SYNTH3__DIS_CLK_XTAL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define SYNTH3__DIS_CLK_XTAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define SYNTH3__DIS_CLK_XTAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SYNTH3__DIS_CLK_XTAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SYNTH3__TYPE                                                  u_int32_t
#define SYNTH3__READ                                                0xffffffffU
#define SYNTH3__WRITE                                               0xffffffffU

#endif /* __SYNTH3_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH3 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH3__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH4 */
#ifndef __SYNTH4_MACRO__
#define __SYNTH4_MACRO__

/* macros for field PS_SINGLE_PULSE */
#define SYNTH4__PS_SINGLE_PULSE__SHIFT                                        0
#define SYNTH4__PS_SINGLE_PULSE__WIDTH                                        1
#define SYNTH4__PS_SINGLE_PULSE__MASK                               0x00000001U
#define SYNTH4__PS_SINGLE_PULSE__READ(src)       (u_int32_t)(src) & 0x00000001U
#define SYNTH4__PS_SINGLE_PULSE__WRITE(src)    ((u_int32_t)(src) & 0x00000001U)
#define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SYNTH4__PS_SINGLE_PULSE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SYNTH4__PS_SINGLE_PULSE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SYNTH4__PS_SINGLE_PULSE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field LONGSHIFTSEL */
#define SYNTH4__LONGSHIFTSEL__SHIFT                                           1
#define SYNTH4__LONGSHIFTSEL__WIDTH                                           1
#define SYNTH4__LONGSHIFTSEL__MASK                                  0x00000002U
#define SYNTH4__LONGSHIFTSEL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
#define SYNTH4__LONGSHIFTSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define SYNTH4__LONGSHIFTSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define SYNTH4__LONGSHIFTSEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define SYNTH4__LONGSHIFTSEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field LOBUF5GTUNE_OVR */
#define SYNTH4__LOBUF5GTUNE_OVR__SHIFT                                        2
#define SYNTH4__LOBUF5GTUNE_OVR__WIDTH                                        2
#define SYNTH4__LOBUF5GTUNE_OVR__MASK                               0x0000000cU
#define SYNTH4__LOBUF5GTUNE_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field FORCE_LOBUF5GTUNE */
#define SYNTH4__FORCE_LOBUF5GTUNE__SHIFT                                      4
#define SYNTH4__FORCE_LOBUF5GTUNE__WIDTH                                      1
#define SYNTH4__FORCE_LOBUF5GTUNE__MASK                             0x00000010U
#define SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field PSCOUNT_FBSEL */
#define SYNTH4__PSCOUNT_FBSEL__SHIFT                                          5
#define SYNTH4__PSCOUNT_FBSEL__WIDTH                                          1
#define SYNTH4__PSCOUNT_FBSEL__MASK                                 0x00000020U
#define SYNTH4__PSCOUNT_FBSEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define SYNTH4__PSCOUNT_FBSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define SYNTH4__PSCOUNT_FBSEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define SYNTH4__PSCOUNT_FBSEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field SDM_DITHER1 */
#define SYNTH4__SDM_DITHER1__SHIFT                                            6
#define SYNTH4__SDM_DITHER1__WIDTH                                            2
#define SYNTH4__SDM_DITHER1__MASK                                   0x000000c0U
#define SYNTH4__SDM_DITHER1__READ(src)  (((u_int32_t)(src) & 0x000000c0U) >> 6)
#define SYNTH4__SDM_DITHER1__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U)
#define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define SYNTH4__SDM_DITHER1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field SDM_MODE */
#define SYNTH4__SDM_MODE__SHIFT                                               8
#define SYNTH4__SDM_MODE__WIDTH                                               1
#define SYNTH4__SDM_MODE__MASK                                      0x00000100U
#define SYNTH4__SDM_MODE__READ(src)     (((u_int32_t)(src) & 0x00000100U) >> 8)
#define SYNTH4__SDM_MODE__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000100U)
#define SYNTH4__SDM_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define SYNTH4__SDM_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define SYNTH4__SDM_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define SYNTH4__SDM_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field SDM_DISABLE */
#define SYNTH4__SDM_DISABLE__SHIFT                                            9
#define SYNTH4__SDM_DISABLE__WIDTH                                            1
#define SYNTH4__SDM_DISABLE__MASK                                   0x00000200U
#define SYNTH4__SDM_DISABLE__READ(src)  (((u_int32_t)(src) & 0x00000200U) >> 9)
#define SYNTH4__SDM_DISABLE__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
#define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define SYNTH4__SDM_DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define SYNTH4__SDM_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define SYNTH4__SDM_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field RESET_PRESC */
#define SYNTH4__RESET_PRESC__SHIFT                                           10
#define SYNTH4__RESET_PRESC__WIDTH                                            1
#define SYNTH4__RESET_PRESC__MASK                                   0x00000400U
#define SYNTH4__RESET_PRESC__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
#define SYNTH4__RESET_PRESC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define SYNTH4__RESET_PRESC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define SYNTH4__RESET_PRESC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define SYNTH4__RESET_PRESC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define SYNTH4__RESET_PRESC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field PRESCSEL */
#define SYNTH4__PRESCSEL__SHIFT                                              11
#define SYNTH4__PRESCSEL__WIDTH                                               2
#define SYNTH4__PRESCSEL__MASK                                      0x00001800U
#define SYNTH4__PRESCSEL__READ(src)    (((u_int32_t)(src) & 0x00001800U) >> 11)
#define SYNTH4__PRESCSEL__WRITE(src)   (((u_int32_t)(src) << 11) & 0x00001800U)
#define SYNTH4__PRESCSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001800U) | (((u_int32_t)(src) <<\
                    11) & 0x00001800U)
#define SYNTH4__PRESCSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00001800U)))

/* macros for field PFD_DISABLE */
#define SYNTH4__PFD_DISABLE__SHIFT                                           13
#define SYNTH4__PFD_DISABLE__WIDTH                                            1
#define SYNTH4__PFD_DISABLE__MASK                                   0x00002000U
#define SYNTH4__PFD_DISABLE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
#define SYNTH4__PFD_DISABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define SYNTH4__PFD_DISABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define SYNTH4__PFD_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define SYNTH4__PFD_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field PFDDELAY_FRACN */
#define SYNTH4__PFDDELAY_FRACN__SHIFT                                        14
#define SYNTH4__PFDDELAY_FRACN__WIDTH                                         1
#define SYNTH4__PFDDELAY_FRACN__MASK                                0x00004000U
#define SYNTH4__PFDDELAY_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define SYNTH4__PFDDELAY_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define SYNTH4__PFDDELAY_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define SYNTH4__PFDDELAY_FRACN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define SYNTH4__PFDDELAY_FRACN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field FORCE_LO_ON */
#define SYNTH4__FORCE_LO_ON__SHIFT                                           15
#define SYNTH4__FORCE_LO_ON__WIDTH                                            1
#define SYNTH4__FORCE_LO_ON__MASK                                   0x00008000U
#define SYNTH4__FORCE_LO_ON__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15)
#define SYNTH4__FORCE_LO_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define SYNTH4__FORCE_LO_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define SYNTH4__FORCE_LO_ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define SYNTH4__FORCE_LO_ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field CLKXTAL_EDGE_SEL */
#define SYNTH4__CLKXTAL_EDGE_SEL__SHIFT                                      16
#define SYNTH4__CLKXTAL_EDGE_SEL__WIDTH                                       1
#define SYNTH4__CLKXTAL_EDGE_SEL__MASK                              0x00010000U
#define SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field VCOCAPPULLUP */
#define SYNTH4__VCOCAPPULLUP__SHIFT                                          17
#define SYNTH4__VCOCAPPULLUP__WIDTH                                           1
#define SYNTH4__VCOCAPPULLUP__MASK                                  0x00020000U
#define SYNTH4__VCOCAPPULLUP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define SYNTH4__VCOCAPPULLUP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define SYNTH4__VCOCAPPULLUP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define SYNTH4__VCOCAPPULLUP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define SYNTH4__VCOCAPPULLUP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field VCOCAP_OVR */
#define SYNTH4__VCOCAP_OVR__SHIFT                                            18
#define SYNTH4__VCOCAP_OVR__WIDTH                                             8
#define SYNTH4__VCOCAP_OVR__MASK                                    0x03fc0000U
#define SYNTH4__VCOCAP_OVR__READ(src)  (((u_int32_t)(src) & 0x03fc0000U) >> 18)
#define SYNTH4__VCOCAP_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x03fc0000U)
#define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x03fc0000U)
#define SYNTH4__VCOCAP_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x03fc0000U)))

/* macros for field FORCE_VCOCAP */
#define SYNTH4__FORCE_VCOCAP__SHIFT                                          26
#define SYNTH4__FORCE_VCOCAP__WIDTH                                           1
#define SYNTH4__FORCE_VCOCAP__MASK                                  0x04000000U
#define SYNTH4__FORCE_VCOCAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define SYNTH4__FORCE_VCOCAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define SYNTH4__FORCE_VCOCAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define SYNTH4__FORCE_VCOCAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define SYNTH4__FORCE_VCOCAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field FORCE_PINVC */
#define SYNTH4__FORCE_PINVC__SHIFT                                           27
#define SYNTH4__FORCE_PINVC__WIDTH                                            1
#define SYNTH4__FORCE_PINVC__MASK                                   0x08000000U
#define SYNTH4__FORCE_PINVC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
#define SYNTH4__FORCE_PINVC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define SYNTH4__FORCE_PINVC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define SYNTH4__FORCE_PINVC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define SYNTH4__FORCE_PINVC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field SHORTR_UNTIL_LOCKED */
#define SYNTH4__SHORTR_UNTIL_LOCKED__SHIFT                                   28
#define SYNTH4__SHORTR_UNTIL_LOCKED__WIDTH                                    1
#define SYNTH4__SHORTR_UNTIL_LOCKED__MASK                           0x10000000U
#define SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x10000000U) >> 28)
#define SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field ALWAYS_SHORTR */
#define SYNTH4__ALWAYS_SHORTR__SHIFT                                         29
#define SYNTH4__ALWAYS_SHORTR__WIDTH                                          1
#define SYNTH4__ALWAYS_SHORTR__MASK                                 0x20000000U
#define SYNTH4__ALWAYS_SHORTR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x20000000U) >> 29)
#define SYNTH4__ALWAYS_SHORTR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define SYNTH4__ALWAYS_SHORTR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define SYNTH4__ALWAYS_SHORTR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define SYNTH4__ALWAYS_SHORTR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field DIS_LOSTVC */
#define SYNTH4__DIS_LOSTVC__SHIFT                                            30
#define SYNTH4__DIS_LOSTVC__WIDTH                                             1
#define SYNTH4__DIS_LOSTVC__MASK                                    0x40000000U
#define SYNTH4__DIS_LOSTVC__READ(src)  (((u_int32_t)(src) & 0x40000000U) >> 30)
#define SYNTH4__DIS_LOSTVC__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
#define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define SYNTH4__DIS_LOSTVC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define SYNTH4__DIS_LOSTVC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define SYNTH4__DIS_LOSTVC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field DIS_LIN_CAPSEARCH */
#define SYNTH4__DIS_LIN_CAPSEARCH__SHIFT                                     31
#define SYNTH4__DIS_LIN_CAPSEARCH__WIDTH                                      1
#define SYNTH4__DIS_LIN_CAPSEARCH__MASK                             0x80000000U
#define SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SYNTH4__TYPE                                                  u_int32_t
#define SYNTH4__READ                                                0xffffffffU
#define SYNTH4__WRITE                                               0xffffffffU

#endif /* __SYNTH4_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH4 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH4__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH5 */
#ifndef __SYNTH5_MACRO__
#define __SYNTH5_MACRO__

/* macros for field VCOBIAS */
#define SYNTH5__VCOBIAS__SHIFT                                                0
#define SYNTH5__VCOBIAS__WIDTH                                                2
#define SYNTH5__VCOBIAS__MASK                                       0x00000003U
#define SYNTH5__VCOBIAS__READ(src)               (u_int32_t)(src) & 0x00000003U
#define SYNTH5__VCOBIAS__WRITE(src)            ((u_int32_t)(src) & 0x00000003U)
#define SYNTH5__VCOBIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define SYNTH5__VCOBIAS__VERIFY(src)     (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field PWDB_ICLOBUF5G50 */
#define SYNTH5__PWDB_ICLOBUF5G50__SHIFT                                       2
#define SYNTH5__PWDB_ICLOBUF5G50__WIDTH                                       3
#define SYNTH5__PWDB_ICLOBUF5G50__MASK                              0x0000001cU
#define SYNTH5__PWDB_ICLOBUF5G50__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define SYNTH5__PWDB_ICLOBUF5G50__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define SYNTH5__PWDB_ICLOBUF5G50__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))

/* macros for field PWDB_ICLOBUF2G50 */
#define SYNTH5__PWDB_ICLOBUF2G50__SHIFT                                       5
#define SYNTH5__PWDB_ICLOBUF2G50__WIDTH                                       3
#define SYNTH5__PWDB_ICLOBUF2G50__MASK                              0x000000e0U
#define SYNTH5__PWDB_ICLOBUF2G50__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000e0U) >> 5)
#define SYNTH5__PWDB_ICLOBUF2G50__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000000e0U)
#define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define SYNTH5__PWDB_ICLOBUF2G50__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))

/* macros for field PWDB_ICVCO25 */
#define SYNTH5__PWDB_ICVCO25__SHIFT                                           8
#define SYNTH5__PWDB_ICVCO25__WIDTH                                           3
#define SYNTH5__PWDB_ICVCO25__MASK                                  0x00000700U
#define SYNTH5__PWDB_ICVCO25__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8)
#define SYNTH5__PWDB_ICVCO25__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000700U)
#define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define SYNTH5__PWDB_ICVCO25__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field PWDB_ICVCOREG25 */
#define SYNTH5__PWDB_ICVCOREG25__SHIFT                                       11
#define SYNTH5__PWDB_ICVCOREG25__WIDTH                                        3
#define SYNTH5__PWDB_ICVCOREG25__MASK                               0x00003800U
#define SYNTH5__PWDB_ICVCOREG25__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003800U) >> 11)
#define SYNTH5__PWDB_ICVCOREG25__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00003800U)
#define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define SYNTH5__PWDB_ICVCOREG25__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field PWDB_IRVCOREG50 */
#define SYNTH5__PWDB_IRVCOREG50__SHIFT                                       14
#define SYNTH5__PWDB_IRVCOREG50__WIDTH                                        1
#define SYNTH5__PWDB_IRVCOREG50__MASK                               0x00004000U
#define SYNTH5__PWDB_IRVCOREG50__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define SYNTH5__PWDB_IRVCOREG50__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define SYNTH5__PWDB_IRVCOREG50__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define SYNTH5__PWDB_IRVCOREG50__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define SYNTH5__PWDB_IRVCOREG50__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field PWDB_ICLOMIX */
#define SYNTH5__PWDB_ICLOMIX__SHIFT                                          15
#define SYNTH5__PWDB_ICLOMIX__WIDTH                                           3
#define SYNTH5__PWDB_ICLOMIX__MASK                                  0x00038000U
#define SYNTH5__PWDB_ICLOMIX__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00038000U) >> 15)
#define SYNTH5__PWDB_ICLOMIX__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00038000U)
#define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define SYNTH5__PWDB_ICLOMIX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00038000U)))

/* macros for field PWDB_ICLODIV50 */
#define SYNTH5__PWDB_ICLODIV50__SHIFT                                        18
#define SYNTH5__PWDB_ICLODIV50__WIDTH                                         3
#define SYNTH5__PWDB_ICLODIV50__MASK                                0x001c0000U
#define SYNTH5__PWDB_ICLODIV50__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001c0000U) >> 18)
#define SYNTH5__PWDB_ICLODIV50__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x001c0000U)
#define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x001c0000U)
#define SYNTH5__PWDB_ICLODIV50__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x001c0000U)))

/* macros for field PWDB_ICPRESC50 */
#define SYNTH5__PWDB_ICPRESC50__SHIFT                                        21
#define SYNTH5__PWDB_ICPRESC50__WIDTH                                         3
#define SYNTH5__PWDB_ICPRESC50__MASK                                0x00e00000U
#define SYNTH5__PWDB_ICPRESC50__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00e00000U) >> 21)
#define SYNTH5__PWDB_ICPRESC50__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00e00000U)
#define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x00e00000U)
#define SYNTH5__PWDB_ICPRESC50__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00e00000U)))

/* macros for field PWDB_IRVCMON25 */
#define SYNTH5__PWDB_IRVCMON25__SHIFT                                        24
#define SYNTH5__PWDB_IRVCMON25__WIDTH                                         3
#define SYNTH5__PWDB_IRVCMON25__MASK                                0x07000000U
#define SYNTH5__PWDB_IRVCMON25__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07000000U) >> 24)
#define SYNTH5__PWDB_IRVCMON25__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x07000000U)
#define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((u_int32_t)(src) <<\
                    24) & 0x07000000U)
#define SYNTH5__PWDB_IRVCMON25__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x07000000U)))

/* macros for field PWDB_IRPFDCP */
#define SYNTH5__PWDB_IRPFDCP__SHIFT                                          27
#define SYNTH5__PWDB_IRPFDCP__WIDTH                                           3
#define SYNTH5__PWDB_IRPFDCP__MASK                                  0x38000000U
#define SYNTH5__PWDB_IRPFDCP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x38000000U) >> 27)
#define SYNTH5__PWDB_IRPFDCP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x38000000U)
#define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x38000000U) | (((u_int32_t)(src) <<\
                    27) & 0x38000000U)
#define SYNTH5__PWDB_IRPFDCP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x38000000U)))

/* macros for field SDM_DITHER2 */
#define SYNTH5__SDM_DITHER2__SHIFT                                           30
#define SYNTH5__SDM_DITHER2__WIDTH                                            2
#define SYNTH5__SDM_DITHER2__MASK                                   0xc0000000U
#define SYNTH5__SDM_DITHER2__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30)
#define SYNTH5__SDM_DITHER2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define SYNTH5__SDM_DITHER2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define SYNTH5__TYPE                                                  u_int32_t
#define SYNTH5__READ                                                0xffffffffU
#define SYNTH5__WRITE                                               0xffffffffU

#endif /* __SYNTH5_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH5 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH5__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH6 */
#ifndef __SYNTH6_MACRO__
#define __SYNTH6_MACRO__

/* macros for field LOBUF5GTUNE */
#define SYNTH6__LOBUF5GTUNE__SHIFT                                            0
#define SYNTH6__LOBUF5GTUNE__WIDTH                                            2
#define SYNTH6__LOBUF5GTUNE__MASK                                   0x00000003U
#define SYNTH6__LOBUF5GTUNE__READ(src)           (u_int32_t)(src) & 0x00000003U

/* macros for field LOOP_IP */
#define SYNTH6__LOOP_IP__SHIFT                                                2
#define SYNTH6__LOOP_IP__WIDTH                                                7
#define SYNTH6__LOOP_IP__MASK                                       0x000001fcU
#define SYNTH6__LOOP_IP__READ(src)      (((u_int32_t)(src) & 0x000001fcU) >> 2)

/* macros for field VC2LOW */
#define SYNTH6__VC2LOW__SHIFT                                                 9
#define SYNTH6__VC2LOW__WIDTH                                                 1
#define SYNTH6__VC2LOW__MASK                                        0x00000200U
#define SYNTH6__VC2LOW__READ(src)       (((u_int32_t)(src) & 0x00000200U) >> 9)
#define SYNTH6__VC2LOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define SYNTH6__VC2LOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field VC2HIGH */
#define SYNTH6__VC2HIGH__SHIFT                                               10
#define SYNTH6__VC2HIGH__WIDTH                                                1
#define SYNTH6__VC2HIGH__MASK                                       0x00000400U
#define SYNTH6__VC2HIGH__READ(src)     (((u_int32_t)(src) & 0x00000400U) >> 10)
#define SYNTH6__VC2HIGH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define SYNTH6__VC2HIGH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field RESET_SDM_B */
#define SYNTH6__RESET_SDM_B__SHIFT                                           11
#define SYNTH6__RESET_SDM_B__WIDTH                                            1
#define SYNTH6__RESET_SDM_B__MASK                                   0x00000800U
#define SYNTH6__RESET_SDM_B__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
#define SYNTH6__RESET_SDM_B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define SYNTH6__RESET_SDM_B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field RESET_PSCOUNTERS */
#define SYNTH6__RESET_PSCOUNTERS__SHIFT                                      12
#define SYNTH6__RESET_PSCOUNTERS__WIDTH                                       1
#define SYNTH6__RESET_PSCOUNTERS__MASK                              0x00001000U
#define SYNTH6__RESET_PSCOUNTERS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define SYNTH6__RESET_PSCOUNTERS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define SYNTH6__RESET_PSCOUNTERS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field RESET_PFD */
#define SYNTH6__RESET_PFD__SHIFT                                             13
#define SYNTH6__RESET_PFD__WIDTH                                              1
#define SYNTH6__RESET_PFD__MASK                                     0x00002000U
#define SYNTH6__RESET_PFD__READ(src)   (((u_int32_t)(src) & 0x00002000U) >> 13)
#define SYNTH6__RESET_PFD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define SYNTH6__RESET_PFD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field RESET_RFD */
#define SYNTH6__RESET_RFD__SHIFT                                             14
#define SYNTH6__RESET_RFD__WIDTH                                              1
#define SYNTH6__RESET_RFD__MASK                                     0x00004000U
#define SYNTH6__RESET_RFD__READ(src)   (((u_int32_t)(src) & 0x00004000U) >> 14)
#define SYNTH6__RESET_RFD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define SYNTH6__RESET_RFD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field SHORT_R */
#define SYNTH6__SHORT_R__SHIFT                                               15
#define SYNTH6__SHORT_R__WIDTH                                                1
#define SYNTH6__SHORT_R__MASK                                       0x00008000U
#define SYNTH6__SHORT_R__READ(src)     (((u_int32_t)(src) & 0x00008000U) >> 15)
#define SYNTH6__SHORT_R__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define SYNTH6__SHORT_R__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field VCO_CAP_ST */
#define SYNTH6__VCO_CAP_ST__SHIFT                                            16
#define SYNTH6__VCO_CAP_ST__WIDTH                                             8
#define SYNTH6__VCO_CAP_ST__MASK                                    0x00ff0000U
#define SYNTH6__VCO_CAP_ST__READ(src)  (((u_int32_t)(src) & 0x00ff0000U) >> 16)

/* macros for field PIN_VC */
#define SYNTH6__PIN_VC__SHIFT                                                24
#define SYNTH6__PIN_VC__WIDTH                                                 1
#define SYNTH6__PIN_VC__MASK                                        0x01000000U
#define SYNTH6__PIN_VC__READ(src)      (((u_int32_t)(src) & 0x01000000U) >> 24)
#define SYNTH6__PIN_VC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define SYNTH6__PIN_VC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field SYNTH_LOCK_VC_OK */
#define SYNTH6__SYNTH_LOCK_VC_OK__SHIFT                                      25
#define SYNTH6__SYNTH_LOCK_VC_OK__WIDTH                                       1
#define SYNTH6__SYNTH_LOCK_VC_OK__MASK                              0x02000000U
#define SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field CAP_SEARCH */
#define SYNTH6__CAP_SEARCH__SHIFT                                            26
#define SYNTH6__CAP_SEARCH__WIDTH                                             1
#define SYNTH6__CAP_SEARCH__MASK                                    0x04000000U
#define SYNTH6__CAP_SEARCH__READ(src)  (((u_int32_t)(src) & 0x04000000U) >> 26)
#define SYNTH6__CAP_SEARCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define SYNTH6__CAP_SEARCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field SYNTH_SM_STATE */
#define SYNTH6__SYNTH_SM_STATE__SHIFT                                        27
#define SYNTH6__SYNTH_SM_STATE__WIDTH                                         4
#define SYNTH6__SYNTH_SM_STATE__MASK                                0x78000000U
#define SYNTH6__SYNTH_SM_STATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x78000000U) >> 27)

/* macros for field SYNTH_ON */
#define SYNTH6__SYNTH_ON__SHIFT                                              31
#define SYNTH6__SYNTH_ON__WIDTH                                               1
#define SYNTH6__SYNTH_ON__MASK                                      0x80000000U
#define SYNTH6__SYNTH_ON__READ(src)    (((u_int32_t)(src) & 0x80000000U) >> 31)
#define SYNTH6__SYNTH_ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SYNTH6__SYNTH_ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SYNTH6__TYPE                                                  u_int32_t
#define SYNTH6__READ                                                0xffffffffU

#endif /* __SYNTH6_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH6 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH6__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH7 */
#ifndef __SYNTH7_MACRO__
#define __SYNTH7_MACRO__

/* macros for field OVRCHANDECODER */
#define SYNTH7__OVRCHANDECODER__SHIFT                                         0
#define SYNTH7__OVRCHANDECODER__WIDTH                                         1
#define SYNTH7__OVRCHANDECODER__MASK                                0x00000001U
#define SYNTH7__OVRCHANDECODER__READ(src)        (u_int32_t)(src) & 0x00000001U
#define SYNTH7__OVRCHANDECODER__WRITE(src)     ((u_int32_t)(src) & 0x00000001U)
#define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SYNTH7__OVRCHANDECODER__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SYNTH7__OVRCHANDECODER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SYNTH7__OVRCHANDECODER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field FORCE_FRACLSB */
#define SYNTH7__FORCE_FRACLSB__SHIFT                                          1
#define SYNTH7__FORCE_FRACLSB__WIDTH                                          1
#define SYNTH7__FORCE_FRACLSB__MASK                                 0x00000002U
#define SYNTH7__FORCE_FRACLSB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define SYNTH7__FORCE_FRACLSB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define SYNTH7__FORCE_FRACLSB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define SYNTH7__FORCE_FRACLSB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define SYNTH7__FORCE_FRACLSB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field CHANFRAC */
#define SYNTH7__CHANFRAC__SHIFT                                               2
#define SYNTH7__CHANFRAC__WIDTH                                              17
#define SYNTH7__CHANFRAC__MASK                                      0x0007fffcU
#define SYNTH7__CHANFRAC__READ(src)     (((u_int32_t)(src) & 0x0007fffcU) >> 2)
#define SYNTH7__CHANFRAC__WRITE(src)    (((u_int32_t)(src) << 2) & 0x0007fffcU)
#define SYNTH7__CHANFRAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0007fffcU) | (((u_int32_t)(src) <<\
                    2) & 0x0007fffcU)
#define SYNTH7__CHANFRAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0007fffcU)))

/* macros for field CHANSEL */
#define SYNTH7__CHANSEL__SHIFT                                               19
#define SYNTH7__CHANSEL__WIDTH                                                9
#define SYNTH7__CHANSEL__MASK                                       0x0ff80000U
#define SYNTH7__CHANSEL__READ(src)     (((u_int32_t)(src) & 0x0ff80000U) >> 19)
#define SYNTH7__CHANSEL__WRITE(src)    (((u_int32_t)(src) << 19) & 0x0ff80000U)
#define SYNTH7__CHANSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0ff80000U) | (((u_int32_t)(src) <<\
                    19) & 0x0ff80000U)
#define SYNTH7__CHANSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x0ff80000U)))

/* macros for field AMODEREFSEL */
#define SYNTH7__AMODEREFSEL__SHIFT                                           28
#define SYNTH7__AMODEREFSEL__WIDTH                                            2
#define SYNTH7__AMODEREFSEL__MASK                                   0x30000000U
#define SYNTH7__AMODEREFSEL__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28)
#define SYNTH7__AMODEREFSEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x30000000U)
#define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((u_int32_t)(src) <<\
                    28) & 0x30000000U)
#define SYNTH7__AMODEREFSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field FRACMODE */
#define SYNTH7__FRACMODE__SHIFT                                              30
#define SYNTH7__FRACMODE__WIDTH                                               1
#define SYNTH7__FRACMODE__MASK                                      0x40000000U
#define SYNTH7__FRACMODE__READ(src)    (((u_int32_t)(src) & 0x40000000U) >> 30)
#define SYNTH7__FRACMODE__WRITE(src)   (((u_int32_t)(src) << 30) & 0x40000000U)
#define SYNTH7__FRACMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define SYNTH7__FRACMODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define SYNTH7__FRACMODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define SYNTH7__FRACMODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field LOADSYNTHCHANNEL */
#define SYNTH7__LOADSYNTHCHANNEL__SHIFT                                      31
#define SYNTH7__LOADSYNTHCHANNEL__WIDTH                                       1
#define SYNTH7__LOADSYNTHCHANNEL__MASK                              0x80000000U
#define SYNTH7__LOADSYNTHCHANNEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define SYNTH7__LOADSYNTHCHANNEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SYNTH7__TYPE                                                  u_int32_t
#define SYNTH7__READ                                                0xffffffffU
#define SYNTH7__WRITE                                               0xffffffffU

#endif /* __SYNTH7_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH7 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH7__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH8 */
#ifndef __SYNTH8_MACRO__
#define __SYNTH8_MACRO__

/* macros for field CPSTEERING_EN_FRACN */
#define SYNTH8__CPSTEERING_EN_FRACN__SHIFT                                    0
#define SYNTH8__CPSTEERING_EN_FRACN__WIDTH                                    1
#define SYNTH8__CPSTEERING_EN_FRACN__MASK                           0x00000001U
#define SYNTH8__CPSTEERING_EN_FRACN__READ(src)   (u_int32_t)(src) & 0x00000001U
#define SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field LOOP_ICPB */
#define SYNTH8__LOOP_ICPB__SHIFT                                              1
#define SYNTH8__LOOP_ICPB__WIDTH                                              7
#define SYNTH8__LOOP_ICPB__MASK                                     0x000000feU
#define SYNTH8__LOOP_ICPB__READ(src)    (((u_int32_t)(src) & 0x000000feU) >> 1)
#define SYNTH8__LOOP_ICPB__WRITE(src)   (((u_int32_t)(src) << 1) & 0x000000feU)
#define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000feU) | (((u_int32_t)(src) <<\
                    1) & 0x000000feU)
#define SYNTH8__LOOP_ICPB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x000000feU)))

/* macros for field LOOP_CSB */
#define SYNTH8__LOOP_CSB__SHIFT                                               8
#define SYNTH8__LOOP_CSB__WIDTH                                               4
#define SYNTH8__LOOP_CSB__MASK                                      0x00000f00U
#define SYNTH8__LOOP_CSB__READ(src)     (((u_int32_t)(src) & 0x00000f00U) >> 8)
#define SYNTH8__LOOP_CSB__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000f00U)
#define SYNTH8__LOOP_CSB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define SYNTH8__LOOP_CSB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field LOOP_RSB */
#define SYNTH8__LOOP_RSB__SHIFT                                              12
#define SYNTH8__LOOP_RSB__WIDTH                                               5
#define SYNTH8__LOOP_RSB__MASK                                      0x0001f000U
#define SYNTH8__LOOP_RSB__READ(src)    (((u_int32_t)(src) & 0x0001f000U) >> 12)
#define SYNTH8__LOOP_RSB__WRITE(src)   (((u_int32_t)(src) << 12) & 0x0001f000U)
#define SYNTH8__LOOP_RSB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define SYNTH8__LOOP_RSB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field LOOP_CPB */
#define SYNTH8__LOOP_CPB__SHIFT                                              17
#define SYNTH8__LOOP_CPB__WIDTH                                               5
#define SYNTH8__LOOP_CPB__MASK                                      0x003e0000U
#define SYNTH8__LOOP_CPB__READ(src)    (((u_int32_t)(src) & 0x003e0000U) >> 17)
#define SYNTH8__LOOP_CPB__WRITE(src)   (((u_int32_t)(src) << 17) & 0x003e0000U)
#define SYNTH8__LOOP_CPB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define SYNTH8__LOOP_CPB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field LOOP_3RD_ORDER_RB */
#define SYNTH8__LOOP_3RD_ORDER_RB__SHIFT                                     22
#define SYNTH8__LOOP_3RD_ORDER_RB__WIDTH                                      5
#define SYNTH8__LOOP_3RD_ORDER_RB__MASK                             0x07c00000U
#define SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))

/* macros for field REFDIVB */
#define SYNTH8__REFDIVB__SHIFT                                               27
#define SYNTH8__REFDIVB__WIDTH                                                5
#define SYNTH8__REFDIVB__MASK                                       0xf8000000U
#define SYNTH8__REFDIVB__READ(src)     (((u_int32_t)(src) & 0xf8000000U) >> 27)
#define SYNTH8__REFDIVB__WRITE(src)    (((u_int32_t)(src) << 27) & 0xf8000000U)
#define SYNTH8__REFDIVB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define SYNTH8__REFDIVB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define SYNTH8__TYPE                                                  u_int32_t
#define SYNTH8__READ                                                0xffffffffU
#define SYNTH8__WRITE                                               0xffffffffU

#endif /* __SYNTH8_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH8 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH8__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH9 */
#ifndef __SYNTH9_MACRO__
#define __SYNTH9_MACRO__

/* macros for field PFDDELAY_INTN */
#define SYNTH9__PFDDELAY_INTN__SHIFT                                          0
#define SYNTH9__PFDDELAY_INTN__WIDTH                                          1
#define SYNTH9__PFDDELAY_INTN__MASK                                 0x00000001U
#define SYNTH9__PFDDELAY_INTN__READ(src)         (u_int32_t)(src) & 0x00000001U
#define SYNTH9__PFDDELAY_INTN__WRITE(src)      ((u_int32_t)(src) & 0x00000001U)
#define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SYNTH9__PFDDELAY_INTN__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define SYNTH9__PFDDELAY_INTN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SYNTH9__PFDDELAY_INTN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field SLOPE_ICPA0 */
#define SYNTH9__SLOPE_ICPA0__SHIFT                                            1
#define SYNTH9__SLOPE_ICPA0__WIDTH                                            3
#define SYNTH9__SLOPE_ICPA0__MASK                                   0x0000000eU
#define SYNTH9__SLOPE_ICPA0__READ(src)  (((u_int32_t)(src) & 0x0000000eU) >> 1)
#define SYNTH9__SLOPE_ICPA0__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU)
#define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define SYNTH9__SLOPE_ICPA0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field LOOP_ICPA0 */
#define SYNTH9__LOOP_ICPA0__SHIFT                                             4
#define SYNTH9__LOOP_ICPA0__WIDTH                                             4
#define SYNTH9__LOOP_ICPA0__MASK                                    0x000000f0U
#define SYNTH9__LOOP_ICPA0__READ(src)   (((u_int32_t)(src) & 0x000000f0U) >> 4)
#define SYNTH9__LOOP_ICPA0__WRITE(src)  (((u_int32_t)(src) << 4) & 0x000000f0U)
#define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define SYNTH9__LOOP_ICPA0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field LOOP_CSA0 */
#define SYNTH9__LOOP_CSA0__SHIFT                                              8
#define SYNTH9__LOOP_CSA0__WIDTH                                              4
#define SYNTH9__LOOP_CSA0__MASK                                     0x00000f00U
#define SYNTH9__LOOP_CSA0__READ(src)    (((u_int32_t)(src) & 0x00000f00U) >> 8)
#define SYNTH9__LOOP_CSA0__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000f00U)
#define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define SYNTH9__LOOP_CSA0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field LOOP_RSA0 */
#define SYNTH9__LOOP_RSA0__SHIFT                                             12
#define SYNTH9__LOOP_RSA0__WIDTH                                              5
#define SYNTH9__LOOP_RSA0__MASK                                     0x0001f000U
#define SYNTH9__LOOP_RSA0__READ(src)   (((u_int32_t)(src) & 0x0001f000U) >> 12)
#define SYNTH9__LOOP_RSA0__WRITE(src)  (((u_int32_t)(src) << 12) & 0x0001f000U)
#define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define SYNTH9__LOOP_RSA0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field LOOP_CPA0 */
#define SYNTH9__LOOP_CPA0__SHIFT                                             17
#define SYNTH9__LOOP_CPA0__WIDTH                                              5
#define SYNTH9__LOOP_CPA0__MASK                                     0x003e0000U
#define SYNTH9__LOOP_CPA0__READ(src)   (((u_int32_t)(src) & 0x003e0000U) >> 17)
#define SYNTH9__LOOP_CPA0__WRITE(src)  (((u_int32_t)(src) << 17) & 0x003e0000U)
#define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define SYNTH9__LOOP_CPA0__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field LOOP_3RD_ORDER_RA */
#define SYNTH9__LOOP_3RD_ORDER_RA__SHIFT                                     22
#define SYNTH9__LOOP_3RD_ORDER_RA__WIDTH                                      5
#define SYNTH9__LOOP_3RD_ORDER_RA__MASK                             0x07c00000U
#define SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))

/* macros for field REFDIVA */
#define SYNTH9__REFDIVA__SHIFT                                               27
#define SYNTH9__REFDIVA__WIDTH                                                5
#define SYNTH9__REFDIVA__MASK                                       0xf8000000U
#define SYNTH9__REFDIVA__READ(src)     (((u_int32_t)(src) & 0xf8000000U) >> 27)
#define SYNTH9__REFDIVA__WRITE(src)    (((u_int32_t)(src) << 27) & 0xf8000000U)
#define SYNTH9__REFDIVA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define SYNTH9__REFDIVA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define SYNTH9__TYPE                                                  u_int32_t
#define SYNTH9__READ                                                0xffffffffU
#define SYNTH9__WRITE                                               0xffffffffU

#endif /* __SYNTH9_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH9 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH9__NUM                                 1

/* macros for BlueprintGlobalNameSpace::SYNTH10 */
#ifndef __SYNTH10_MACRO__
#define __SYNTH10_MACRO__

/* macros for field SPARE10A */
#define SYNTH10__SPARE10A__SHIFT                                              0
#define SYNTH10__SPARE10A__WIDTH                                              2
#define SYNTH10__SPARE10A__MASK                                     0x00000003U
#define SYNTH10__SPARE10A__READ(src)             (u_int32_t)(src) & 0x00000003U
#define SYNTH10__SPARE10A__WRITE(src)          ((u_int32_t)(src) & 0x00000003U)
#define SYNTH10__SPARE10A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define SYNTH10__SPARE10A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field PWDB_ICLOBIAS50 */
#define SYNTH10__PWDB_ICLOBIAS50__SHIFT                                       2
#define SYNTH10__PWDB_ICLOBIAS50__WIDTH                                       3
#define SYNTH10__PWDB_ICLOBIAS50__MASK                              0x0000001cU
#define SYNTH10__PWDB_ICLOBIAS50__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define SYNTH10__PWDB_ICLOBIAS50__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define SYNTH10__PWDB_ICLOBIAS50__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))

/* macros for field PWDB_IRSPARE25 */
#define SYNTH10__PWDB_IRSPARE25__SHIFT                                        5
#define SYNTH10__PWDB_IRSPARE25__WIDTH                                        3
#define SYNTH10__PWDB_IRSPARE25__MASK                               0x000000e0U
#define SYNTH10__PWDB_IRSPARE25__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000e0U) >> 5)
#define SYNTH10__PWDB_IRSPARE25__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000000e0U)
#define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define SYNTH10__PWDB_IRSPARE25__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))

/* macros for field PWDB_ICSPARE25 */
#define SYNTH10__PWDB_ICSPARE25__SHIFT                                        8
#define SYNTH10__PWDB_ICSPARE25__WIDTH                                        3
#define SYNTH10__PWDB_ICSPARE25__MASK                               0x00000700U
#define SYNTH10__PWDB_ICSPARE25__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000700U) >> 8)
#define SYNTH10__PWDB_ICSPARE25__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000700U)
#define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define SYNTH10__PWDB_ICSPARE25__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field SLOPE_ICPA1 */
#define SYNTH10__SLOPE_ICPA1__SHIFT                                          11
#define SYNTH10__SLOPE_ICPA1__WIDTH                                           3
#define SYNTH10__SLOPE_ICPA1__MASK                                  0x00003800U
#define SYNTH10__SLOPE_ICPA1__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003800U) >> 11)
#define SYNTH10__SLOPE_ICPA1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00003800U)
#define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define SYNTH10__SLOPE_ICPA1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field LOOP_ICPA1 */
#define SYNTH10__LOOP_ICPA1__SHIFT                                           14
#define SYNTH10__LOOP_ICPA1__WIDTH                                            4
#define SYNTH10__LOOP_ICPA1__MASK                                   0x0003c000U
#define SYNTH10__LOOP_ICPA1__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14)
#define SYNTH10__LOOP_ICPA1__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0003c000U)
#define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0003c000U)
#define SYNTH10__LOOP_ICPA1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0003c000U)))

/* macros for field LOOP_CSA1 */
#define SYNTH10__LOOP_CSA1__SHIFT                                            18
#define SYNTH10__LOOP_CSA1__WIDTH                                             4
#define SYNTH10__LOOP_CSA1__MASK                                    0x003c0000U
#define SYNTH10__LOOP_CSA1__READ(src)  (((u_int32_t)(src) & 0x003c0000U) >> 18)
#define SYNTH10__LOOP_CSA1__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U)
#define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x003c0000U)
#define SYNTH10__LOOP_CSA1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x003c0000U)))

/* macros for field LOOP_RSA1 */
#define SYNTH10__LOOP_RSA1__SHIFT                                            22
#define SYNTH10__LOOP_RSA1__WIDTH                                             5
#define SYNTH10__LOOP_RSA1__MASK                                    0x07c00000U
#define SYNTH10__LOOP_RSA1__READ(src)  (((u_int32_t)(src) & 0x07c00000U) >> 22)
#define SYNTH10__LOOP_RSA1__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U)
#define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define SYNTH10__LOOP_RSA1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))

/* macros for field LOOP_CPA1 */
#define SYNTH10__LOOP_CPA1__SHIFT                                            27
#define SYNTH10__LOOP_CPA1__WIDTH                                             5
#define SYNTH10__LOOP_CPA1__MASK                                    0xf8000000U
#define SYNTH10__LOOP_CPA1__READ(src)  (((u_int32_t)(src) & 0xf8000000U) >> 27)
#define SYNTH10__LOOP_CPA1__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
#define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define SYNTH10__LOOP_CPA1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define SYNTH10__TYPE                                                 u_int32_t
#define SYNTH10__READ                                               0xffffffffU
#define SYNTH10__WRITE                                              0xffffffffU

#endif /* __SYNTH10_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH10 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH10__NUM                                1

/* macros for BlueprintGlobalNameSpace::SYNTH11 */
#ifndef __SYNTH11_MACRO__
#define __SYNTH11_MACRO__

/* macros for field SPARE11A */
#define SYNTH11__SPARE11A__SHIFT                                              0
#define SYNTH11__SPARE11A__WIDTH                                              5
#define SYNTH11__SPARE11A__MASK                                     0x0000001fU
#define SYNTH11__SPARE11A__READ(src)             (u_int32_t)(src) & 0x0000001fU
#define SYNTH11__SPARE11A__WRITE(src)          ((u_int32_t)(src) & 0x0000001fU)
#define SYNTH11__SPARE11A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define SYNTH11__SPARE11A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000001fU)))

/* macros for field FORCE_LOBUF5G_ON */
#define SYNTH11__FORCE_LOBUF5G_ON__SHIFT                                      5
#define SYNTH11__FORCE_LOBUF5G_ON__WIDTH                                      1
#define SYNTH11__FORCE_LOBUF5G_ON__MASK                             0x00000020U
#define SYNTH11__FORCE_LOBUF5G_ON__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field LOREFSEL */
#define SYNTH11__LOREFSEL__SHIFT                                              6
#define SYNTH11__LOREFSEL__WIDTH                                              2
#define SYNTH11__LOREFSEL__MASK                                     0x000000c0U
#define SYNTH11__LOREFSEL__READ(src)    (((u_int32_t)(src) & 0x000000c0U) >> 6)
#define SYNTH11__LOREFSEL__WRITE(src)   (((u_int32_t)(src) << 6) & 0x000000c0U)
#define SYNTH11__LOREFSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define SYNTH11__LOREFSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field LOBUF2GTUNE */
#define SYNTH11__LOBUF2GTUNE__SHIFT                                           8
#define SYNTH11__LOBUF2GTUNE__WIDTH                                           2
#define SYNTH11__LOBUF2GTUNE__MASK                                  0x00000300U
#define SYNTH11__LOBUF2GTUNE__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
#define SYNTH11__LOBUF2GTUNE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define SYNTH11__LOBUF2GTUNE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field CPSTEERING_MODE */
#define SYNTH11__CPSTEERING_MODE__SHIFT                                      10
#define SYNTH11__CPSTEERING_MODE__WIDTH                                       1
#define SYNTH11__CPSTEERING_MODE__MASK                              0x00000400U
#define SYNTH11__CPSTEERING_MODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define SYNTH11__CPSTEERING_MODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define SYNTH11__CPSTEERING_MODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define SYNTH11__CPSTEERING_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define SYNTH11__CPSTEERING_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field SLOPE_ICPA2 */
#define SYNTH11__SLOPE_ICPA2__SHIFT                                          11
#define SYNTH11__SLOPE_ICPA2__WIDTH                                           3
#define SYNTH11__SLOPE_ICPA2__MASK                                  0x00003800U
#define SYNTH11__SLOPE_ICPA2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003800U) >> 11)
#define SYNTH11__SLOPE_ICPA2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00003800U)
#define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define SYNTH11__SLOPE_ICPA2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field LOOP_ICPA2 */
#define SYNTH11__LOOP_ICPA2__SHIFT                                           14
#define SYNTH11__LOOP_ICPA2__WIDTH                                            4
#define SYNTH11__LOOP_ICPA2__MASK                                   0x0003c000U
#define SYNTH11__LOOP_ICPA2__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14)
#define SYNTH11__LOOP_ICPA2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0003c000U)
#define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0003c000U)
#define SYNTH11__LOOP_ICPA2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0003c000U)))

/* macros for field LOOP_CSA2 */
#define SYNTH11__LOOP_CSA2__SHIFT                                            18
#define SYNTH11__LOOP_CSA2__WIDTH                                             4
#define SYNTH11__LOOP_CSA2__MASK                                    0x003c0000U
#define SYNTH11__LOOP_CSA2__READ(src)  (((u_int32_t)(src) & 0x003c0000U) >> 18)
#define SYNTH11__LOOP_CSA2__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U)
#define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x003c0000U)
#define SYNTH11__LOOP_CSA2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x003c0000U)))

/* macros for field LOOP_RSA2 */
#define SYNTH11__LOOP_RSA2__SHIFT                                            22
#define SYNTH11__LOOP_RSA2__WIDTH                                             5
#define SYNTH11__LOOP_RSA2__MASK                                    0x07c00000U
#define SYNTH11__LOOP_RSA2__READ(src)  (((u_int32_t)(src) & 0x07c00000U) >> 22)
#define SYNTH11__LOOP_RSA2__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U)
#define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define SYNTH11__LOOP_RSA2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))

/* macros for field LOOP_CPA2 */
#define SYNTH11__LOOP_CPA2__SHIFT                                            27
#define SYNTH11__LOOP_CPA2__WIDTH                                             5
#define SYNTH11__LOOP_CPA2__MASK                                    0xf8000000U
#define SYNTH11__LOOP_CPA2__READ(src)  (((u_int32_t)(src) & 0xf8000000U) >> 27)
#define SYNTH11__LOOP_CPA2__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
#define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define SYNTH11__LOOP_CPA2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define SYNTH11__TYPE                                                 u_int32_t
#define SYNTH11__READ                                               0xffffffffU
#define SYNTH11__WRITE                                              0xffffffffU

#endif /* __SYNTH11_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH11 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH11__NUM                                1

/* macros for BlueprintGlobalNameSpace::SYNTH12 */
#ifndef __SYNTH12_MACRO__
#define __SYNTH12_MACRO__

/* macros for field SPARE12A */
#define SYNTH12__SPARE12A__SHIFT                                              0
#define SYNTH12__SPARE12A__WIDTH                                             10
#define SYNTH12__SPARE12A__MASK                                     0x000003ffU
#define SYNTH12__SPARE12A__READ(src)             (u_int32_t)(src) & 0x000003ffU
#define SYNTH12__SPARE12A__WRITE(src)          ((u_int32_t)(src) & 0x000003ffU)
#define SYNTH12__SPARE12A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define SYNTH12__SPARE12A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000003ffU)))

/* macros for field LOOPLEAKCUR_FRACN */
#define SYNTH12__LOOPLEAKCUR_FRACN__SHIFT                                    10
#define SYNTH12__LOOPLEAKCUR_FRACN__WIDTH                                     4
#define SYNTH12__LOOPLEAKCUR_FRACN__MASK                            0x00003c00U
#define SYNTH12__LOOPLEAKCUR_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003c00U) >> 10)
#define SYNTH12__LOOPLEAKCUR_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00003c00U)
#define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00003c00U)
#define SYNTH12__LOOPLEAKCUR_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00003c00U)))

/* macros for field CPLOWLK_FRACN */
#define SYNTH12__CPLOWLK_FRACN__SHIFT                                        14
#define SYNTH12__CPLOWLK_FRACN__WIDTH                                         1
#define SYNTH12__CPLOWLK_FRACN__MASK                                0x00004000U
#define SYNTH12__CPLOWLK_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define SYNTH12__CPLOWLK_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define SYNTH12__CPLOWLK_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define SYNTH12__CPLOWLK_FRACN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define SYNTH12__CPLOWLK_FRACN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field CPBIAS_FRACN */
#define SYNTH12__CPBIAS_FRACN__SHIFT                                         15
#define SYNTH12__CPBIAS_FRACN__WIDTH                                          2
#define SYNTH12__CPBIAS_FRACN__MASK                                 0x00018000U
#define SYNTH12__CPBIAS_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00018000U) >> 15)
#define SYNTH12__CPBIAS_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00018000U)
#define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00018000U) | (((u_int32_t)(src) <<\
                    15) & 0x00018000U)
#define SYNTH12__CPBIAS_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00018000U)))

/* macros for field SYNTHDIGOUTEN */
#define SYNTH12__SYNTHDIGOUTEN__SHIFT                                        17
#define SYNTH12__SYNTHDIGOUTEN__WIDTH                                         1
#define SYNTH12__SYNTHDIGOUTEN__MASK                                0x00020000U
#define SYNTH12__SYNTHDIGOUTEN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00020000U) >> 17)
#define SYNTH12__SYNTHDIGOUTEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00020000U)
#define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define SYNTH12__SYNTHDIGOUTEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define SYNTH12__SYNTHDIGOUTEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define SYNTH12__SYNTHDIGOUTEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field STRCONT */
#define SYNTH12__STRCONT__SHIFT                                              18
#define SYNTH12__STRCONT__WIDTH                                               1
#define SYNTH12__STRCONT__MASK                                      0x00040000U
#define SYNTH12__STRCONT__READ(src)    (((u_int32_t)(src) & 0x00040000U) >> 18)
#define SYNTH12__STRCONT__WRITE(src)   (((u_int32_t)(src) << 18) & 0x00040000U)
#define SYNTH12__STRCONT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define SYNTH12__STRCONT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define SYNTH12__STRCONT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define SYNTH12__STRCONT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field VREFMUL3 */
#define SYNTH12__VREFMUL3__SHIFT                                             19
#define SYNTH12__VREFMUL3__WIDTH                                              4
#define SYNTH12__VREFMUL3__MASK                                     0x00780000U
#define SYNTH12__VREFMUL3__READ(src)   (((u_int32_t)(src) & 0x00780000U) >> 19)
#define SYNTH12__VREFMUL3__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00780000U)
#define SYNTH12__VREFMUL3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00780000U) | (((u_int32_t)(src) <<\
                    19) & 0x00780000U)
#define SYNTH12__VREFMUL3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00780000U)))

/* macros for field VREFMUL2 */
#define SYNTH12__VREFMUL2__SHIFT                                             23
#define SYNTH12__VREFMUL2__WIDTH                                              4
#define SYNTH12__VREFMUL2__MASK                                     0x07800000U
#define SYNTH12__VREFMUL2__READ(src)   (((u_int32_t)(src) & 0x07800000U) >> 23)
#define SYNTH12__VREFMUL2__WRITE(src)  (((u_int32_t)(src) << 23) & 0x07800000U)
#define SYNTH12__VREFMUL2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07800000U) | (((u_int32_t)(src) <<\
                    23) & 0x07800000U)
#define SYNTH12__VREFMUL2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x07800000U)))

/* macros for field VREFMUL1 */
#define SYNTH12__VREFMUL1__SHIFT                                             27
#define SYNTH12__VREFMUL1__WIDTH                                              4
#define SYNTH12__VREFMUL1__MASK                                     0x78000000U
#define SYNTH12__VREFMUL1__READ(src)   (((u_int32_t)(src) & 0x78000000U) >> 27)
#define SYNTH12__VREFMUL1__WRITE(src)  (((u_int32_t)(src) << 27) & 0x78000000U)
#define SYNTH12__VREFMUL1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define SYNTH12__VREFMUL1__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))

/* macros for field CLK_DOUBLER_EN */
#define SYNTH12__CLK_DOUBLER_EN__SHIFT                                       31
#define SYNTH12__CLK_DOUBLER_EN__WIDTH                                        1
#define SYNTH12__CLK_DOUBLER_EN__MASK                               0x80000000U
#define SYNTH12__CLK_DOUBLER_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define SYNTH12__CLK_DOUBLER_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define SYNTH12__CLK_DOUBLER_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define SYNTH12__CLK_DOUBLER_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define SYNTH12__CLK_DOUBLER_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define SYNTH12__TYPE                                                 u_int32_t
#define SYNTH12__READ                                               0xffffffffU
#define SYNTH12__WRITE                                              0xffffffffU

#endif /* __SYNTH12_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH12 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH12__NUM                                1

/* macros for BlueprintGlobalNameSpace::SYNTH13 */
#ifndef __SYNTH13_MACRO__
#define __SYNTH13_MACRO__

/* macros for field SPARE13A */
#define SYNTH13__SPARE13A__SHIFT                                              0
#define SYNTH13__SPARE13A__WIDTH                                              1
#define SYNTH13__SPARE13A__MASK                                     0x00000001U
#define SYNTH13__SPARE13A__READ(src)             (u_int32_t)(src) & 0x00000001U
#define SYNTH13__SPARE13A__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
#define SYNTH13__SPARE13A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define SYNTH13__SPARE13A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
#define SYNTH13__SPARE13A__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define SYNTH13__SPARE13A__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field SLOPE_ICPA_FRACN */
#define SYNTH13__SLOPE_ICPA_FRACN__SHIFT                                      1
#define SYNTH13__SLOPE_ICPA_FRACN__WIDTH                                      3
#define SYNTH13__SLOPE_ICPA_FRACN__MASK                             0x0000000eU
#define SYNTH13__SLOPE_ICPA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000eU) >> 1)
#define SYNTH13__SLOPE_ICPA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x0000000eU)
#define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000eU) | (((u_int32_t)(src) <<\
                    1) & 0x0000000eU)
#define SYNTH13__SLOPE_ICPA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x0000000eU)))

/* macros for field LOOP_ICPA_FRACN */
#define SYNTH13__LOOP_ICPA_FRACN__SHIFT                                       4
#define SYNTH13__LOOP_ICPA_FRACN__WIDTH                                       4
#define SYNTH13__LOOP_ICPA_FRACN__MASK                              0x000000f0U
#define SYNTH13__LOOP_ICPA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define SYNTH13__LOOP_ICPA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define SYNTH13__LOOP_ICPA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field LOOP_CSA_FRACN */
#define SYNTH13__LOOP_CSA_FRACN__SHIFT                                        8
#define SYNTH13__LOOP_CSA_FRACN__WIDTH                                        4
#define SYNTH13__LOOP_CSA_FRACN__MASK                               0x00000f00U
#define SYNTH13__LOOP_CSA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define SYNTH13__LOOP_CSA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define SYNTH13__LOOP_CSA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field LOOP_RSA_FRACN */
#define SYNTH13__LOOP_RSA_FRACN__SHIFT                                       12
#define SYNTH13__LOOP_RSA_FRACN__WIDTH                                        5
#define SYNTH13__LOOP_RSA_FRACN__MASK                               0x0001f000U
#define SYNTH13__LOOP_RSA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001f000U) >> 12)
#define SYNTH13__LOOP_RSA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x0001f000U)
#define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f000U) | (((u_int32_t)(src) <<\
                    12) & 0x0001f000U)
#define SYNTH13__LOOP_RSA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x0001f000U)))

/* macros for field LOOP_CPA_FRACN */
#define SYNTH13__LOOP_CPA_FRACN__SHIFT                                       17
#define SYNTH13__LOOP_CPA_FRACN__WIDTH                                        5
#define SYNTH13__LOOP_CPA_FRACN__MASK                               0x003e0000U
#define SYNTH13__LOOP_CPA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003e0000U) >> 17)
#define SYNTH13__LOOP_CPA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x003e0000U)
#define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x003e0000U)
#define SYNTH13__LOOP_CPA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x003e0000U)))

/* macros for field LOOP_3RD_ORDER_RA_FRACN */
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__SHIFT                              22
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WIDTH                               5
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MASK                      0x07c00000U
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07c00000U) >> 22)
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x07c00000U)
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x07c00000U)
#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x07c00000U)))

/* macros for field REFDIVA_FRACN */
#define SYNTH13__REFDIVA_FRACN__SHIFT                                        27
#define SYNTH13__REFDIVA_FRACN__WIDTH                                         5
#define SYNTH13__REFDIVA_FRACN__MASK                                0xf8000000U
#define SYNTH13__REFDIVA_FRACN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xf8000000U) >> 27)
#define SYNTH13__REFDIVA_FRACN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0xf8000000U)
#define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define SYNTH13__REFDIVA_FRACN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define SYNTH13__TYPE                                                 u_int32_t
#define SYNTH13__READ                                               0xffffffffU
#define SYNTH13__WRITE                                              0xffffffffU

#endif /* __SYNTH13_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH13 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH13__NUM                                1

/* macros for BlueprintGlobalNameSpace::SYNTH14 */
#ifndef __SYNTH14_MACRO__
#define __SYNTH14_MACRO__

/* macros for field SPARE14A */
#define SYNTH14__SPARE14A__SHIFT                                              0
#define SYNTH14__SPARE14A__WIDTH                                              2
#define SYNTH14__SPARE14A__MASK                                     0x00000003U
#define SYNTH14__SPARE14A__READ(src)             (u_int32_t)(src) & 0x00000003U
#define SYNTH14__SPARE14A__WRITE(src)          ((u_int32_t)(src) & 0x00000003U)
#define SYNTH14__SPARE14A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define SYNTH14__SPARE14A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field LOBUF5GTUNE_3 */
#define SYNTH14__LOBUF5GTUNE_3__SHIFT                                         2
#define SYNTH14__LOBUF5GTUNE_3__WIDTH                                         2
#define SYNTH14__LOBUF5GTUNE_3__MASK                                0x0000000cU
#define SYNTH14__LOBUF5GTUNE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000000cU) >> 2)
#define SYNTH14__LOBUF5GTUNE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000000cU)
#define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000000cU)
#define SYNTH14__LOBUF5GTUNE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field LOBUF2GTUNE_3 */
#define SYNTH14__LOBUF2GTUNE_3__SHIFT                                         4
#define SYNTH14__LOBUF2GTUNE_3__WIDTH                                         2
#define SYNTH14__LOBUF2GTUNE_3__MASK                                0x00000030U
#define SYNTH14__LOBUF2GTUNE_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000030U) >> 4)
#define SYNTH14__LOBUF2GTUNE_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000030U)
#define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define SYNTH14__LOBUF2GTUNE_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field LOBUF5GTUNE_2 */
#define SYNTH14__LOBUF5GTUNE_2__SHIFT                                         6
#define SYNTH14__LOBUF5GTUNE_2__WIDTH                                         2
#define SYNTH14__LOBUF5GTUNE_2__MASK                                0x000000c0U
#define SYNTH14__LOBUF5GTUNE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000c0U) >> 6)
#define SYNTH14__LOBUF5GTUNE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000000c0U)
#define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000000c0U)
#define SYNTH14__LOBUF5GTUNE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field LOBUF2GTUNE_2 */
#define SYNTH14__LOBUF2GTUNE_2__SHIFT                                         8
#define SYNTH14__LOBUF2GTUNE_2__WIDTH                                         2
#define SYNTH14__LOBUF2GTUNE_2__MASK                                0x00000300U
#define SYNTH14__LOBUF2GTUNE_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000300U) >> 8)
#define SYNTH14__LOBUF2GTUNE_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define SYNTH14__LOBUF2GTUNE_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field PWD_LOBUF5G_3 */
#define SYNTH14__PWD_LOBUF5G_3__SHIFT                                        10
#define SYNTH14__PWD_LOBUF5G_3__WIDTH                                         1
#define SYNTH14__PWD_LOBUF5G_3__MASK                                0x00000400U
#define SYNTH14__PWD_LOBUF5G_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define SYNTH14__PWD_LOBUF5G_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define SYNTH14__PWD_LOBUF5G_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define SYNTH14__PWD_LOBUF5G_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define SYNTH14__PWD_LOBUF5G_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field PWD_LOBUF2G_3 */
#define SYNTH14__PWD_LOBUF2G_3__SHIFT                                        11
#define SYNTH14__PWD_LOBUF2G_3__WIDTH                                         1
#define SYNTH14__PWD_LOBUF2G_3__MASK                                0x00000800U
#define SYNTH14__PWD_LOBUF2G_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define SYNTH14__PWD_LOBUF2G_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define SYNTH14__PWD_LOBUF2G_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define SYNTH14__PWD_LOBUF2G_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define SYNTH14__PWD_LOBUF2G_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field PWD_LOBUF5G_2 */
#define SYNTH14__PWD_LOBUF5G_2__SHIFT                                        12
#define SYNTH14__PWD_LOBUF5G_2__WIDTH                                         1
#define SYNTH14__PWD_LOBUF5G_2__MASK                                0x00001000U
#define SYNTH14__PWD_LOBUF5G_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define SYNTH14__PWD_LOBUF5G_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define SYNTH14__PWD_LOBUF5G_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define SYNTH14__PWD_LOBUF5G_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define SYNTH14__PWD_LOBUF5G_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field PWD_LOBUF2G_2 */
#define SYNTH14__PWD_LOBUF2G_2__SHIFT                                        13
#define SYNTH14__PWD_LOBUF2G_2__WIDTH                                         1
#define SYNTH14__PWD_LOBUF2G_2__MASK                                0x00002000U
#define SYNTH14__PWD_LOBUF2G_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define SYNTH14__PWD_LOBUF2G_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define SYNTH14__PWD_LOBUF2G_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define SYNTH14__PWD_LOBUF2G_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define SYNTH14__PWD_LOBUF2G_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field PWUPLO23_PD */
#define SYNTH14__PWUPLO23_PD__SHIFT                                          14
#define SYNTH14__PWUPLO23_PD__WIDTH                                           3
#define SYNTH14__PWUPLO23_PD__MASK                                  0x0001c000U
#define SYNTH14__PWUPLO23_PD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001c000U) >> 14)
#define SYNTH14__PWUPLO23_PD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0001c000U)
#define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define SYNTH14__PWUPLO23_PD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field PWDB_ICLOBUF5G50_3 */
#define SYNTH14__PWDB_ICLOBUF5G50_3__SHIFT                                   17
#define SYNTH14__PWDB_ICLOBUF5G50_3__WIDTH                                    3
#define SYNTH14__PWDB_ICLOBUF5G50_3__MASK                           0x000e0000U
#define SYNTH14__PWDB_ICLOBUF5G50_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000e0000U) >> 17)
#define SYNTH14__PWDB_ICLOBUF5G50_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x000e0000U)
#define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define SYNTH14__PWDB_ICLOBUF5G50_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field PWDB_ICLOBUF2G50_3 */
#define SYNTH14__PWDB_ICLOBUF2G50_3__SHIFT                                   20
#define SYNTH14__PWDB_ICLOBUF2G50_3__WIDTH                                    3
#define SYNTH14__PWDB_ICLOBUF2G50_3__MASK                           0x00700000U
#define SYNTH14__PWDB_ICLOBUF2G50_3__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00700000U) >> 20)
#define SYNTH14__PWDB_ICLOBUF2G50_3__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00700000U)
#define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define SYNTH14__PWDB_ICLOBUF2G50_3__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field PWDB_ICLOBUF5G50_2 */
#define SYNTH14__PWDB_ICLOBUF5G50_2__SHIFT                                   23
#define SYNTH14__PWDB_ICLOBUF5G50_2__WIDTH                                    3
#define SYNTH14__PWDB_ICLOBUF5G50_2__MASK                           0x03800000U
#define SYNTH14__PWDB_ICLOBUF5G50_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03800000U) >> 23)
#define SYNTH14__PWDB_ICLOBUF5G50_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x03800000U)
#define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define SYNTH14__PWDB_ICLOBUF5G50_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field PWDB_ICLOBUF2G50_2 */
#define SYNTH14__PWDB_ICLOBUF2G50_2__SHIFT                                   26
#define SYNTH14__PWDB_ICLOBUF2G50_2__WIDTH                                    3
#define SYNTH14__PWDB_ICLOBUF2G50_2__MASK                           0x1c000000U
#define SYNTH14__PWDB_ICLOBUF2G50_2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define SYNTH14__PWDB_ICLOBUF2G50_2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define SYNTH14__PWDB_ICLOBUF2G50_2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field PWDB_ICLVLSHFT */
#define SYNTH14__PWDB_ICLVLSHFT__SHIFT                                       29
#define SYNTH14__PWDB_ICLVLSHFT__WIDTH                                        3
#define SYNTH14__PWDB_ICLVLSHFT__MASK                               0xe0000000U
#define SYNTH14__PWDB_ICLVLSHFT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xe0000000U) >> 29)
#define SYNTH14__PWDB_ICLVLSHFT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0xe0000000U)
#define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define SYNTH14__PWDB_ICLVLSHFT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define SYNTH14__TYPE                                                 u_int32_t
#define SYNTH14__READ                                               0xffffffffU
#define SYNTH14__WRITE                                              0xffffffffU

#endif /* __SYNTH14_MACRO__ */


/* macros for radio65_reg_map.ch0_SYNTH14 */
#define INST_RADIO65_REG_MAP__CH0_SYNTH14__NUM                                1

/* macros for BlueprintGlobalNameSpace::BIAS1 */
#ifndef __BIAS1_MACRO__
#define __BIAS1_MACRO__

/* macros for field SPARE1 */
#define BIAS1__SPARE1__SHIFT                                                  0
#define BIAS1__SPARE1__WIDTH                                                  3
#define BIAS1__SPARE1__MASK                                         0x00000007U
#define BIAS1__SPARE1__READ(src)                 (u_int32_t)(src) & 0x00000007U
#define BIAS1__SPARE1__WRITE(src)              ((u_int32_t)(src) & 0x00000007U)
#define BIAS1__SPARE1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define BIAS1__SPARE1__VERIFY(src)       (!(((u_int32_t)(src) & ~0x00000007U)))

/* macros for field pwd_ic100pcie */
#define BIAS1__PWD_IC100PCIE__SHIFT                                           3
#define BIAS1__PWD_IC100PCIE__WIDTH                                           3
#define BIAS1__PWD_IC100PCIE__MASK                                  0x00000038U
#define BIAS1__PWD_IC100PCIE__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3)
#define BIAS1__PWD_IC100PCIE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000038U)
#define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000038U) | (((u_int32_t)(src) <<\
                    3) & 0x00000038U)
#define BIAS1__PWD_IC100PCIE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000038U)))

/* macros for field pwd_ic25v2iQ */
#define BIAS1__PWD_IC25V2IQ__SHIFT                                            6
#define BIAS1__PWD_IC25V2IQ__WIDTH                                            3
#define BIAS1__PWD_IC25V2IQ__MASK                                   0x000001c0U
#define BIAS1__PWD_IC25V2IQ__READ(src)  (((u_int32_t)(src) & 0x000001c0U) >> 6)
#define BIAS1__PWD_IC25V2IQ__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U)
#define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000001c0U)
#define BIAS1__PWD_IC25V2IQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000001c0U)))

/* macros for field pwd_ic25v2iI */
#define BIAS1__PWD_IC25V2II__SHIFT                                            9
#define BIAS1__PWD_IC25V2II__WIDTH                                            3
#define BIAS1__PWD_IC25V2II__MASK                                   0x00000e00U
#define BIAS1__PWD_IC25V2II__READ(src)  (((u_int32_t)(src) & 0x00000e00U) >> 9)
#define BIAS1__PWD_IC25V2II__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
#define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define BIAS1__PWD_IC25V2II__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field pwd_ic25bb */
#define BIAS1__PWD_IC25BB__SHIFT                                             12
#define BIAS1__PWD_IC25BB__WIDTH                                              3
#define BIAS1__PWD_IC25BB__MASK                                     0x00007000U
#define BIAS1__PWD_IC25BB__READ(src)   (((u_int32_t)(src) & 0x00007000U) >> 12)
#define BIAS1__PWD_IC25BB__WRITE(src)  (((u_int32_t)(src) << 12) & 0x00007000U)
#define BIAS1__PWD_IC25BB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define BIAS1__PWD_IC25BB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field pwd_ic25dac */
#define BIAS1__PWD_IC25DAC__SHIFT                                            15
#define BIAS1__PWD_IC25DAC__WIDTH                                             3
#define BIAS1__PWD_IC25DAC__MASK                                    0x00038000U
#define BIAS1__PWD_IC25DAC__READ(src)  (((u_int32_t)(src) & 0x00038000U) >> 15)
#define BIAS1__PWD_IC25DAC__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
#define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define BIAS1__PWD_IC25DAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00038000U)))

/* macros for field pwd_ic25fir */
#define BIAS1__PWD_IC25FIR__SHIFT                                            18
#define BIAS1__PWD_IC25FIR__WIDTH                                             3
#define BIAS1__PWD_IC25FIR__MASK                                    0x001c0000U
#define BIAS1__PWD_IC25FIR__READ(src)  (((u_int32_t)(src) & 0x001c0000U) >> 18)
#define BIAS1__PWD_IC25FIR__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U)
#define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x001c0000U)
#define BIAS1__PWD_IC25FIR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x001c0000U)))

/* macros for field pwd_ic25adc */
#define BIAS1__PWD_IC25ADC__SHIFT                                            21
#define BIAS1__PWD_IC25ADC__WIDTH                                             3
#define BIAS1__PWD_IC25ADC__MASK                                    0x00e00000U
#define BIAS1__PWD_IC25ADC__READ(src)  (((u_int32_t)(src) & 0x00e00000U) >> 21)
#define BIAS1__PWD_IC25ADC__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U)
#define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x00e00000U)
#define BIAS1__PWD_IC25ADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00e00000U)))

/* macros for field bias_sel */
#define BIAS1__BIAS_SEL__SHIFT                                               24
#define BIAS1__BIAS_SEL__WIDTH                                                8
#define BIAS1__BIAS_SEL__MASK                                       0xff000000U
#define BIAS1__BIAS_SEL__READ(src)     (((u_int32_t)(src) & 0xff000000U) >> 24)
#define BIAS1__BIAS_SEL__WRITE(src)    (((u_int32_t)(src) << 24) & 0xff000000U)
#define BIAS1__BIAS_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((u_int32_t)(src) <<\
                    24) & 0xff000000U)
#define BIAS1__BIAS_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0xff000000U)))
#define BIAS1__TYPE                                                   u_int32_t
#define BIAS1__READ                                                 0xffffffffU
#define BIAS1__WRITE                                                0xffffffffU

#endif /* __BIAS1_MACRO__ */


/* macros for radio65_reg_map.ch0_BIAS1 */
#define INST_RADIO65_REG_MAP__CH0_BIAS1__NUM                                  1

/* macros for BlueprintGlobalNameSpace::BIAS2 */
#ifndef __BIAS2_MACRO__
#define __BIAS2_MACRO__

/* macros for field SPARE2 */
#define BIAS2__SPARE2__SHIFT                                                  0
#define BIAS2__SPARE2__WIDTH                                                  5
#define BIAS2__SPARE2__MASK                                         0x0000001fU
#define BIAS2__SPARE2__READ(src)                 (u_int32_t)(src) & 0x0000001fU
#define BIAS2__SPARE2__WRITE(src)              ((u_int32_t)(src) & 0x0000001fU)
#define BIAS2__SPARE2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define BIAS2__SPARE2__VERIFY(src)       (!(((u_int32_t)(src) & ~0x0000001fU)))

/* macros for field pwd_ic25xtalreg */
#define BIAS2__PWD_IC25XTALREG__SHIFT                                         5
#define BIAS2__PWD_IC25XTALREG__WIDTH                                         3
#define BIAS2__PWD_IC25XTALREG__MASK                                0x000000e0U
#define BIAS2__PWD_IC25XTALREG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000e0U) >> 5)
#define BIAS2__PWD_IC25XTALREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x000000e0U)
#define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define BIAS2__PWD_IC25XTALREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))

/* macros for field pwd_ic25xtal */
#define BIAS2__PWD_IC25XTAL__SHIFT                                            8
#define BIAS2__PWD_IC25XTAL__WIDTH                                            3
#define BIAS2__PWD_IC25XTAL__MASK                                   0x00000700U
#define BIAS2__PWD_IC25XTAL__READ(src)  (((u_int32_t)(src) & 0x00000700U) >> 8)
#define BIAS2__PWD_IC25XTAL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
#define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define BIAS2__PWD_IC25XTAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field pwd_ic25txrf */
#define BIAS2__PWD_IC25TXRF__SHIFT                                           11
#define BIAS2__PWD_IC25TXRF__WIDTH                                            3
#define BIAS2__PWD_IC25TXRF__MASK                                   0x00003800U
#define BIAS2__PWD_IC25TXRF__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11)
#define BIAS2__PWD_IC25TXRF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00003800U)
#define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define BIAS2__PWD_IC25TXRF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field pwd_ic25rxrf */
#define BIAS2__PWD_IC25RXRF__SHIFT                                           14
#define BIAS2__PWD_IC25RXRF__WIDTH                                            3
#define BIAS2__PWD_IC25RXRF__MASK                                   0x0001c000U
#define BIAS2__PWD_IC25RXRF__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
#define BIAS2__PWD_IC25RXRF__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0001c000U)
#define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define BIAS2__PWD_IC25RXRF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field pwd_ic25synth */
#define BIAS2__PWD_IC25SYNTH__SHIFT                                          17
#define BIAS2__PWD_IC25SYNTH__WIDTH                                           3
#define BIAS2__PWD_IC25SYNTH__MASK                                  0x000e0000U
#define BIAS2__PWD_IC25SYNTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000e0000U) >> 17)
#define BIAS2__PWD_IC25SYNTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x000e0000U)
#define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define BIAS2__PWD_IC25SYNTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field pwd_ic25pllreg */
#define BIAS2__PWD_IC25PLLREG__SHIFT                                         20
#define BIAS2__PWD_IC25PLLREG__WIDTH                                          3
#define BIAS2__PWD_IC25PLLREG__MASK                                 0x00700000U
#define BIAS2__PWD_IC25PLLREG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00700000U) >> 20)
#define BIAS2__PWD_IC25PLLREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00700000U)
#define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define BIAS2__PWD_IC25PLLREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field pwd_ic25pllcp2 */
#define BIAS2__PWD_IC25PLLCP2__SHIFT                                         23
#define BIAS2__PWD_IC25PLLCP2__WIDTH                                          3
#define BIAS2__PWD_IC25PLLCP2__MASK                                 0x03800000U
#define BIAS2__PWD_IC25PLLCP2__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03800000U) >> 23)
#define BIAS2__PWD_IC25PLLCP2__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x03800000U)
#define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define BIAS2__PWD_IC25PLLCP2__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field pwd_ic25pllcp */
#define BIAS2__PWD_IC25PLLCP__SHIFT                                          26
#define BIAS2__PWD_IC25PLLCP__WIDTH                                           3
#define BIAS2__PWD_IC25PLLCP__MASK                                  0x1c000000U
#define BIAS2__PWD_IC25PLLCP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define BIAS2__PWD_IC25PLLCP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define BIAS2__PWD_IC25PLLCP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field pwd_ic25pllgm */
#define BIAS2__PWD_IC25PLLGM__SHIFT                                          29
#define BIAS2__PWD_IC25PLLGM__WIDTH                                           3
#define BIAS2__PWD_IC25PLLGM__MASK                                  0xe0000000U
#define BIAS2__PWD_IC25PLLGM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xe0000000U) >> 29)
#define BIAS2__PWD_IC25PLLGM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0xe0000000U)
#define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define BIAS2__PWD_IC25PLLGM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define BIAS2__TYPE                                                   u_int32_t
#define BIAS2__READ                                                 0xffffffffU
#define BIAS2__WRITE                                                0xffffffffU

#endif /* __BIAS2_MACRO__ */


/* macros for radio65_reg_map.ch0_BIAS2 */
#define INST_RADIO65_REG_MAP__CH0_BIAS2__NUM                                  1

/* macros for BlueprintGlobalNameSpace::BIAS3 */
#ifndef __BIAS3_MACRO__
#define __BIAS3_MACRO__

/* macros for field SPARE3 */
#define BIAS3__SPARE3__SHIFT                                                  0
#define BIAS3__SPARE3__WIDTH                                                  2
#define BIAS3__SPARE3__MASK                                         0x00000003U
#define BIAS3__SPARE3__READ(src)                 (u_int32_t)(src) & 0x00000003U
#define BIAS3__SPARE3__WRITE(src)              ((u_int32_t)(src) & 0x00000003U)
#define BIAS3__SPARE3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define BIAS3__SPARE3__VERIFY(src)       (!(((u_int32_t)(src) & ~0x00000003U)))

/* macros for field pwd_ir25xtalreg */
#define BIAS3__PWD_IR25XTALREG__SHIFT                                         2
#define BIAS3__PWD_IR25XTALREG__WIDTH                                         3
#define BIAS3__PWD_IR25XTALREG__MASK                                0x0000001cU
#define BIAS3__PWD_IR25XTALREG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000001cU) >> 2)
#define BIAS3__PWD_IR25XTALREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x0000001cU)
#define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000001cU)
#define BIAS3__PWD_IR25XTALREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000001cU)))

/* macros for field pwd_ir25txrf */
#define BIAS3__PWD_IR25TXRF__SHIFT                                            5
#define BIAS3__PWD_IR25TXRF__WIDTH                                            3
#define BIAS3__PWD_IR25TXRF__MASK                                   0x000000e0U
#define BIAS3__PWD_IR25TXRF__READ(src)  (((u_int32_t)(src) & 0x000000e0U) >> 5)
#define BIAS3__PWD_IR25TXRF__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U)
#define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000e0U) | (((u_int32_t)(src) <<\
                    5) & 0x000000e0U)
#define BIAS3__PWD_IR25TXRF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x000000e0U)))

/* macros for field pwd_ir25rxrf */
#define BIAS3__PWD_IR25RXRF__SHIFT                                            8
#define BIAS3__PWD_IR25RXRF__WIDTH                                            3
#define BIAS3__PWD_IR25RXRF__MASK                                   0x00000700U
#define BIAS3__PWD_IR25RXRF__READ(src)  (((u_int32_t)(src) & 0x00000700U) >> 8)
#define BIAS3__PWD_IR25RXRF__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
#define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((u_int32_t)(src) <<\
                    8) & 0x00000700U)
#define BIAS3__PWD_IR25RXRF__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field pwd_ir25synth */
#define BIAS3__PWD_IR25SYNTH__SHIFT                                          11
#define BIAS3__PWD_IR25SYNTH__WIDTH                                           3
#define BIAS3__PWD_IR25SYNTH__MASK                                  0x00003800U
#define BIAS3__PWD_IR25SYNTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003800U) >> 11)
#define BIAS3__PWD_IR25SYNTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00003800U)
#define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003800U) | (((u_int32_t)(src) <<\
                    11) & 0x00003800U)
#define BIAS3__PWD_IR25SYNTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00003800U)))

/* macros for field pwd_ir25pllreg */
#define BIAS3__PWD_IR25PLLREG__SHIFT                                         14
#define BIAS3__PWD_IR25PLLREG__WIDTH                                          3
#define BIAS3__PWD_IR25PLLREG__MASK                                 0x0001c000U
#define BIAS3__PWD_IR25PLLREG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001c000U) >> 14)
#define BIAS3__PWD_IR25PLLREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0001c000U)
#define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define BIAS3__PWD_IR25PLLREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field pwd_ir25bb */
#define BIAS3__PWD_IR25BB__SHIFT                                             17
#define BIAS3__PWD_IR25BB__WIDTH                                              3
#define BIAS3__PWD_IR25BB__MASK                                     0x000e0000U
#define BIAS3__PWD_IR25BB__READ(src)   (((u_int32_t)(src) & 0x000e0000U) >> 17)
#define BIAS3__PWD_IR25BB__WRITE(src)  (((u_int32_t)(src) << 17) & 0x000e0000U)
#define BIAS3__PWD_IR25BB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define BIAS3__PWD_IR25BB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field pwd_ir50dac */
#define BIAS3__PWD_IR50DAC__SHIFT                                            20
#define BIAS3__PWD_IR50DAC__WIDTH                                             3
#define BIAS3__PWD_IR50DAC__MASK                                    0x00700000U
#define BIAS3__PWD_IR50DAC__READ(src)  (((u_int32_t)(src) & 0x00700000U) >> 20)
#define BIAS3__PWD_IR50DAC__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
#define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define BIAS3__PWD_IR50DAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field pwd_ir25dac */
#define BIAS3__PWD_IR25DAC__SHIFT                                            23
#define BIAS3__PWD_IR25DAC__WIDTH                                             3
#define BIAS3__PWD_IR25DAC__MASK                                    0x03800000U
#define BIAS3__PWD_IR25DAC__READ(src)  (((u_int32_t)(src) & 0x03800000U) >> 23)
#define BIAS3__PWD_IR25DAC__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
#define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define BIAS3__PWD_IR25DAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field pwd_ir25fir */
#define BIAS3__PWD_IR25FIR__SHIFT                                            26
#define BIAS3__PWD_IR25FIR__WIDTH                                             3
#define BIAS3__PWD_IR25FIR__MASK                                    0x1c000000U
#define BIAS3__PWD_IR25FIR__READ(src)  (((u_int32_t)(src) & 0x1c000000U) >> 26)
#define BIAS3__PWD_IR25FIR__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
#define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define BIAS3__PWD_IR25FIR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field pwd_ir50adc */
#define BIAS3__PWD_IR50ADC__SHIFT                                            29
#define BIAS3__PWD_IR50ADC__WIDTH                                             3
#define BIAS3__PWD_IR50ADC__MASK                                    0xe0000000U
#define BIAS3__PWD_IR50ADC__READ(src)  (((u_int32_t)(src) & 0xe0000000U) >> 29)
#define BIAS3__PWD_IR50ADC__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
#define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define BIAS3__PWD_IR50ADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define BIAS3__TYPE                                                   u_int32_t
#define BIAS3__READ                                                 0xffffffffU
#define BIAS3__WRITE                                                0xffffffffU

#endif /* __BIAS3_MACRO__ */


/* macros for radio65_reg_map.ch0_BIAS3 */
#define INST_RADIO65_REG_MAP__CH0_BIAS3__NUM                                  1

/* macros for BlueprintGlobalNameSpace::BIAS4 */
#ifndef __BIAS4_MACRO__
#define __BIAS4_MACRO__

/* macros for field SPARE4 */
#define BIAS4__SPARE4__SHIFT                                                  0
#define BIAS4__SPARE4__WIDTH                                                 14
#define BIAS4__SPARE4__MASK                                         0x00003fffU
#define BIAS4__SPARE4__READ(src)                 (u_int32_t)(src) & 0x00003fffU
#define BIAS4__SPARE4__WRITE(src)              ((u_int32_t)(src) & 0x00003fffU)
#define BIAS4__SPARE4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((u_int32_t)(src) &\
                    0x00003fffU)
#define BIAS4__SPARE4__VERIFY(src)       (!(((u_int32_t)(src) & ~0x00003fffU)))

/* macros for field pwd_ir25xpabias */
#define BIAS4__PWD_IR25XPABIAS__SHIFT                                        14
#define BIAS4__PWD_IR25XPABIAS__WIDTH                                         3
#define BIAS4__PWD_IR25XPABIAS__MASK                                0x0001c000U
#define BIAS4__PWD_IR25XPABIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0001c000U) >> 14)
#define BIAS4__PWD_IR25XPABIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x0001c000U)
#define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((u_int32_t)(src) <<\
                    14) & 0x0001c000U)
#define BIAS4__PWD_IR25XPABIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field pwd_ir25thermadc */
#define BIAS4__PWD_IR25THERMADC__SHIFT                                       17
#define BIAS4__PWD_IR25THERMADC__WIDTH                                        3
#define BIAS4__PWD_IR25THERMADC__MASK                               0x000e0000U
#define BIAS4__PWD_IR25THERMADC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000e0000U) >> 17)
#define BIAS4__PWD_IR25THERMADC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x000e0000U)
#define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000e0000U) | (((u_int32_t)(src) <<\
                    17) & 0x000e0000U)
#define BIAS4__PWD_IR25THERMADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x000e0000U)))

/* macros for field pwd_ir25otpreg */
#define BIAS4__PWD_IR25OTPREG__SHIFT                                         20
#define BIAS4__PWD_IR25OTPREG__WIDTH                                          3
#define BIAS4__PWD_IR25OTPREG__MASK                                 0x00700000U
#define BIAS4__PWD_IR25OTPREG__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00700000U) >> 20)
#define BIAS4__PWD_IR25OTPREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00700000U)
#define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((u_int32_t)(src) <<\
                    20) & 0x00700000U)
#define BIAS4__PWD_IR25OTPREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field pwd_ic25xpabias */
#define BIAS4__PWD_IC25XPABIAS__SHIFT                                        23
#define BIAS4__PWD_IC25XPABIAS__WIDTH                                         3
#define BIAS4__PWD_IC25XPABIAS__MASK                                0x03800000U
#define BIAS4__PWD_IC25XPABIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03800000U) >> 23)
#define BIAS4__PWD_IC25XPABIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 23) & 0x03800000U)
#define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03800000U) | (((u_int32_t)(src) <<\
                    23) & 0x03800000U)
#define BIAS4__PWD_IC25XPABIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x03800000U)))

/* macros for field pwd_ic25spareB */
#define BIAS4__PWD_IC25SPAREB__SHIFT                                         26
#define BIAS4__PWD_IC25SPAREB__WIDTH                                          3
#define BIAS4__PWD_IC25SPAREB__MASK                                 0x1c000000U
#define BIAS4__PWD_IC25SPAREB__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1c000000U) >> 26)
#define BIAS4__PWD_IC25SPAREB__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x1c000000U)
#define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define BIAS4__PWD_IC25SPAREB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field pwd_ic25spareA */
#define BIAS4__PWD_IC25SPAREA__SHIFT                                         29
#define BIAS4__PWD_IC25SPAREA__WIDTH                                          3
#define BIAS4__PWD_IC25SPAREA__MASK                                 0xe0000000U
#define BIAS4__PWD_IC25SPAREA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xe0000000U) >> 29)
#define BIAS4__PWD_IC25SPAREA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0xe0000000U)
#define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define BIAS4__PWD_IC25SPAREA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define BIAS4__TYPE                                                   u_int32_t
#define BIAS4__READ                                                 0xffffffffU
#define BIAS4__WRITE                                                0xffffffffU

#endif /* __BIAS4_MACRO__ */


/* macros for radio65_reg_map.ch0_BIAS4 */
#define INST_RADIO65_REG_MAP__CH0_BIAS4__NUM                                  1

/* macros for BlueprintGlobalNameSpace::RXTX1 */
#ifndef __RXTX1_MACRO__
#define __RXTX1_MACRO__

/* macros for field scfir_gain */
#define RXTX1__SCFIR_GAIN__SHIFT                                              0
#define RXTX1__SCFIR_GAIN__WIDTH                                              1
#define RXTX1__SCFIR_GAIN__MASK                                     0x00000001U
#define RXTX1__SCFIR_GAIN__READ(src)             (u_int32_t)(src) & 0x00000001U
#define RXTX1__SCFIR_GAIN__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
#define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXTX1__SCFIR_GAIN__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
#define RXTX1__SCFIR_GAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RXTX1__SCFIR_GAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field manrxgain */
#define RXTX1__MANRXGAIN__SHIFT                                               1
#define RXTX1__MANRXGAIN__WIDTH                                               1
#define RXTX1__MANRXGAIN__MASK                                      0x00000002U
#define RXTX1__MANRXGAIN__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
#define RXTX1__MANRXGAIN__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
#define RXTX1__MANRXGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RXTX1__MANRXGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RXTX1__MANRXGAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RXTX1__MANRXGAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field agc_dbdac */
#define RXTX1__AGC_DBDAC__SHIFT                                               2
#define RXTX1__AGC_DBDAC__WIDTH                                               4
#define RXTX1__AGC_DBDAC__MASK                                      0x0000003cU
#define RXTX1__AGC_DBDAC__READ(src)     (((u_int32_t)(src) & 0x0000003cU) >> 2)
#define RXTX1__AGC_DBDAC__WRITE(src)    (((u_int32_t)(src) << 2) & 0x0000003cU)
#define RXTX1__AGC_DBDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003cU) | (((u_int32_t)(src) <<\
                    2) & 0x0000003cU)
#define RXTX1__AGC_DBDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x0000003cU)))

/* macros for field ovr_agc_dbdac */
#define RXTX1__OVR_AGC_DBDAC__SHIFT                                           6
#define RXTX1__OVR_AGC_DBDAC__WIDTH                                           1
#define RXTX1__OVR_AGC_DBDAC__MASK                                  0x00000040U
#define RXTX1__OVR_AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
#define RXTX1__OVR_AGC_DBDAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define RXTX1__OVR_AGC_DBDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define RXTX1__OVR_AGC_DBDAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define RXTX1__OVR_AGC_DBDAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field enable_PAL */
#define RXTX1__ENABLE_PAL__SHIFT                                              7
#define RXTX1__ENABLE_PAL__WIDTH                                              1
#define RXTX1__ENABLE_PAL__MASK                                     0x00000080U
#define RXTX1__ENABLE_PAL__READ(src)    (((u_int32_t)(src) & 0x00000080U) >> 7)
#define RXTX1__ENABLE_PAL__WRITE(src)   (((u_int32_t)(src) << 7) & 0x00000080U)
#define RXTX1__ENABLE_PAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RXTX1__ENABLE_PAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define RXTX1__ENABLE_PAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RXTX1__ENABLE_PAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field enable_PAL_ovr */
#define RXTX1__ENABLE_PAL_OVR__SHIFT                                          8
#define RXTX1__ENABLE_PAL_OVR__WIDTH                                          1
#define RXTX1__ENABLE_PAL_OVR__MASK                                 0x00000100U
#define RXTX1__ENABLE_PAL_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define RXTX1__ENABLE_PAL_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define RXTX1__ENABLE_PAL_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define RXTX1__ENABLE_PAL_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define RXTX1__ENABLE_PAL_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field tx1db_biquad */
#define RXTX1__TX1DB_BIQUAD__SHIFT                                            9
#define RXTX1__TX1DB_BIQUAD__WIDTH                                            3
#define RXTX1__TX1DB_BIQUAD__MASK                                   0x00000e00U
#define RXTX1__TX1DB_BIQUAD__READ(src)  (((u_int32_t)(src) & 0x00000e00U) >> 9)
#define RXTX1__TX1DB_BIQUAD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
#define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define RXTX1__TX1DB_BIQUAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field tx6db_biquad */
#define RXTX1__TX6DB_BIQUAD__SHIFT                                           12
#define RXTX1__TX6DB_BIQUAD__WIDTH                                            2
#define RXTX1__TX6DB_BIQUAD__MASK                                   0x00003000U
#define RXTX1__TX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00003000U) >> 12)
#define RXTX1__TX6DB_BIQUAD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00003000U)
#define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((u_int32_t)(src) <<\
                    12) & 0x00003000U)
#define RXTX1__TX6DB_BIQUAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field padrvhalfgn2g */
#define RXTX1__PADRVHALFGN2G__SHIFT                                          14
#define RXTX1__PADRVHALFGN2G__WIDTH                                           1
#define RXTX1__PADRVHALFGN2G__MASK                                  0x00004000U
#define RXTX1__PADRVHALFGN2G__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define RXTX1__PADRVHALFGN2G__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define RXTX1__PADRVHALFGN2G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define RXTX1__PADRVHALFGN2G__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define RXTX1__PADRVHALFGN2G__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field padrv2gn */
#define RXTX1__PADRV2GN__SHIFT                                               15
#define RXTX1__PADRV2GN__WIDTH                                                4
#define RXTX1__PADRV2GN__MASK                                       0x00078000U
#define RXTX1__PADRV2GN__READ(src)     (((u_int32_t)(src) & 0x00078000U) >> 15)
#define RXTX1__PADRV2GN__WRITE(src)    (((u_int32_t)(src) << 15) & 0x00078000U)
#define RXTX1__PADRV2GN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00078000U) | (((u_int32_t)(src) <<\
                    15) & 0x00078000U)
#define RXTX1__PADRV2GN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00078000U)))

/* macros for field padrv3gn5g */
#define RXTX1__PADRV3GN5G__SHIFT                                             19
#define RXTX1__PADRV3GN5G__WIDTH                                              4
#define RXTX1__PADRV3GN5G__MASK                                     0x00780000U
#define RXTX1__PADRV3GN5G__READ(src)   (((u_int32_t)(src) & 0x00780000U) >> 19)
#define RXTX1__PADRV3GN5G__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00780000U)
#define RXTX1__PADRV3GN5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00780000U) | (((u_int32_t)(src) <<\
                    19) & 0x00780000U)
#define RXTX1__PADRV3GN5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00780000U)))

/* macros for field padrv4gn5g */
#define RXTX1__PADRV4GN5G__SHIFT                                             23
#define RXTX1__PADRV4GN5G__WIDTH                                              4
#define RXTX1__PADRV4GN5G__MASK                                     0x07800000U
#define RXTX1__PADRV4GN5G__READ(src)   (((u_int32_t)(src) & 0x07800000U) >> 23)
#define RXTX1__PADRV4GN5G__WRITE(src)  (((u_int32_t)(src) << 23) & 0x07800000U)
#define RXTX1__PADRV4GN5G__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07800000U) | (((u_int32_t)(src) <<\
                    23) & 0x07800000U)
#define RXTX1__PADRV4GN5G__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x07800000U)))

/* macros for field txbb_gc */
#define RXTX1__TXBB_GC__SHIFT                                                27
#define RXTX1__TXBB_GC__WIDTH                                                 4
#define RXTX1__TXBB_GC__MASK                                        0x78000000U
#define RXTX1__TXBB_GC__READ(src)      (((u_int32_t)(src) & 0x78000000U) >> 27)
#define RXTX1__TXBB_GC__WRITE(src)     (((u_int32_t)(src) << 27) & 0x78000000U)
#define RXTX1__TXBB_GC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x78000000U) | (((u_int32_t)(src) <<\
                    27) & 0x78000000U)
#define RXTX1__TXBB_GC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x78000000U)))

/* macros for field mantxgain */
#define RXTX1__MANTXGAIN__SHIFT                                              31
#define RXTX1__MANTXGAIN__WIDTH                                               1
#define RXTX1__MANTXGAIN__MASK                                      0x80000000U
#define RXTX1__MANTXGAIN__READ(src)    (((u_int32_t)(src) & 0x80000000U) >> 31)
#define RXTX1__MANTXGAIN__WRITE(src)   (((u_int32_t)(src) << 31) & 0x80000000U)
#define RXTX1__MANTXGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RXTX1__MANTXGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RXTX1__MANTXGAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RXTX1__MANTXGAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RXTX1__TYPE                                                   u_int32_t
#define RXTX1__READ                                                 0xffffffffU
#define RXTX1__WRITE                                                0xffffffffU

#endif /* __RXTX1_MACRO__ */


/* macros for radio65_reg_map.ch0_RXTX1 */
#define INST_RADIO65_REG_MAP__CH0_RXTX1__NUM                                  1

/* macros for BlueprintGlobalNameSpace::RXTX2 */
#ifndef __RXTX2_MACRO__
#define __RXTX2_MACRO__

/* macros for field bmode */
#define RXTX2__BMODE__SHIFT                                                   0
#define RXTX2__BMODE__WIDTH                                                   1
#define RXTX2__BMODE__MASK                                          0x00000001U
#define RXTX2__BMODE__READ(src)                  (u_int32_t)(src) & 0x00000001U
#define RXTX2__BMODE__WRITE(src)               ((u_int32_t)(src) & 0x00000001U)
#define RXTX2__BMODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXTX2__BMODE__VERIFY(src)        (!(((u_int32_t)(src) & ~0x00000001U)))
#define RXTX2__BMODE__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
#define RXTX2__BMODE__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)

/* macros for field bmode_ovr */
#define RXTX2__BMODE_OVR__SHIFT                                               1
#define RXTX2__BMODE_OVR__WIDTH                                               1
#define RXTX2__BMODE_OVR__MASK                                      0x00000002U
#define RXTX2__BMODE_OVR__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
#define RXTX2__BMODE_OVR__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
#define RXTX2__BMODE_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RXTX2__BMODE_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RXTX2__BMODE_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RXTX2__BMODE_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field synthon */
#define RXTX2__SYNTHON__SHIFT                                                 2
#define RXTX2__SYNTHON__WIDTH                                                 1
#define RXTX2__SYNTHON__MASK                                        0x00000004U
#define RXTX2__SYNTHON__READ(src)       (((u_int32_t)(src) & 0x00000004U) >> 2)
#define RXTX2__SYNTHON__WRITE(src)      (((u_int32_t)(src) << 2) & 0x00000004U)
#define RXTX2__SYNTHON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RXTX2__SYNTHON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RXTX2__SYNTHON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RXTX2__SYNTHON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field synthon_ovr */
#define RXTX2__SYNTHON_OVR__SHIFT                                             3
#define RXTX2__SYNTHON_OVR__WIDTH                                             1
#define RXTX2__SYNTHON_OVR__MASK                                    0x00000008U
#define RXTX2__SYNTHON_OVR__READ(src)   (((u_int32_t)(src) & 0x00000008U) >> 3)
#define RXTX2__SYNTHON_OVR__WRITE(src)  (((u_int32_t)(src) << 3) & 0x00000008U)
#define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RXTX2__SYNTHON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RXTX2__SYNTHON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RXTX2__SYNTHON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field BW_ST */
#define RXTX2__BW_ST__SHIFT                                                   4
#define RXTX2__BW_ST__WIDTH                                                   2
#define RXTX2__BW_ST__MASK                                          0x00000030U
#define RXTX2__BW_ST__READ(src)         (((u_int32_t)(src) & 0x00000030U) >> 4)
#define RXTX2__BW_ST__WRITE(src)        (((u_int32_t)(src) << 4) & 0x00000030U)
#define RXTX2__BW_ST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((u_int32_t)(src) <<\
                    4) & 0x00000030U)
#define RXTX2__BW_ST__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000030U)))

/* macros for field BW_ST_ovr */
#define RXTX2__BW_ST_OVR__SHIFT                                               6
#define RXTX2__BW_ST_OVR__WIDTH                                               1
#define RXTX2__BW_ST_OVR__MASK                                      0x00000040U
#define RXTX2__BW_ST_OVR__READ(src)     (((u_int32_t)(src) & 0x00000040U) >> 6)
#define RXTX2__BW_ST_OVR__WRITE(src)    (((u_int32_t)(src) << 6) & 0x00000040U)
#define RXTX2__BW_ST_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define RXTX2__BW_ST_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define RXTX2__BW_ST_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define RXTX2__BW_ST_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field txon */
#define RXTX2__TXON__SHIFT                                                    7
#define RXTX2__TXON__WIDTH                                                    1
#define RXTX2__TXON__MASK                                           0x00000080U
#define RXTX2__TXON__READ(src)          (((u_int32_t)(src) & 0x00000080U) >> 7)
#define RXTX2__TXON__WRITE(src)         (((u_int32_t)(src) << 7) & 0x00000080U)
#define RXTX2__TXON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RXTX2__TXON__VERIFY(src)  (!((((u_int32_t)(src) << 7) & ~0x00000080U)))
#define RXTX2__TXON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RXTX2__TXON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field txon_ovr */
#define RXTX2__TXON_OVR__SHIFT                                                8
#define RXTX2__TXON_OVR__WIDTH                                                1
#define RXTX2__TXON_OVR__MASK                                       0x00000100U
#define RXTX2__TXON_OVR__READ(src)      (((u_int32_t)(src) & 0x00000100U) >> 8)
#define RXTX2__TXON_OVR__WRITE(src)     (((u_int32_t)(src) << 8) & 0x00000100U)
#define RXTX2__TXON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define RXTX2__TXON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define RXTX2__TXON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define RXTX2__TXON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field paon */
#define RXTX2__PAON__SHIFT                                                    9
#define RXTX2__PAON__WIDTH                                                    1
#define RXTX2__PAON__MASK                                           0x00000200U
#define RXTX2__PAON__READ(src)          (((u_int32_t)(src) & 0x00000200U) >> 9)
#define RXTX2__PAON__WRITE(src)         (((u_int32_t)(src) << 9) & 0x00000200U)
#define RXTX2__PAON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define RXTX2__PAON__VERIFY(src)  (!((((u_int32_t)(src) << 9) & ~0x00000200U)))
#define RXTX2__PAON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define RXTX2__PAON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field paon_ovr */
#define RXTX2__PAON_OVR__SHIFT                                               10
#define RXTX2__PAON_OVR__WIDTH                                                1
#define RXTX2__PAON_OVR__MASK                                       0x00000400U
#define RXTX2__PAON_OVR__READ(src)     (((u_int32_t)(src) & 0x00000400U) >> 10)
#define RXTX2__PAON_OVR__WRITE(src)    (((u_int32_t)(src) << 10) & 0x00000400U)
#define RXTX2__PAON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define RXTX2__PAON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define RXTX2__PAON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define RXTX2__PAON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field rxon */
#define RXTX2__RXON__SHIFT                                                   11
#define RXTX2__RXON__WIDTH                                                    1
#define RXTX2__RXON__MASK                                           0x00000800U
#define RXTX2__RXON__READ(src)         (((u_int32_t)(src) & 0x00000800U) >> 11)
#define RXTX2__RXON__WRITE(src)        (((u_int32_t)(src) << 11) & 0x00000800U)
#define RXTX2__RXON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define RXTX2__RXON__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00000800U)))
#define RXTX2__RXON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define RXTX2__RXON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field rxon_ovr */
#define RXTX2__RXON_OVR__SHIFT                                               12
#define RXTX2__RXON_OVR__WIDTH                                                1
#define RXTX2__RXON_OVR__MASK                                       0x00001000U
#define RXTX2__RXON_OVR__READ(src)     (((u_int32_t)(src) & 0x00001000U) >> 12)
#define RXTX2__RXON_OVR__WRITE(src)    (((u_int32_t)(src) << 12) & 0x00001000U)
#define RXTX2__RXON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define RXTX2__RXON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define RXTX2__RXON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define RXTX2__RXON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field agcon */
#define RXTX2__AGCON__SHIFT                                                  13
#define RXTX2__AGCON__WIDTH                                                   1
#define RXTX2__AGCON__MASK                                          0x00002000U
#define RXTX2__AGCON__READ(src)        (((u_int32_t)(src) & 0x00002000U) >> 13)
#define RXTX2__AGCON__WRITE(src)       (((u_int32_t)(src) << 13) & 0x00002000U)
#define RXTX2__AGCON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define RXTX2__AGCON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define RXTX2__AGCON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define RXTX2__AGCON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field agcon_ovr */
#define RXTX2__AGCON_OVR__SHIFT                                              14
#define RXTX2__AGCON_OVR__WIDTH                                               1
#define RXTX2__AGCON_OVR__MASK                                      0x00004000U
#define RXTX2__AGCON_OVR__READ(src)    (((u_int32_t)(src) & 0x00004000U) >> 14)
#define RXTX2__AGCON_OVR__WRITE(src)   (((u_int32_t)(src) << 14) & 0x00004000U)
#define RXTX2__AGCON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define RXTX2__AGCON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define RXTX2__AGCON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define RXTX2__AGCON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field txmod */
#define RXTX2__TXMOD__SHIFT                                                  15
#define RXTX2__TXMOD__WIDTH                                                   3
#define RXTX2__TXMOD__MASK                                          0x00038000U
#define RXTX2__TXMOD__READ(src)        (((u_int32_t)(src) & 0x00038000U) >> 15)
#define RXTX2__TXMOD__WRITE(src)       (((u_int32_t)(src) << 15) & 0x00038000U)
#define RXTX2__TXMOD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define RXTX2__TXMOD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00038000U)))

/* macros for field txmod_ovr */
#define RXTX2__TXMOD_OVR__SHIFT                                              18
#define RXTX2__TXMOD_OVR__WIDTH                                               1
#define RXTX2__TXMOD_OVR__MASK                                      0x00040000U
#define RXTX2__TXMOD_OVR__READ(src)    (((u_int32_t)(src) & 0x00040000U) >> 18)
#define RXTX2__TXMOD_OVR__WRITE(src)   (((u_int32_t)(src) << 18) & 0x00040000U)
#define RXTX2__TXMOD_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define RXTX2__TXMOD_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define RXTX2__TXMOD_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define RXTX2__TXMOD_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field rx1db_biquad */
#define RXTX2__RX1DB_BIQUAD__SHIFT                                           19
#define RXTX2__RX1DB_BIQUAD__WIDTH                                            3
#define RXTX2__RX1DB_BIQUAD__MASK                                   0x00380000U
#define RXTX2__RX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00380000U) >> 19)
#define RXTX2__RX1DB_BIQUAD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 19) & 0x00380000U)
#define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00380000U) | (((u_int32_t)(src) <<\
                    19) & 0x00380000U)
#define RXTX2__RX1DB_BIQUAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00380000U)))

/* macros for field rx6db_biquad */
#define RXTX2__RX6DB_BIQUAD__SHIFT                                           22
#define RXTX2__RX6DB_BIQUAD__WIDTH                                            2
#define RXTX2__RX6DB_BIQUAD__MASK                                   0x00c00000U
#define RXTX2__RX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22)
#define RXTX2__RX6DB_BIQUAD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00c00000U)
#define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00c00000U) | (((u_int32_t)(src) <<\
                    22) & 0x00c00000U)
#define RXTX2__RX6DB_BIQUAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00c00000U)))

/* macros for field mxrgain */
#define RXTX2__MXRGAIN__SHIFT                                                24
#define RXTX2__MXRGAIN__WIDTH                                                 2
#define RXTX2__MXRGAIN__MASK                                        0x03000000U
#define RXTX2__MXRGAIN__READ(src)      (((u_int32_t)(src) & 0x03000000U) >> 24)
#define RXTX2__MXRGAIN__WRITE(src)     (((u_int32_t)(src) << 24) & 0x03000000U)
#define RXTX2__MXRGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((u_int32_t)(src) <<\
                    24) & 0x03000000U)
#define RXTX2__MXRGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field vgagain */
#define RXTX2__VGAGAIN__SHIFT                                                26
#define RXTX2__VGAGAIN__WIDTH                                                 3
#define RXTX2__VGAGAIN__MASK                                        0x1c000000U
#define RXTX2__VGAGAIN__READ(src)      (((u_int32_t)(src) & 0x1c000000U) >> 26)
#define RXTX2__VGAGAIN__WRITE(src)     (((u_int32_t)(src) << 26) & 0x1c000000U)
#define RXTX2__VGAGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x1c000000U)
#define RXTX2__VGAGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x1c000000U)))

/* macros for field lnagain */
#define RXTX2__LNAGAIN__SHIFT                                                29
#define RXTX2__LNAGAIN__WIDTH                                                 3
#define RXTX2__LNAGAIN__MASK                                        0xe0000000U
#define RXTX2__LNAGAIN__READ(src)      (((u_int32_t)(src) & 0xe0000000U) >> 29)
#define RXTX2__LNAGAIN__WRITE(src)     (((u_int32_t)(src) << 29) & 0xe0000000U)
#define RXTX2__LNAGAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define RXTX2__LNAGAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define RXTX2__TYPE                                                   u_int32_t
#define RXTX2__READ                                                 0xffffffffU
#define RXTX2__WRITE                                                0xffffffffU

#endif /* __RXTX2_MACRO__ */


/* macros for radio65_reg_map.ch0_RXTX2 */
#define INST_RADIO65_REG_MAP__CH0_RXTX2__NUM                                  1

/* macros for BlueprintGlobalNameSpace::RXTX3 */
#ifndef __RXTX3_MACRO__
#define __RXTX3_MACRO__

/* macros for field xlnabias_pwd */
#define RXTX3__XLNABIAS_PWD__SHIFT                                            0
#define RXTX3__XLNABIAS_PWD__WIDTH                                            1
#define RXTX3__XLNABIAS_PWD__MASK                                   0x00000001U
#define RXTX3__XLNABIAS_PWD__READ(src)           (u_int32_t)(src) & 0x00000001U
#define RXTX3__XLNABIAS_PWD__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
#define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RXTX3__XLNABIAS_PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
#define RXTX3__XLNABIAS_PWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RXTX3__XLNABIAS_PWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field xlnaon */
#define RXTX3__XLNAON__SHIFT                                                  1
#define RXTX3__XLNAON__WIDTH                                                  1
#define RXTX3__XLNAON__MASK                                         0x00000002U
#define RXTX3__XLNAON__READ(src)        (((u_int32_t)(src) & 0x00000002U) >> 1)
#define RXTX3__XLNAON__WRITE(src)       (((u_int32_t)(src) << 1) & 0x00000002U)
#define RXTX3__XLNAON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RXTX3__XLNAON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RXTX3__XLNAON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RXTX3__XLNAON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field xlnaon_ovr */
#define RXTX3__XLNAON_OVR__SHIFT                                              2
#define RXTX3__XLNAON_OVR__WIDTH                                              1
#define RXTX3__XLNAON_OVR__MASK                                     0x00000004U
#define RXTX3__XLNAON_OVR__READ(src)    (((u_int32_t)(src) & 0x00000004U) >> 2)
#define RXTX3__XLNAON_OVR__WRITE(src)   (((u_int32_t)(src) << 2) & 0x00000004U)
#define RXTX3__XLNAON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RXTX3__XLNAON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RXTX3__XLNAON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RXTX3__XLNAON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field dacFullScale */
#define RXTX3__DACFULLSCALE__SHIFT                                            3
#define RXTX3__DACFULLSCALE__WIDTH                                            1
#define RXTX3__DACFULLSCALE__MASK                                   0x00000008U
#define RXTX3__DACFULLSCALE__READ(src)  (((u_int32_t)(src) & 0x00000008U) >> 3)
#define RXTX3__DACFULLSCALE__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
#define RXTX3__DACFULLSCALE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RXTX3__DACFULLSCALE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RXTX3__DACFULLSCALE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RXTX3__DACFULLSCALE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field dacrstb */
#define RXTX3__DACRSTB__SHIFT                                                 4
#define RXTX3__DACRSTB__WIDTH                                                 1
#define RXTX3__DACRSTB__MASK                                        0x00000010U
#define RXTX3__DACRSTB__READ(src)       (((u_int32_t)(src) & 0x00000010U) >> 4)
#define RXTX3__DACRSTB__WRITE(src)      (((u_int32_t)(src) << 4) & 0x00000010U)
#define RXTX3__DACRSTB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RXTX3__DACRSTB__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RXTX3__DACRSTB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RXTX3__DACRSTB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field addacloopback */
#define RXTX3__ADDACLOOPBACK__SHIFT                                           5
#define RXTX3__ADDACLOOPBACK__WIDTH                                           1
#define RXTX3__ADDACLOOPBACK__MASK                                  0x00000020U
#define RXTX3__ADDACLOOPBACK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
#define RXTX3__ADDACLOOPBACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define RXTX3__ADDACLOOPBACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define RXTX3__ADDACLOOPBACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RXTX3__ADDACLOOPBACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field adcshort */
#define RXTX3__ADCSHORT__SHIFT                                                6
#define RXTX3__ADCSHORT__WIDTH                                                1
#define RXTX3__ADCSHORT__MASK                                       0x00000040U
#define RXTX3__ADCSHORT__READ(src)      (((u_int32_t)(src) & 0x00000040U) >> 6)
#define RXTX3__ADCSHORT__WRITE(src)     (((u_int32_t)(src) << 6) & 0x00000040U)
#define RXTX3__ADCSHORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define RXTX3__ADCSHORT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define RXTX3__ADCSHORT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define RXTX3__ADCSHORT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field dacpwd */
#define RXTX3__DACPWD__SHIFT                                                  7
#define RXTX3__DACPWD__WIDTH                                                  1
#define RXTX3__DACPWD__MASK                                         0x00000080U
#define RXTX3__DACPWD__READ(src)        (((u_int32_t)(src) & 0x00000080U) >> 7)
#define RXTX3__DACPWD__WRITE(src)       (((u_int32_t)(src) << 7) & 0x00000080U)
#define RXTX3__DACPWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RXTX3__DACPWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define RXTX3__DACPWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RXTX3__DACPWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field dacpwd_ovr */
#define RXTX3__DACPWD_OVR__SHIFT                                              8
#define RXTX3__DACPWD_OVR__WIDTH                                              1
#define RXTX3__DACPWD_OVR__MASK                                     0x00000100U
#define RXTX3__DACPWD_OVR__READ(src)    (((u_int32_t)(src) & 0x00000100U) >> 8)
#define RXTX3__DACPWD_OVR__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000100U)
#define RXTX3__DACPWD_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define RXTX3__DACPWD_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define RXTX3__DACPWD_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define RXTX3__DACPWD_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field adcpwd */
#define RXTX3__ADCPWD__SHIFT                                                  9
#define RXTX3__ADCPWD__WIDTH                                                  1
#define RXTX3__ADCPWD__MASK                                         0x00000200U
#define RXTX3__ADCPWD__READ(src)        (((u_int32_t)(src) & 0x00000200U) >> 9)
#define RXTX3__ADCPWD__WRITE(src)       (((u_int32_t)(src) << 9) & 0x00000200U)
#define RXTX3__ADCPWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define RXTX3__ADCPWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define RXTX3__ADCPWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define RXTX3__ADCPWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field adcpwd_ovr */
#define RXTX3__ADCPWD_OVR__SHIFT                                             10
#define RXTX3__ADCPWD_OVR__WIDTH                                              1
#define RXTX3__ADCPWD_OVR__MASK                                     0x00000400U
#define RXTX3__ADCPWD_OVR__READ(src)   (((u_int32_t)(src) & 0x00000400U) >> 10)
#define RXTX3__ADCPWD_OVR__WRITE(src)  (((u_int32_t)(src) << 10) & 0x00000400U)
#define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define RXTX3__ADCPWD_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define RXTX3__ADCPWD_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define RXTX3__ADCPWD_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field agc_caldac */
#define RXTX3__AGC_CALDAC__SHIFT                                             11
#define RXTX3__AGC_CALDAC__WIDTH                                              6
#define RXTX3__AGC_CALDAC__MASK                                     0x0001f800U
#define RXTX3__AGC_CALDAC__READ(src)   (((u_int32_t)(src) & 0x0001f800U) >> 11)
#define RXTX3__AGC_CALDAC__WRITE(src)  (((u_int32_t)(src) << 11) & 0x0001f800U)
#define RXTX3__AGC_CALDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001f800U) | (((u_int32_t)(src) <<\
                    11) & 0x0001f800U)
#define RXTX3__AGC_CALDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x0001f800U)))

/* macros for field agc_cal */
#define RXTX3__AGC_CAL__SHIFT                                                17
#define RXTX3__AGC_CAL__WIDTH                                                 1
#define RXTX3__AGC_CAL__MASK                                        0x00020000U
#define RXTX3__AGC_CAL__READ(src)      (((u_int32_t)(src) & 0x00020000U) >> 17)
#define RXTX3__AGC_CAL__WRITE(src)     (((u_int32_t)(src) << 17) & 0x00020000U)
#define RXTX3__AGC_CAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define RXTX3__AGC_CAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define RXTX3__AGC_CAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define RXTX3__AGC_CAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field agc_cal_ovr */
#define RXTX3__AGC_CAL_OVR__SHIFT                                            18
#define RXTX3__AGC_CAL_OVR__WIDTH                                             1
#define RXTX3__AGC_CAL_OVR__MASK                                    0x00040000U
#define RXTX3__AGC_CAL_OVR__READ(src)  (((u_int32_t)(src) & 0x00040000U) >> 18)
#define RXTX3__AGC_CAL_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
#define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define RXTX3__AGC_CAL_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define RXTX3__AGC_CAL_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define RXTX3__AGC_CAL_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field LOforcedon */
#define RXTX3__LOFORCEDON__SHIFT                                             19
#define RXTX3__LOFORCEDON__WIDTH                                              1
#define RXTX3__LOFORCEDON__MASK                                     0x00080000U
#define RXTX3__LOFORCEDON__READ(src)   (((u_int32_t)(src) & 0x00080000U) >> 19)
#define RXTX3__LOFORCEDON__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00080000U)
#define RXTX3__LOFORCEDON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define RXTX3__LOFORCEDON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define RXTX3__LOFORCEDON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define RXTX3__LOFORCEDON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field calresidue */
#define RXTX3__CALRESIDUE__SHIFT                                             20
#define RXTX3__CALRESIDUE__WIDTH                                              1
#define RXTX3__CALRESIDUE__MASK                                     0x00100000U
#define RXTX3__CALRESIDUE__READ(src)   (((u_int32_t)(src) & 0x00100000U) >> 20)
#define RXTX3__CALRESIDUE__WRITE(src)  (((u_int32_t)(src) << 20) & 0x00100000U)
#define RXTX3__CALRESIDUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define RXTX3__CALRESIDUE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define RXTX3__CALRESIDUE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define RXTX3__CALRESIDUE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field calresidue_ovr */
#define RXTX3__CALRESIDUE_OVR__SHIFT                                         21
#define RXTX3__CALRESIDUE_OVR__WIDTH                                          1
#define RXTX3__CALRESIDUE_OVR__MASK                                 0x00200000U
#define RXTX3__CALRESIDUE_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define RXTX3__CALRESIDUE_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define RXTX3__CALRESIDUE_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define RXTX3__CALRESIDUE_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define RXTX3__CALRESIDUE_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field calfc */
#define RXTX3__CALFC__SHIFT                                                  22
#define RXTX3__CALFC__WIDTH                                                   1
#define RXTX3__CALFC__MASK                                          0x00400000U
#define RXTX3__CALFC__READ(src)        (((u_int32_t)(src) & 0x00400000U) >> 22)
#define RXTX3__CALFC__WRITE(src)       (((u_int32_t)(src) << 22) & 0x00400000U)
#define RXTX3__CALFC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define RXTX3__CALFC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define RXTX3__CALFC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define RXTX3__CALFC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field calfc_ovr */
#define RXTX3__CALFC_OVR__SHIFT                                              23
#define RXTX3__CALFC_OVR__WIDTH                                               1
#define RXTX3__CALFC_OVR__MASK                                      0x00800000U
#define RXTX3__CALFC_OVR__READ(src)    (((u_int32_t)(src) & 0x00800000U) >> 23)
#define RXTX3__CALFC_OVR__WRITE(src)   (((u_int32_t)(src) << 23) & 0x00800000U)
#define RXTX3__CALFC_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define RXTX3__CALFC_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define RXTX3__CALFC_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define RXTX3__CALFC_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field caltx */
#define RXTX3__CALTX__SHIFT                                                  24
#define RXTX3__CALTX__WIDTH                                                   1
#define RXTX3__CALTX__MASK                                          0x01000000U
#define RXTX3__CALTX__READ(src)        (((u_int32_t)(src) & 0x01000000U) >> 24)
#define RXTX3__CALTX__WRITE(src)       (((u_int32_t)(src) << 24) & 0x01000000U)
#define RXTX3__CALTX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define RXTX3__CALTX__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define RXTX3__CALTX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define RXTX3__CALTX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field caltx_ovr */
#define RXTX3__CALTX_OVR__SHIFT                                              25
#define RXTX3__CALTX_OVR__WIDTH                                               1
#define RXTX3__CALTX_OVR__MASK                                      0x02000000U
#define RXTX3__CALTX_OVR__READ(src)    (((u_int32_t)(src) & 0x02000000U) >> 25)
#define RXTX3__CALTX_OVR__WRITE(src)   (((u_int32_t)(src) << 25) & 0x02000000U)
#define RXTX3__CALTX_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define RXTX3__CALTX_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define RXTX3__CALTX_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define RXTX3__CALTX_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field caltxshift */
#define RXTX3__CALTXSHIFT__SHIFT                                             26
#define RXTX3__CALTXSHIFT__WIDTH                                              1
#define RXTX3__CALTXSHIFT__MASK                                     0x04000000U
#define RXTX3__CALTXSHIFT__READ(src)   (((u_int32_t)(src) & 0x04000000U) >> 26)
#define RXTX3__CALTXSHIFT__WRITE(src)  (((u_int32_t)(src) << 26) & 0x04000000U)
#define RXTX3__CALTXSHIFT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define RXTX3__CALTXSHIFT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define RXTX3__CALTXSHIFT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define RXTX3__CALTXSHIFT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field caltxshift_ovr */
#define RXTX3__CALTXSHIFT_OVR__SHIFT                                         27
#define RXTX3__CALTXSHIFT_OVR__WIDTH                                          1
#define RXTX3__CALTXSHIFT_OVR__MASK                                 0x08000000U
#define RXTX3__CALTXSHIFT_OVR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x08000000U) >> 27)
#define RXTX3__CALTXSHIFT_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define RXTX3__CALTXSHIFT_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define RXTX3__CALTXSHIFT_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define RXTX3__CALTXSHIFT_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field calpa */
#define RXTX3__CALPA__SHIFT                                                  28
#define RXTX3__CALPA__WIDTH                                                   1
#define RXTX3__CALPA__MASK                                          0x10000000U
#define RXTX3__CALPA__READ(src)        (((u_int32_t)(src) & 0x10000000U) >> 28)
#define RXTX3__CALPA__WRITE(src)       (((u_int32_t)(src) << 28) & 0x10000000U)
#define RXTX3__CALPA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define RXTX3__CALPA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define RXTX3__CALPA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define RXTX3__CALPA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field calpa_ovr */
#define RXTX3__CALPA_OVR__SHIFT                                              29
#define RXTX3__CALPA_OVR__WIDTH                                               1
#define RXTX3__CALPA_OVR__MASK                                      0x20000000U
#define RXTX3__CALPA_OVR__READ(src)    (((u_int32_t)(src) & 0x20000000U) >> 29)
#define RXTX3__CALPA_OVR__WRITE(src)   (((u_int32_t)(src) << 29) & 0x20000000U)
#define RXTX3__CALPA_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define RXTX3__CALPA_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define RXTX3__CALPA_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define RXTX3__CALPA_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field spuron */
#define RXTX3__SPURON__SHIFT                                                 30
#define RXTX3__SPURON__WIDTH                                                  1
#define RXTX3__SPURON__MASK                                         0x40000000U
#define RXTX3__SPURON__READ(src)       (((u_int32_t)(src) & 0x40000000U) >> 30)
#define RXTX3__SPURON__WRITE(src)      (((u_int32_t)(src) << 30) & 0x40000000U)
#define RXTX3__SPURON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define RXTX3__SPURON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define RXTX3__SPURON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define RXTX3__SPURON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field PAL_lockedEn */
#define RXTX3__PAL_LOCKEDEN__SHIFT                                           31
#define RXTX3__PAL_LOCKEDEN__WIDTH                                            1
#define RXTX3__PAL_LOCKEDEN__MASK                                   0x80000000U
#define RXTX3__PAL_LOCKEDEN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
#define RXTX3__PAL_LOCKEDEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define RXTX3__PAL_LOCKEDEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define RXTX3__PAL_LOCKEDEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define RXTX3__PAL_LOCKEDEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define RXTX3__TYPE                                                   u_int32_t
#define RXTX3__READ                                                 0xffffffffU
#define RXTX3__WRITE                                                0xffffffffU

#endif /* __RXTX3_MACRO__ */


/* macros for radio65_reg_map.ch0_RXTX3 */
#define INST_RADIO65_REG_MAP__CH0_RXTX3__NUM                                  1

/* macros for BlueprintGlobalNameSpace::RXTX4 */
#ifndef __RXTX4_MACRO__
#define __RXTX4_MACRO__

/* macros for field SPARE4 */
#define RXTX4__SPARE4__SHIFT                                                  0
#define RXTX4__SPARE4__WIDTH                                                 21
#define RXTX4__SPARE4__MASK                                         0x001fffffU
#define RXTX4__SPARE4__READ(src)                 (u_int32_t)(src) & 0x001fffffU
#define RXTX4__SPARE4__WRITE(src)              ((u_int32_t)(src) & 0x001fffffU)
#define RXTX4__SPARE4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001fffffU) | ((u_int32_t)(src) &\
                    0x001fffffU)
#define RXTX4__SPARE4__VERIFY(src)       (!(((u_int32_t)(src) & ~0x001fffffU)))

/* macros for field obdb2G_ssctrl */
#define RXTX4__OBDB2G_SSCTRL__SHIFT                                          21
#define RXTX4__OBDB2G_SSCTRL__WIDTH                                           1
#define RXTX4__OBDB2G_SSCTRL__MASK                                  0x00200000U
#define RXTX4__OBDB2G_SSCTRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00200000U) >> 21)
#define RXTX4__OBDB2G_SSCTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 21) & 0x00200000U)
#define RXTX4__OBDB2G_SSCTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define RXTX4__OBDB2G_SSCTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define RXTX4__OBDB2G_SSCTRL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define RXTX4__OBDB2G_SSCTRL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field obdb5G_ssctrl */
#define RXTX4__OBDB5G_SSCTRL__SHIFT                                          22
#define RXTX4__OBDB5G_SSCTRL__WIDTH                                           1
#define RXTX4__OBDB5G_SSCTRL__MASK                                  0x00400000U
#define RXTX4__OBDB5G_SSCTRL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00400000U) >> 22)
#define RXTX4__OBDB5G_SSCTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 22) & 0x00400000U)
#define RXTX4__OBDB5G_SSCTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define RXTX4__OBDB5G_SSCTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define RXTX4__OBDB5G_SSCTRL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define RXTX4__OBDB5G_SSCTRL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field testiq_on */
#define RXTX4__TESTIQ_ON__SHIFT                                              23
#define RXTX4__TESTIQ_ON__WIDTH                                               1
#define RXTX4__TESTIQ_ON__MASK                                      0x00800000U
#define RXTX4__TESTIQ_ON__READ(src)    (((u_int32_t)(src) & 0x00800000U) >> 23)
#define RXTX4__TESTIQ_ON__WRITE(src)   (((u_int32_t)(src) << 23) & 0x00800000U)
#define RXTX4__TESTIQ_ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define RXTX4__TESTIQ_ON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define RXTX4__TESTIQ_ON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define RXTX4__TESTIQ_ON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field testiq_bufen */
#define RXTX4__TESTIQ_BUFEN__SHIFT                                           24
#define RXTX4__TESTIQ_BUFEN__WIDTH                                            1
#define RXTX4__TESTIQ_BUFEN__MASK                                   0x01000000U
#define RXTX4__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
#define RXTX4__TESTIQ_BUFEN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define RXTX4__TESTIQ_BUFEN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define RXTX4__TESTIQ_BUFEN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define RXTX4__TESTIQ_BUFEN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field testiq_rsel */
#define RXTX4__TESTIQ_RSEL__SHIFT                                            25
#define RXTX4__TESTIQ_RSEL__WIDTH                                             1
#define RXTX4__TESTIQ_RSEL__MASK                                    0x02000000U
#define RXTX4__TESTIQ_RSEL__READ(src)  (((u_int32_t)(src) & 0x02000000U) >> 25)
#define RXTX4__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U)
#define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define RXTX4__TESTIQ_RSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define RXTX4__TESTIQ_RSEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define RXTX4__TESTIQ_RSEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field turboADC */
#define RXTX4__TURBOADC__SHIFT                                               26
#define RXTX4__TURBOADC__WIDTH                                                1
#define RXTX4__TURBOADC__MASK                                       0x04000000U
#define RXTX4__TURBOADC__READ(src)     (((u_int32_t)(src) & 0x04000000U) >> 26)
#define RXTX4__TURBOADC__WRITE(src)    (((u_int32_t)(src) << 26) & 0x04000000U)
#define RXTX4__TURBOADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define RXTX4__TURBOADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define RXTX4__TURBOADC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define RXTX4__TURBOADC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field turboADC_ovr */
#define RXTX4__TURBOADC_OVR__SHIFT                                           27
#define RXTX4__TURBOADC_OVR__WIDTH                                            1
#define RXTX4__TURBOADC_OVR__MASK                                   0x08000000U
#define RXTX4__TURBOADC_OVR__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
#define RXTX4__TURBOADC_OVR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 27) & 0x08000000U)
#define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define RXTX4__TURBOADC_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define RXTX4__TURBOADC_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define RXTX4__TURBOADC_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field thermOn */
#define RXTX4__THERMON__SHIFT                                                28
#define RXTX4__THERMON__WIDTH                                                 1
#define RXTX4__THERMON__MASK                                        0x10000000U
#define RXTX4__THERMON__READ(src)      (((u_int32_t)(src) & 0x10000000U) >> 28)
#define RXTX4__THERMON__WRITE(src)     (((u_int32_t)(src) << 28) & 0x10000000U)
#define RXTX4__THERMON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define RXTX4__THERMON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define RXTX4__THERMON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define RXTX4__THERMON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field thermOn_ovr */
#define RXTX4__THERMON_OVR__SHIFT                                            29
#define RXTX4__THERMON_OVR__WIDTH                                             1
#define RXTX4__THERMON_OVR__MASK                                    0x20000000U
#define RXTX4__THERMON_OVR__READ(src)  (((u_int32_t)(src) & 0x20000000U) >> 29)
#define RXTX4__THERMON_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
#define RXTX4__THERMON_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define RXTX4__THERMON_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define RXTX4__THERMON_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define RXTX4__THERMON_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field xlna_strength */
#define RXTX4__XLNA_STRENGTH__SHIFT                                          30
#define RXTX4__XLNA_STRENGTH__WIDTH                                           2
#define RXTX4__XLNA_STRENGTH__MASK                                  0xc0000000U
#define RXTX4__XLNA_STRENGTH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0xc0000000U) >> 30)
#define RXTX4__XLNA_STRENGTH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0xc0000000U)
#define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define RXTX4__XLNA_STRENGTH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define RXTX4__TYPE                                                   u_int32_t
#define RXTX4__READ                                                 0xffffffffU
#define RXTX4__WRITE                                                0xffffffffU

#endif /* __RXTX4_MACRO__ */


/* macros for radio65_reg_map.ch0_RXTX4 */
#define INST_RADIO65_REG_MAP__CH0_RXTX4__NUM                                  1

/* macros for BlueprintGlobalNameSpace::BB1 */
#ifndef __BB1_MACRO__
#define __BB1_MACRO__

/* macros for field I2V_CURR2X */
#define BB1__I2V_CURR2X__SHIFT                                                0
#define BB1__I2V_CURR2X__WIDTH                                                1
#define BB1__I2V_CURR2X__MASK                                       0x00000001U
#define BB1__I2V_CURR2X__READ(src)               (u_int32_t)(src) & 0x00000001U
#define BB1__I2V_CURR2X__WRITE(src)            ((u_int32_t)(src) & 0x00000001U)
#define BB1__I2V_CURR2X__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define BB1__I2V_CURR2X__VERIFY(src)     (!(((u_int32_t)(src) & ~0x00000001U)))
#define BB1__I2V_CURR2X__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define BB1__I2V_CURR2X__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field ENABLE_LOQ */
#define BB1__ENABLE_LOQ__SHIFT                                                1
#define BB1__ENABLE_LOQ__WIDTH                                                1
#define BB1__ENABLE_LOQ__MASK                                       0x00000002U
#define BB1__ENABLE_LOQ__READ(src)      (((u_int32_t)(src) & 0x00000002U) >> 1)
#define BB1__ENABLE_LOQ__WRITE(src)     (((u_int32_t)(src) << 1) & 0x00000002U)
#define BB1__ENABLE_LOQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define BB1__ENABLE_LOQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define BB1__ENABLE_LOQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define BB1__ENABLE_LOQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field FORCE_LOQ */
#define BB1__FORCE_LOQ__SHIFT                                                 2
#define BB1__FORCE_LOQ__WIDTH                                                 1
#define BB1__FORCE_LOQ__MASK                                        0x00000004U
#define BB1__FORCE_LOQ__READ(src)       (((u_int32_t)(src) & 0x00000004U) >> 2)
#define BB1__FORCE_LOQ__WRITE(src)      (((u_int32_t)(src) << 2) & 0x00000004U)
#define BB1__FORCE_LOQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define BB1__FORCE_LOQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define BB1__FORCE_LOQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define BB1__FORCE_LOQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field ENABLE_NOTCH */
#define BB1__ENABLE_NOTCH__SHIFT                                              3
#define BB1__ENABLE_NOTCH__WIDTH                                              1
#define BB1__ENABLE_NOTCH__MASK                                     0x00000008U
#define BB1__ENABLE_NOTCH__READ(src)    (((u_int32_t)(src) & 0x00000008U) >> 3)
#define BB1__ENABLE_NOTCH__WRITE(src)   (((u_int32_t)(src) << 3) & 0x00000008U)
#define BB1__ENABLE_NOTCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define BB1__ENABLE_NOTCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define BB1__ENABLE_NOTCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define BB1__ENABLE_NOTCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field FORCE_NOTCH */
#define BB1__FORCE_NOTCH__SHIFT                                               4
#define BB1__FORCE_NOTCH__WIDTH                                               1
#define BB1__FORCE_NOTCH__MASK                                      0x00000010U
#define BB1__FORCE_NOTCH__READ(src)     (((u_int32_t)(src) & 0x00000010U) >> 4)
#define BB1__FORCE_NOTCH__WRITE(src)    (((u_int32_t)(src) << 4) & 0x00000010U)
#define BB1__FORCE_NOTCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define BB1__FORCE_NOTCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define BB1__FORCE_NOTCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define BB1__FORCE_NOTCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field ENABLE_BIQUAD */
#define BB1__ENABLE_BIQUAD__SHIFT                                             5
#define BB1__ENABLE_BIQUAD__WIDTH                                             1
#define BB1__ENABLE_BIQUAD__MASK                                    0x00000020U
#define BB1__ENABLE_BIQUAD__READ(src)   (((u_int32_t)(src) & 0x00000020U) >> 5)
#define BB1__ENABLE_BIQUAD__WRITE(src)  (((u_int32_t)(src) << 5) & 0x00000020U)
#define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define BB1__ENABLE_BIQUAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define BB1__ENABLE_BIQUAD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define BB1__ENABLE_BIQUAD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field FORCE_BIQUAD */
#define BB1__FORCE_BIQUAD__SHIFT                                              6
#define BB1__FORCE_BIQUAD__WIDTH                                              1
#define BB1__FORCE_BIQUAD__MASK                                     0x00000040U
#define BB1__FORCE_BIQUAD__READ(src)    (((u_int32_t)(src) & 0x00000040U) >> 6)
#define BB1__FORCE_BIQUAD__WRITE(src)   (((u_int32_t)(src) << 6) & 0x00000040U)
#define BB1__FORCE_BIQUAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define BB1__FORCE_BIQUAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define BB1__FORCE_BIQUAD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define BB1__FORCE_BIQUAD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field ENABLE_OSDAC */
#define BB1__ENABLE_OSDAC__SHIFT                                              7
#define BB1__ENABLE_OSDAC__WIDTH                                              1
#define BB1__ENABLE_OSDAC__MASK                                     0x00000080U
#define BB1__ENABLE_OSDAC__READ(src)    (((u_int32_t)(src) & 0x00000080U) >> 7)
#define BB1__ENABLE_OSDAC__WRITE(src)   (((u_int32_t)(src) << 7) & 0x00000080U)
#define BB1__ENABLE_OSDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define BB1__ENABLE_OSDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define BB1__ENABLE_OSDAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define BB1__ENABLE_OSDAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field FORCE_OSDAC */
#define BB1__FORCE_OSDAC__SHIFT                                               8
#define BB1__FORCE_OSDAC__WIDTH                                               1
#define BB1__FORCE_OSDAC__MASK                                      0x00000100U
#define BB1__FORCE_OSDAC__READ(src)     (((u_int32_t)(src) & 0x00000100U) >> 8)
#define BB1__FORCE_OSDAC__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000100U)
#define BB1__FORCE_OSDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define BB1__FORCE_OSDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define BB1__FORCE_OSDAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define BB1__FORCE_OSDAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field ENABLE_V2I */
#define BB1__ENABLE_V2I__SHIFT                                                9
#define BB1__ENABLE_V2I__WIDTH                                                1
#define BB1__ENABLE_V2I__MASK                                       0x00000200U
#define BB1__ENABLE_V2I__READ(src)      (((u_int32_t)(src) & 0x00000200U) >> 9)
#define BB1__ENABLE_V2I__WRITE(src)     (((u_int32_t)(src) << 9) & 0x00000200U)
#define BB1__ENABLE_V2I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define BB1__ENABLE_V2I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define BB1__ENABLE_V2I__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define BB1__ENABLE_V2I__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field FORCE_V2I */
#define BB1__FORCE_V2I__SHIFT                                                10
#define BB1__FORCE_V2I__WIDTH                                                 1
#define BB1__FORCE_V2I__MASK                                        0x00000400U
#define BB1__FORCE_V2I__READ(src)      (((u_int32_t)(src) & 0x00000400U) >> 10)
#define BB1__FORCE_V2I__WRITE(src)     (((u_int32_t)(src) << 10) & 0x00000400U)
#define BB1__FORCE_V2I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define BB1__FORCE_V2I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define BB1__FORCE_V2I__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define BB1__FORCE_V2I__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field ENABLE_I2V */
#define BB1__ENABLE_I2V__SHIFT                                               11
#define BB1__ENABLE_I2V__WIDTH                                                1
#define BB1__ENABLE_I2V__MASK                                       0x00000800U
#define BB1__ENABLE_I2V__READ(src)     (((u_int32_t)(src) & 0x00000800U) >> 11)
#define BB1__ENABLE_I2V__WRITE(src)    (((u_int32_t)(src) << 11) & 0x00000800U)
#define BB1__ENABLE_I2V__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define BB1__ENABLE_I2V__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define BB1__ENABLE_I2V__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define BB1__ENABLE_I2V__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field FORCE_I2V */
#define BB1__FORCE_I2V__SHIFT                                                12
#define BB1__FORCE_I2V__WIDTH                                                 1
#define BB1__FORCE_I2V__MASK                                        0x00001000U
#define BB1__FORCE_I2V__READ(src)      (((u_int32_t)(src) & 0x00001000U) >> 12)
#define BB1__FORCE_I2V__WRITE(src)     (((u_int32_t)(src) << 12) & 0x00001000U)
#define BB1__FORCE_I2V__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define BB1__FORCE_I2V__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define BB1__FORCE_I2V__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define BB1__FORCE_I2V__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field CMSEL */
#define BB1__CMSEL__SHIFT                                                    13
#define BB1__CMSEL__WIDTH                                                     3
#define BB1__CMSEL__MASK                                            0x0000e000U
#define BB1__CMSEL__READ(src)          (((u_int32_t)(src) & 0x0000e000U) >> 13)
#define BB1__CMSEL__WRITE(src)         (((u_int32_t)(src) << 13) & 0x0000e000U)
#define BB1__CMSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0000e000U)
#define BB1__CMSEL__VERIFY(src)  (!((((u_int32_t)(src) << 13) & ~0x0000e000U)))

/* macros for field ATBSEL */
#define BB1__ATBSEL__SHIFT                                                   16
#define BB1__ATBSEL__WIDTH                                                    2
#define BB1__ATBSEL__MASK                                           0x00030000U
#define BB1__ATBSEL__READ(src)         (((u_int32_t)(src) & 0x00030000U) >> 16)
#define BB1__ATBSEL__WRITE(src)        (((u_int32_t)(src) << 16) & 0x00030000U)
#define BB1__ATBSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00030000U) | (((u_int32_t)(src) <<\
                    16) & 0x00030000U)
#define BB1__ATBSEL__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x00030000U)))

/* macros for field PD_OSDAC_CALTX_CALPA */
#define BB1__PD_OSDAC_CALTX_CALPA__SHIFT                                     18
#define BB1__PD_OSDAC_CALTX_CALPA__WIDTH                                      1
#define BB1__PD_OSDAC_CALTX_CALPA__MASK                             0x00040000U
#define BB1__PD_OSDAC_CALTX_CALPA__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00040000U) >> 18)
#define BB1__PD_OSDAC_CALTX_CALPA__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 18) & 0x00040000U)
#define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define BB1__PD_OSDAC_CALTX_CALPA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define BB1__PD_OSDAC_CALTX_CALPA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define BB1__PD_OSDAC_CALTX_CALPA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field OFSTCORRI2VQ */
#define BB1__OFSTCORRI2VQ__SHIFT                                             19
#define BB1__OFSTCORRI2VQ__WIDTH                                              5
#define BB1__OFSTCORRI2VQ__MASK                                     0x00f80000U
#define BB1__OFSTCORRI2VQ__READ(src)   (((u_int32_t)(src) & 0x00f80000U) >> 19)
#define BB1__OFSTCORRI2VQ__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00f80000U)
#define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f80000U) | (((u_int32_t)(src) <<\
                    19) & 0x00f80000U)
#define BB1__OFSTCORRI2VQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00f80000U)))

/* macros for field OFSTCORRI2VI */
#define BB1__OFSTCORRI2VI__SHIFT                                             24
#define BB1__OFSTCORRI2VI__WIDTH                                              5
#define BB1__OFSTCORRI2VI__MASK                                     0x1f000000U
#define BB1__OFSTCORRI2VI__READ(src)   (((u_int32_t)(src) & 0x1f000000U) >> 24)
#define BB1__OFSTCORRI2VI__WRITE(src)  (((u_int32_t)(src) << 24) & 0x1f000000U)
#define BB1__OFSTCORRI2VI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x1f000000U)
#define BB1__OFSTCORRI2VI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x1f000000U)))

/* macros for field LOCALOFFSET */
#define BB1__LOCALOFFSET__SHIFT                                              29
#define BB1__LOCALOFFSET__WIDTH                                               1
#define BB1__LOCALOFFSET__MASK                                      0x20000000U
#define BB1__LOCALOFFSET__READ(src)    (((u_int32_t)(src) & 0x20000000U) >> 29)
#define BB1__LOCALOFFSET__WRITE(src)   (((u_int32_t)(src) << 29) & 0x20000000U)
#define BB1__LOCALOFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define BB1__LOCALOFFSET__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define BB1__LOCALOFFSET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define BB1__LOCALOFFSET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field RANGE_OSDAC */
#define BB1__RANGE_OSDAC__SHIFT                                              30
#define BB1__RANGE_OSDAC__WIDTH                                               2
#define BB1__RANGE_OSDAC__MASK                                      0xc0000000U
#define BB1__RANGE_OSDAC__READ(src)    (((u_int32_t)(src) & 0xc0000000U) >> 30)
#define BB1__RANGE_OSDAC__WRITE(src)   (((u_int32_t)(src) << 30) & 0xc0000000U)
#define BB1__RANGE_OSDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define BB1__RANGE_OSDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define BB1__TYPE                                                     u_int32_t
#define BB1__READ                                                   0xffffffffU
#define BB1__WRITE                                                  0xffffffffU

#endif /* __BB1_MACRO__ */


/* macros for radio65_reg_map.ch0_BB1 */
#define INST_RADIO65_REG_MAP__CH0_BB1__NUM                                    1

/* macros for BlueprintGlobalNameSpace::BB2 */
#ifndef __BB2_MACRO__
#define __BB2_MACRO__

/* macros for field SPARE */
#define BB2__SPARE__SHIFT                                                     0
#define BB2__SPARE__WIDTH                                                     4
#define BB2__SPARE__MASK                                            0x0000000fU
#define BB2__SPARE__READ(src)                    (u_int32_t)(src) & 0x0000000fU
#define BB2__SPARE__WRITE(src)                 ((u_int32_t)(src) & 0x0000000fU)
#define BB2__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define BB2__SPARE__VERIFY(src)          (!(((u_int32_t)(src) & ~0x0000000fU)))

/* macros for field MXR_HIGHGAINMASK */
#define BB2__MXR_HIGHGAINMASK__SHIFT                                          4
#define BB2__MXR_HIGHGAINMASK__WIDTH                                          4
#define BB2__MXR_HIGHGAINMASK__MASK                                 0x000000f0U
#define BB2__MXR_HIGHGAINMASK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define BB2__MXR_HIGHGAINMASK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define BB2__MXR_HIGHGAINMASK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field SEL_TEST */
#define BB2__SEL_TEST__SHIFT                                                  8
#define BB2__SEL_TEST__WIDTH                                                  2
#define BB2__SEL_TEST__MASK                                         0x00000300U
#define BB2__SEL_TEST__READ(src)        (((u_int32_t)(src) & 0x00000300U) >> 8)
#define BB2__SEL_TEST__WRITE(src)       (((u_int32_t)(src) << 8) & 0x00000300U)
#define BB2__SEL_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define BB2__SEL_TEST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field RCFILTER_CAP */
#define BB2__RCFILTER_CAP__SHIFT                                             10
#define BB2__RCFILTER_CAP__WIDTH                                              5
#define BB2__RCFILTER_CAP__MASK                                     0x00007c00U
#define BB2__RCFILTER_CAP__READ(src)   (((u_int32_t)(src) & 0x00007c00U) >> 10)
#define BB2__RCFILTER_CAP__WRITE(src)  (((u_int32_t)(src) << 10) & 0x00007c00U)
#define BB2__RCFILTER_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007c00U) | (((u_int32_t)(src) <<\
                    10) & 0x00007c00U)
#define BB2__RCFILTER_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00007c00U)))

/* macros for field OVERRIDE_RCFILTER_CAP */
#define BB2__OVERRIDE_RCFILTER_CAP__SHIFT                                    15
#define BB2__OVERRIDE_RCFILTER_CAP__WIDTH                                     1
#define BB2__OVERRIDE_RCFILTER_CAP__MASK                            0x00008000U
#define BB2__OVERRIDE_RCFILTER_CAP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define BB2__OVERRIDE_RCFILTER_CAP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define BB2__OVERRIDE_RCFILTER_CAP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define BB2__OVERRIDE_RCFILTER_CAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define BB2__OVERRIDE_RCFILTER_CAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field FNOTCH */
#define BB2__FNOTCH__SHIFT                                                   16
#define BB2__FNOTCH__WIDTH                                                    4
#define BB2__FNOTCH__MASK                                           0x000f0000U
#define BB2__FNOTCH__READ(src)         (((u_int32_t)(src) & 0x000f0000U) >> 16)
#define BB2__FNOTCH__WRITE(src)        (((u_int32_t)(src) << 16) & 0x000f0000U)
#define BB2__FNOTCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define BB2__FNOTCH__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x000f0000U)))

/* macros for field OVERRIDE_FNOTCH */
#define BB2__OVERRIDE_FNOTCH__SHIFT                                          20
#define BB2__OVERRIDE_FNOTCH__WIDTH                                           1
#define BB2__OVERRIDE_FNOTCH__MASK                                  0x00100000U
#define BB2__OVERRIDE_FNOTCH__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00100000U) >> 20)
#define BB2__OVERRIDE_FNOTCH__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 20) & 0x00100000U)
#define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define BB2__OVERRIDE_FNOTCH__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define BB2__OVERRIDE_FNOTCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define BB2__OVERRIDE_FNOTCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field FILTERFC */
#define BB2__FILTERFC__SHIFT                                                 21
#define BB2__FILTERFC__WIDTH                                                  5
#define BB2__FILTERFC__MASK                                         0x03e00000U
#define BB2__FILTERFC__READ(src)       (((u_int32_t)(src) & 0x03e00000U) >> 21)
#define BB2__FILTERFC__WRITE(src)      (((u_int32_t)(src) << 21) & 0x03e00000U)
#define BB2__FILTERFC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x03e00000U)
#define BB2__FILTERFC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x03e00000U)))

/* macros for field OVERRIDE_FILTERFC */
#define BB2__OVERRIDE_FILTERFC__SHIFT                                        26
#define BB2__OVERRIDE_FILTERFC__WIDTH                                         1
#define BB2__OVERRIDE_FILTERFC__MASK                                0x04000000U
#define BB2__OVERRIDE_FILTERFC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x04000000U) >> 26)
#define BB2__OVERRIDE_FILTERFC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define BB2__OVERRIDE_FILTERFC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define BB2__OVERRIDE_FILTERFC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define BB2__OVERRIDE_FILTERFC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field I2V2RXOUT_EN */
#define BB2__I2V2RXOUT_EN__SHIFT                                             27
#define BB2__I2V2RXOUT_EN__WIDTH                                              1
#define BB2__I2V2RXOUT_EN__MASK                                     0x08000000U
#define BB2__I2V2RXOUT_EN__READ(src)   (((u_int32_t)(src) & 0x08000000U) >> 27)
#define BB2__I2V2RXOUT_EN__WRITE(src)  (((u_int32_t)(src) << 27) & 0x08000000U)
#define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define BB2__I2V2RXOUT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define BB2__I2V2RXOUT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define BB2__I2V2RXOUT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field BQ2RXOUT_EN */
#define BB2__BQ2RXOUT_EN__SHIFT                                              28
#define BB2__BQ2RXOUT_EN__WIDTH                                               1
#define BB2__BQ2RXOUT_EN__MASK                                      0x10000000U
#define BB2__BQ2RXOUT_EN__READ(src)    (((u_int32_t)(src) & 0x10000000U) >> 28)
#define BB2__BQ2RXOUT_EN__WRITE(src)   (((u_int32_t)(src) << 28) & 0x10000000U)
#define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define BB2__BQ2RXOUT_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define BB2__BQ2RXOUT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define BB2__BQ2RXOUT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field RXIN2I2V_EN */
#define BB2__RXIN2I2V_EN__SHIFT                                              29
#define BB2__RXIN2I2V_EN__WIDTH                                               1
#define BB2__RXIN2I2V_EN__MASK                                      0x20000000U
#define BB2__RXIN2I2V_EN__READ(src)    (((u_int32_t)(src) & 0x20000000U) >> 29)
#define BB2__RXIN2I2V_EN__WRITE(src)   (((u_int32_t)(src) << 29) & 0x20000000U)
#define BB2__RXIN2I2V_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define BB2__RXIN2I2V_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define BB2__RXIN2I2V_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define BB2__RXIN2I2V_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field RXIN2BQ_EN */
#define BB2__RXIN2BQ_EN__SHIFT                                               30
#define BB2__RXIN2BQ_EN__WIDTH                                                1
#define BB2__RXIN2BQ_EN__MASK                                       0x40000000U
#define BB2__RXIN2BQ_EN__READ(src)     (((u_int32_t)(src) & 0x40000000U) >> 30)
#define BB2__RXIN2BQ_EN__WRITE(src)    (((u_int32_t)(src) << 30) & 0x40000000U)
#define BB2__RXIN2BQ_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define BB2__RXIN2BQ_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define BB2__RXIN2BQ_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define BB2__RXIN2BQ_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field SWITCH_OVERRIDE */
#define BB2__SWITCH_OVERRIDE__SHIFT                                          31
#define BB2__SWITCH_OVERRIDE__WIDTH                                           1
#define BB2__SWITCH_OVERRIDE__MASK                                  0x80000000U
#define BB2__SWITCH_OVERRIDE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define BB2__SWITCH_OVERRIDE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define BB2__SWITCH_OVERRIDE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define BB2__SWITCH_OVERRIDE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define BB2__SWITCH_OVERRIDE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define BB2__TYPE                                                     u_int32_t
#define BB2__READ                                                   0xffffffffU
#define BB2__WRITE                                                  0xffffffffU

#endif /* __BB2_MACRO__ */


/* macros for radio65_reg_map.ch0_BB2 */
#define INST_RADIO65_REG_MAP__CH0_BB2__NUM                                    1

/* macros for BlueprintGlobalNameSpace::BB3 */
#ifndef __BB3_MACRO__
#define __BB3_MACRO__

/* macros for field SPARE */
#define BB3__SPARE__SHIFT                                                     0
#define BB3__SPARE__WIDTH                                                     8
#define BB3__SPARE__MASK                                            0x000000ffU
#define BB3__SPARE__READ(src)                    (u_int32_t)(src) & 0x000000ffU
#define BB3__SPARE__WRITE(src)                 ((u_int32_t)(src) & 0x000000ffU)
#define BB3__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((u_int32_t)(src) &\
                    0x000000ffU)
#define BB3__SPARE__VERIFY(src)          (!(((u_int32_t)(src) & ~0x000000ffU)))

/* macros for field SEL_OFST_READBK */
#define BB3__SEL_OFST_READBK__SHIFT                                           8
#define BB3__SEL_OFST_READBK__WIDTH                                           2
#define BB3__SEL_OFST_READBK__MASK                                  0x00000300U
#define BB3__SEL_OFST_READBK__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
#define BB3__SEL_OFST_READBK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000300U)
#define BB3__SEL_OFST_READBK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((u_int32_t)(src) <<\
                    8) & 0x00000300U)
#define BB3__SEL_OFST_READBK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field OVERRIDE_RXONLY_FILTERFC */
#define BB3__OVERRIDE_RXONLY_FILTERFC__SHIFT                                 10
#define BB3__OVERRIDE_RXONLY_FILTERFC__WIDTH                                  1
#define BB3__OVERRIDE_RXONLY_FILTERFC__MASK                         0x00000400U
#define BB3__OVERRIDE_RXONLY_FILTERFC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define BB3__OVERRIDE_RXONLY_FILTERFC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define BB3__OVERRIDE_RXONLY_FILTERFC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define BB3__OVERRIDE_RXONLY_FILTERFC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define BB3__OVERRIDE_RXONLY_FILTERFC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field RXONLY_FILTERFC */
#define BB3__RXONLY_FILTERFC__SHIFT                                          11
#define BB3__RXONLY_FILTERFC__WIDTH                                           5
#define BB3__RXONLY_FILTERFC__MASK                                  0x0000f800U
#define BB3__RXONLY_FILTERFC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x0000f800U) >> 11)
#define BB3__RXONLY_FILTERFC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x0000f800U)
#define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f800U) | (((u_int32_t)(src) <<\
                    11) & 0x0000f800U)
#define BB3__RXONLY_FILTERFC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x0000f800U)))

/* macros for field FILTERFC */
#define BB3__FILTERFC__SHIFT                                                 16
#define BB3__FILTERFC__WIDTH                                                  5
#define BB3__FILTERFC__MASK                                         0x001f0000U
#define BB3__FILTERFC__READ(src)       (((u_int32_t)(src) & 0x001f0000U) >> 16)

/* macros for field OFSTCORRI2VQ */
#define BB3__OFSTCORRI2VQ__SHIFT                                             21
#define BB3__OFSTCORRI2VQ__WIDTH                                              5
#define BB3__OFSTCORRI2VQ__MASK                                     0x03e00000U
#define BB3__OFSTCORRI2VQ__READ(src)   (((u_int32_t)(src) & 0x03e00000U) >> 21)

/* macros for field OFSTCORRI2VI */
#define BB3__OFSTCORRI2VI__SHIFT                                             26
#define BB3__OFSTCORRI2VI__WIDTH                                              5
#define BB3__OFSTCORRI2VI__MASK                                     0x7c000000U
#define BB3__OFSTCORRI2VI__READ(src)   (((u_int32_t)(src) & 0x7c000000U) >> 26)

/* macros for field EN_TXBBCONSTCUR */
#define BB3__EN_TXBBCONSTCUR__SHIFT                                          31
#define BB3__EN_TXBBCONSTCUR__WIDTH                                           1
#define BB3__EN_TXBBCONSTCUR__MASK                                  0x80000000U
#define BB3__EN_TXBBCONSTCUR__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x80000000U) >> 31)
#define BB3__EN_TXBBCONSTCUR__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define BB3__EN_TXBBCONSTCUR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define BB3__EN_TXBBCONSTCUR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define BB3__EN_TXBBCONSTCUR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define BB3__TYPE                                                     u_int32_t
#define BB3__READ                                                   0xffffffffU
#define BB3__WRITE                                                  0xffffffffU

#endif /* __BB3_MACRO__ */


/* macros for radio65_reg_map.ch0_BB3 */
#define INST_RADIO65_REG_MAP__CH0_BB3__NUM                                    1

/* macros for BlueprintGlobalNameSpace::DPLL */
#ifndef __DPLL_MACRO__
#define __DPLL_MACRO__

/* macros for field nfrac */
#define DPLL__NFRAC__SHIFT                                                    0
#define DPLL__NFRAC__WIDTH                                                   18
#define DPLL__NFRAC__MASK                                           0x0003ffffU
#define DPLL__NFRAC__READ(src)                   (u_int32_t)(src) & 0x0003ffffU
#define DPLL__NFRAC__WRITE(src)                ((u_int32_t)(src) & 0x0003ffffU)
#define DPLL__NFRAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003ffffU) | ((u_int32_t)(src) &\
                    0x0003ffffU)
#define DPLL__NFRAC__VERIFY(src)         (!(((u_int32_t)(src) & ~0x0003ffffU)))

/* macros for field nint */
#define DPLL__NINT__SHIFT                                                    18
#define DPLL__NINT__WIDTH                                                     9
#define DPLL__NINT__MASK                                            0x07fc0000U
#define DPLL__NINT__READ(src)          (((u_int32_t)(src) & 0x07fc0000U) >> 18)
#define DPLL__NINT__WRITE(src)         (((u_int32_t)(src) << 18) & 0x07fc0000U)
#define DPLL__NINT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07fc0000U) | (((u_int32_t)(src) <<\
                    18) & 0x07fc0000U)
#define DPLL__NINT__VERIFY(src)  (!((((u_int32_t)(src) << 18) & ~0x07fc0000U)))

/* macros for field refdiv */
#define DPLL__REFDIV__SHIFT                                                  27
#define DPLL__REFDIV__WIDTH                                                   5
#define DPLL__REFDIV__MASK                                          0xf8000000U
#define DPLL__REFDIV__READ(src)        (((u_int32_t)(src) & 0xf8000000U) >> 27)
#define DPLL__REFDIV__WRITE(src)       (((u_int32_t)(src) << 27) & 0xf8000000U)
#define DPLL__REFDIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf8000000U) | (((u_int32_t)(src) <<\
                    27) & 0xf8000000U)
#define DPLL__REFDIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0xf8000000U)))
#define DPLL__TYPE                                                    u_int32_t
#define DPLL__READ                                                  0xffffffffU
#define DPLL__WRITE                                                 0xffffffffU

#endif /* __DPLL_MACRO__ */


/* macros for radio65_reg_map.ch0_BB_PLL */
#define INST_RADIO65_REG_MAP__CH0_BB_PLL__NUM                                 1

/* macros for BlueprintGlobalNameSpace::DPLL2 */
#ifndef __DPLL2_MACRO__
#define __DPLL2_MACRO__

/* macros for field testinMSB */
#define DPLL2__TESTINMSB__SHIFT                                               0
#define DPLL2__TESTINMSB__WIDTH                                               7
#define DPLL2__TESTINMSB__MASK                                      0x0000007fU
#define DPLL2__TESTINMSB__READ(src)              (u_int32_t)(src) & 0x0000007fU
#define DPLL2__TESTINMSB__WRITE(src)           ((u_int32_t)(src) & 0x0000007fU)
#define DPLL2__TESTINMSB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define DPLL2__TESTINMSB__VERIFY(src)    (!(((u_int32_t)(src) & ~0x0000007fU)))

/* macros for field delta */
#define DPLL2__DELTA__SHIFT                                                   7
#define DPLL2__DELTA__WIDTH                                                   6
#define DPLL2__DELTA__MASK                                          0x00001f80U
#define DPLL2__DELTA__READ(src)         (((u_int32_t)(src) & 0x00001f80U) >> 7)
#define DPLL2__DELTA__WRITE(src)        (((u_int32_t)(src) << 7) & 0x00001f80U)
#define DPLL2__DELTA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f80U) | (((u_int32_t)(src) <<\
                    7) & 0x00001f80U)
#define DPLL2__DELTA__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00001f80U)))

/* macros for field outdiv */
#define DPLL2__OUTDIV__SHIFT                                                 13
#define DPLL2__OUTDIV__WIDTH                                                  3
#define DPLL2__OUTDIV__MASK                                         0x0000e000U
#define DPLL2__OUTDIV__READ(src)       (((u_int32_t)(src) & 0x0000e000U) >> 13)
#define DPLL2__OUTDIV__WRITE(src)      (((u_int32_t)(src) << 13) & 0x0000e000U)
#define DPLL2__OUTDIV__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000e000U) | (((u_int32_t)(src) <<\
                    13) & 0x0000e000U)
#define DPLL2__OUTDIV__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x0000e000U)))

/* macros for field pll_pwd */
#define DPLL2__PLL_PWD__SHIFT                                                16
#define DPLL2__PLL_PWD__WIDTH                                                 1
#define DPLL2__PLL_PWD__MASK                                        0x00010000U
#define DPLL2__PLL_PWD__READ(src)      (((u_int32_t)(src) & 0x00010000U) >> 16)
#define DPLL2__PLL_PWD__WRITE(src)     (((u_int32_t)(src) << 16) & 0x00010000U)
#define DPLL2__PLL_PWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define DPLL2__PLL_PWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define DPLL2__PLL_PWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define DPLL2__PLL_PWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)

/* macros for field sel_1sdm */
#define DPLL2__SEL_1SDM__SHIFT                                               17
#define DPLL2__SEL_1SDM__WIDTH                                                1
#define DPLL2__SEL_1SDM__MASK                                       0x00020000U
#define DPLL2__SEL_1SDM__READ(src)     (((u_int32_t)(src) & 0x00020000U) >> 17)
#define DPLL2__SEL_1SDM__WRITE(src)    (((u_int32_t)(src) << 17) & 0x00020000U)
#define DPLL2__SEL_1SDM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((u_int32_t)(src) <<\
                    17) & 0x00020000U)
#define DPLL2__SEL_1SDM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00020000U)))
#define DPLL2__SEL_1SDM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(1) << 17)
#define DPLL2__SEL_1SDM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((u_int32_t)(0) << 17)

/* macros for field en_negtrig */
#define DPLL2__EN_NEGTRIG__SHIFT                                             18
#define DPLL2__EN_NEGTRIG__WIDTH                                              1
#define DPLL2__EN_NEGTRIG__MASK                                     0x00040000U
#define DPLL2__EN_NEGTRIG__READ(src)   (((u_int32_t)(src) & 0x00040000U) >> 18)
#define DPLL2__EN_NEGTRIG__WRITE(src)  (((u_int32_t)(src) << 18) & 0x00040000U)
#define DPLL2__EN_NEGTRIG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define DPLL2__EN_NEGTRIG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define DPLL2__EN_NEGTRIG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define DPLL2__EN_NEGTRIG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field kd */
#define DPLL2__KD__SHIFT                                                     19
#define DPLL2__KD__WIDTH                                                      7
#define DPLL2__KD__MASK                                             0x03f80000U
#define DPLL2__KD__READ(src)           (((u_int32_t)(src) & 0x03f80000U) >> 19)
#define DPLL2__KD__WRITE(src)          (((u_int32_t)(src) << 19) & 0x03f80000U)
#define DPLL2__KD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03f80000U) | (((u_int32_t)(src) <<\
                    19) & 0x03f80000U)
#define DPLL2__KD__VERIFY(src)   (!((((u_int32_t)(src) << 19) & ~0x03f80000U)))

/* macros for field ki */
#define DPLL2__KI__SHIFT                                                     26
#define DPLL2__KI__WIDTH                                                      4
#define DPLL2__KI__MASK                                             0x3c000000U
#define DPLL2__KI__READ(src)           (((u_int32_t)(src) & 0x3c000000U) >> 26)
#define DPLL2__KI__WRITE(src)          (((u_int32_t)(src) << 26) & 0x3c000000U)
#define DPLL2__KI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x3c000000U)
#define DPLL2__KI__VERIFY(src)   (!((((u_int32_t)(src) << 26) & ~0x3c000000U)))

/* macros for field local_pll */
#define DPLL2__LOCAL_PLL__SHIFT                                              30
#define DPLL2__LOCAL_PLL__WIDTH                                               1
#define DPLL2__LOCAL_PLL__MASK                                      0x40000000U
#define DPLL2__LOCAL_PLL__READ(src)    (((u_int32_t)(src) & 0x40000000U) >> 30)
#define DPLL2__LOCAL_PLL__WRITE(src)   (((u_int32_t)(src) << 30) & 0x40000000U)
#define DPLL2__LOCAL_PLL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define DPLL2__LOCAL_PLL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define DPLL2__LOCAL_PLL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define DPLL2__LOCAL_PLL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field range */
#define DPLL2__RANGE__SHIFT                                                  31
#define DPLL2__RANGE__WIDTH                                                   1
#define DPLL2__RANGE__MASK                                          0x80000000U
#define DPLL2__RANGE__READ(src)        (((u_int32_t)(src) & 0x80000000U) >> 31)
#define DPLL2__RANGE__WRITE(src)       (((u_int32_t)(src) << 31) & 0x80000000U)
#define DPLL2__RANGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define DPLL2__RANGE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define DPLL2__RANGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define DPLL2__RANGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define DPLL2__TYPE                                                   u_int32_t
#define DPLL2__READ                                                 0xffffffffU
#define DPLL2__WRITE                                                0xffffffffU

#endif /* __DPLL2_MACRO__ */


/* macros for radio65_reg_map.ch0_BB_PLL2 */
#define INST_RADIO65_REG_MAP__CH0_BB_PLL2__NUM                                1

/* macros for BlueprintGlobalNameSpace::DPLL3 */
#ifndef __DPLL3_MACRO__
#define __DPLL3_MACRO__

/* macros for field testinLSB */
#define DPLL3__TESTINLSB__SHIFT                                               0
#define DPLL3__TESTINLSB__WIDTH                                               3
#define DPLL3__TESTINLSB__MASK                                      0x00000007U
#define DPLL3__TESTINLSB__READ(src)              (u_int32_t)(src) & 0x00000007U
#define DPLL3__TESTINLSB__WRITE(src)           ((u_int32_t)(src) & 0x00000007U)
#define DPLL3__TESTINLSB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((u_int32_t)(src) &\
                    0x00000007U)
#define DPLL3__TESTINLSB__VERIFY(src)    (!(((u_int32_t)(src) & ~0x00000007U)))

/* macros for field sqsum_dvc */
#define DPLL3__SQSUM_DVC__SHIFT                                               3
#define DPLL3__SQSUM_DVC__WIDTH                                              20
#define DPLL3__SQSUM_DVC__MASK                                      0x007ffff8U
#define DPLL3__SQSUM_DVC__READ(src)     (((u_int32_t)(src) & 0x007ffff8U) >> 3)

/* macros for field phase_shift */
#define DPLL3__PHASE_SHIFT__SHIFT                                            23
#define DPLL3__PHASE_SHIFT__WIDTH                                             7
#define DPLL3__PHASE_SHIFT__MASK                                    0x3f800000U
#define DPLL3__PHASE_SHIFT__READ(src)  (((u_int32_t)(src) & 0x3f800000U) >> 23)
#define DPLL3__PHASE_SHIFT__WRITE(src) (((u_int32_t)(src) << 23) & 0x3f800000U)
#define DPLL3__PHASE_SHIFT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f800000U) | (((u_int32_t)(src) <<\
                    23) & 0x3f800000U)
#define DPLL3__PHASE_SHIFT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x3f800000U)))

/* macros for field do_meas */
#define DPLL3__DO_MEAS__SHIFT                                                30
#define DPLL3__DO_MEAS__WIDTH                                                 1
#define DPLL3__DO_MEAS__MASK                                        0x40000000U
#define DPLL3__DO_MEAS__READ(src)      (((u_int32_t)(src) & 0x40000000U) >> 30)
#define DPLL3__DO_MEAS__WRITE(src)     (((u_int32_t)(src) << 30) & 0x40000000U)
#define DPLL3__DO_MEAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define DPLL3__DO_MEAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define DPLL3__DO_MEAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define DPLL3__DO_MEAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field meas_at_txon */
#define DPLL3__MEAS_AT_TXON__SHIFT                                           31
#define DPLL3__MEAS_AT_TXON__WIDTH                                            1
#define DPLL3__MEAS_AT_TXON__MASK                                   0x80000000U
#define DPLL3__MEAS_AT_TXON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
#define DPLL3__MEAS_AT_TXON__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define DPLL3__MEAS_AT_TXON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define DPLL3__MEAS_AT_TXON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define DPLL3__MEAS_AT_TXON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define DPLL3__MEAS_AT_TXON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define DPLL3__TYPE                                                   u_int32_t
#define DPLL3__READ                                                 0xffffffffU
#define DPLL3__WRITE                                                0xffffffffU

#endif /* __DPLL3_MACRO__ */


/* macros for radio65_reg_map.ch0_BB_PLL3 */
#define INST_RADIO65_REG_MAP__CH0_BB_PLL3__NUM                                1

/* macros for BlueprintGlobalNameSpace::DPLL4 */
#ifndef __DPLL4_MACRO__
#define __DPLL4_MACRO__

/* macros for field SPARE */
#define DPLL4__SPARE__SHIFT                                                   0
#define DPLL4__SPARE__WIDTH                                                   1
#define DPLL4__SPARE__MASK                                          0x00000001U
#define DPLL4__SPARE__READ(src)                  (u_int32_t)(src) & 0x00000001U
#define DPLL4__SPARE__WRITE(src)               ((u_int32_t)(src) & 0x00000001U)
#define DPLL4__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define DPLL4__SPARE__VERIFY(src)        (!(((u_int32_t)(src) & ~0x00000001U)))
#define DPLL4__SPARE__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
#define DPLL4__SPARE__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)

/* macros for field sel_count */
#define DPLL4__SEL_COUNT__SHIFT                                               1
#define DPLL4__SEL_COUNT__WIDTH                                               1
#define DPLL4__SEL_COUNT__MASK                                      0x00000002U
#define DPLL4__SEL_COUNT__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
#define DPLL4__SEL_COUNT__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
#define DPLL4__SEL_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define DPLL4__SEL_COUNT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define DPLL4__SEL_COUNT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define DPLL4__SEL_COUNT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field reset_test */
#define DPLL4__RESET_TEST__SHIFT                                              2
#define DPLL4__RESET_TEST__WIDTH                                              1
#define DPLL4__RESET_TEST__MASK                                     0x00000004U
#define DPLL4__RESET_TEST__READ(src)    (((u_int32_t)(src) & 0x00000004U) >> 2)
#define DPLL4__RESET_TEST__WRITE(src)   (((u_int32_t)(src) << 2) & 0x00000004U)
#define DPLL4__RESET_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define DPLL4__RESET_TEST__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define DPLL4__RESET_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define DPLL4__RESET_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field meas_done */
#define DPLL4__MEAS_DONE__SHIFT                                               3
#define DPLL4__MEAS_DONE__WIDTH                                               1
#define DPLL4__MEAS_DONE__MASK                                      0x00000008U
#define DPLL4__MEAS_DONE__READ(src)     (((u_int32_t)(src) & 0x00000008U) >> 3)
#define DPLL4__MEAS_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define DPLL4__MEAS_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field vc_meas0 */
#define DPLL4__VC_MEAS0__SHIFT                                                4
#define DPLL4__VC_MEAS0__WIDTH                                               17
#define DPLL4__VC_MEAS0__MASK                                       0x001ffff0U
#define DPLL4__VC_MEAS0__READ(src)      (((u_int32_t)(src) & 0x001ffff0U) >> 4)

/* macros for field mean_dvc */
#define DPLL4__MEAN_DVC__SHIFT                                               21
#define DPLL4__MEAN_DVC__WIDTH                                               11
#define DPLL4__MEAN_DVC__MASK                                       0xffe00000U
#define DPLL4__MEAN_DVC__READ(src)     (((u_int32_t)(src) & 0xffe00000U) >> 21)
#define DPLL4__TYPE                                                   u_int32_t
#define DPLL4__READ                                                 0xffffffffU
#define DPLL4__WRITE                                                0xffffffffU

#endif /* __DPLL4_MACRO__ */


/* macros for radio65_reg_map.ch0_BB_PLL4 */
#define INST_RADIO65_REG_MAP__CH0_BB_PLL4__NUM                                1

/* macros for radio65_reg_map.ch0_CPU_PLL */
#define INST_RADIO65_REG_MAP__CH0_CPU_PLL__NUM                                1

/* macros for radio65_reg_map.ch0_CPU_PLL2 */
#define INST_RADIO65_REG_MAP__CH0_CPU_PLL2__NUM                               1

/* macros for radio65_reg_map.ch0_CPU_PLL3 */
#define INST_RADIO65_REG_MAP__CH0_CPU_PLL3__NUM                               1

/* macros for radio65_reg_map.ch0_CPU_PLL4 */
#define INST_RADIO65_REG_MAP__CH0_CPU_PLL4__NUM                               1

/* macros for radio65_reg_map.ch0_AUDIO_PLL */
#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL__NUM                              1

/* macros for radio65_reg_map.ch0_AUDIO_PLL2 */
#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL2__NUM                             1

/* macros for radio65_reg_map.ch0_AUDIO_PLL3 */
#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL3__NUM                             1

/* macros for radio65_reg_map.ch0_AUDIO_PLL4 */
#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL4__NUM                             1

/* macros for radio65_reg_map.ch0_DDR_PLL */
#define INST_RADIO65_REG_MAP__CH0_DDR_PLL__NUM                                1

/* macros for radio65_reg_map.ch0_DDR_PLL2 */
#define INST_RADIO65_REG_MAP__CH0_DDR_PLL2__NUM                               1

/* macros for radio65_reg_map.ch0_DDR_PLL3 */
#define INST_RADIO65_REG_MAP__CH0_DDR_PLL3__NUM                               1

/* macros for radio65_reg_map.ch0_DDR_PLL4 */
#define INST_RADIO65_REG_MAP__CH0_DDR_PLL4__NUM                               1

/* macros for BlueprintGlobalNameSpace::TOP */
#ifndef __TOP_MACRO__
#define __TOP_MACRO__

/* macros for field sel_tempsensor */
#define TOP__SEL_TEMPSENSOR__SHIFT                                            0
#define TOP__SEL_TEMPSENSOR__WIDTH                                            1
#define TOP__SEL_TEMPSENSOR__MASK                                   0x00000001U
#define TOP__SEL_TEMPSENSOR__READ(src)           (u_int32_t)(src) & 0x00000001U
#define TOP__SEL_TEMPSENSOR__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
#define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TOP__SEL_TEMPSENSOR__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
#define TOP__SEL_TEMPSENSOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TOP__SEL_TEMPSENSOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field spare */
#define TOP__SPARE__SHIFT                                                     1
#define TOP__SPARE__WIDTH                                                     1
#define TOP__SPARE__MASK                                            0x00000002U
#define TOP__SPARE__READ(src)           (((u_int32_t)(src) & 0x00000002U) >> 1)
#define TOP__SPARE__WRITE(src)          (((u_int32_t)(src) << 1) & 0x00000002U)
#define TOP__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define TOP__SPARE__VERIFY(src)   (!((((u_int32_t)(src) << 1) & ~0x00000002U)))
#define TOP__SPARE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TOP__SPARE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field clk107_en */
#define TOP__CLK107_EN__SHIFT                                                 2
#define TOP__CLK107_EN__WIDTH                                                 1
#define TOP__CLK107_EN__MASK                                        0x00000004U
#define TOP__CLK107_EN__READ(src)       (((u_int32_t)(src) & 0x00000004U) >> 2)
#define TOP__CLK107_EN__WRITE(src)      (((u_int32_t)(src) << 2) & 0x00000004U)
#define TOP__CLK107_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define TOP__CLK107_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define TOP__CLK107_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TOP__CLK107_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field pwdv2i */
#define TOP__PWDV2I__SHIFT                                                    3
#define TOP__PWDV2I__WIDTH                                                    1
#define TOP__PWDV2I__MASK                                           0x00000008U
#define TOP__PWDV2I__READ(src)          (((u_int32_t)(src) & 0x00000008U) >> 3)
#define TOP__PWDV2I__WRITE(src)         (((u_int32_t)(src) << 3) & 0x00000008U)
#define TOP__PWDV2I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define TOP__PWDV2I__VERIFY(src)  (!((((u_int32_t)(src) << 3) & ~0x00000008U)))
#define TOP__PWDV2I__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TOP__PWDV2I__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field pwdbias */
#define TOP__PWDBIAS__SHIFT                                                   4
#define TOP__PWDBIAS__WIDTH                                                   1
#define TOP__PWDBIAS__MASK                                          0x00000010U
#define TOP__PWDBIAS__READ(src)         (((u_int32_t)(src) & 0x00000010U) >> 4)
#define TOP__PWDBIAS__WRITE(src)        (((u_int32_t)(src) << 4) & 0x00000010U)
#define TOP__PWDBIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define TOP__PWDBIAS__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000010U)))
#define TOP__PWDBIAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define TOP__PWDBIAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field xpabias_bypass */
#define TOP__XPABIAS_BYPASS__SHIFT                                            5
#define TOP__XPABIAS_BYPASS__WIDTH                                            1
#define TOP__XPABIAS_BYPASS__MASK                                   0x00000020U
#define TOP__XPABIAS_BYPASS__READ(src)  (((u_int32_t)(src) & 0x00000020U) >> 5)
#define TOP__XPABIAS_BYPASS__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
#define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define TOP__XPABIAS_BYPASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define TOP__XPABIAS_BYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define TOP__XPABIAS_BYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field xpabiaslvl */
#define TOP__XPABIASLVL__SHIFT                                                6
#define TOP__XPABIASLVL__WIDTH                                                4
#define TOP__XPABIASLVL__MASK                                       0x000003c0U
#define TOP__XPABIASLVL__READ(src)      (((u_int32_t)(src) & 0x000003c0U) >> 6)
#define TOP__XPABIASLVL__WRITE(src)     (((u_int32_t)(src) << 6) & 0x000003c0U)
#define TOP__XPABIASLVL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000003c0U)
#define TOP__XPABIASLVL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000003c0U)))

/* macros for field xparegulator_en */
#define TOP__XPAREGULATOR_EN__SHIFT                                          10
#define TOP__XPAREGULATOR_EN__WIDTH                                           1
#define TOP__XPAREGULATOR_EN__MASK                                  0x00000400U
#define TOP__XPAREGULATOR_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define TOP__XPAREGULATOR_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define TOP__XPAREGULATOR_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define TOP__XPAREGULATOR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define TOP__XPAREGULATOR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field xpashort2gnd */
#define TOP__XPASHORT2GND__SHIFT                                             11
#define TOP__XPASHORT2GND__WIDTH                                              1
#define TOP__XPASHORT2GND__MASK                                     0x00000800U
#define TOP__XPASHORT2GND__READ(src)   (((u_int32_t)(src) & 0x00000800U) >> 11)
#define TOP__XPASHORT2GND__WRITE(src)  (((u_int32_t)(src) << 11) & 0x00000800U)
#define TOP__XPASHORT2GND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define TOP__XPASHORT2GND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define TOP__XPASHORT2GND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define TOP__XPASHORT2GND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field xpa5on */
#define TOP__XPA5ON__SHIFT                                                   12
#define TOP__XPA5ON__WIDTH                                                    3
#define TOP__XPA5ON__MASK                                           0x00007000U
#define TOP__XPA5ON__READ(src)         (((u_int32_t)(src) & 0x00007000U) >> 12)
#define TOP__XPA5ON__WRITE(src)        (((u_int32_t)(src) << 12) & 0x00007000U)
#define TOP__XPA5ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define TOP__XPA5ON__VERIFY(src) (!((((u_int32_t)(src) << 12) & ~0x00007000U)))

/* macros for field xpa2on */
#define TOP__XPA2ON__SHIFT                                                   15
#define TOP__XPA2ON__WIDTH                                                    3
#define TOP__XPA2ON__MASK                                           0x00038000U
#define TOP__XPA2ON__READ(src)         (((u_int32_t)(src) & 0x00038000U) >> 15)
#define TOP__XPA2ON__WRITE(src)        (((u_int32_t)(src) << 15) & 0x00038000U)
#define TOP__XPA2ON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define TOP__XPA2ON__VERIFY(src) (!((((u_int32_t)(src) << 15) & ~0x00038000U)))

/* macros for field local_xpaon */
#define TOP__LOCAL_XPAON__SHIFT                                              18
#define TOP__LOCAL_XPAON__WIDTH                                               1
#define TOP__LOCAL_XPAON__MASK                                      0x00040000U
#define TOP__LOCAL_XPAON__READ(src)    (((u_int32_t)(src) & 0x00040000U) >> 18)
#define TOP__LOCAL_XPAON__WRITE(src)   (((u_int32_t)(src) << 18) & 0x00040000U)
#define TOP__LOCAL_XPAON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((u_int32_t)(src) <<\
                    18) & 0x00040000U)
#define TOP__LOCAL_XPAON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x00040000U)))
#define TOP__LOCAL_XPAON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(1) << 18)
#define TOP__LOCAL_XPAON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((u_int32_t)(0) << 18)

/* macros for field pad2gnd */
#define TOP__PAD2GND__SHIFT                                                  19
#define TOP__PAD2GND__WIDTH                                                   1
#define TOP__PAD2GND__MASK                                          0x00080000U
#define TOP__PAD2GND__READ(src)        (((u_int32_t)(src) & 0x00080000U) >> 19)
#define TOP__PAD2GND__WRITE(src)       (((u_int32_t)(src) << 19) & 0x00080000U)
#define TOP__PAD2GND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((u_int32_t)(src) <<\
                    19) & 0x00080000U)
#define TOP__PAD2GND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 19) & ~0x00080000U)))
#define TOP__PAD2GND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(1) << 19)
#define TOP__PAD2GND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((u_int32_t)(0) << 19)

/* macros for field intH2pad */
#define TOP__INTH2PAD__SHIFT                                                 20
#define TOP__INTH2PAD__WIDTH                                                  1
#define TOP__INTH2PAD__MASK                                         0x00100000U
#define TOP__INTH2PAD__READ(src)       (((u_int32_t)(src) & 0x00100000U) >> 20)
#define TOP__INTH2PAD__WRITE(src)      (((u_int32_t)(src) << 20) & 0x00100000U)
#define TOP__INTH2PAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((u_int32_t)(src) <<\
                    20) & 0x00100000U)
#define TOP__INTH2PAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 20) & ~0x00100000U)))
#define TOP__INTH2PAD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(1) << 20)
#define TOP__INTH2PAD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((u_int32_t)(0) << 20)

/* macros for field intH2gnd */
#define TOP__INTH2GND__SHIFT                                                 21
#define TOP__INTH2GND__WIDTH                                                  1
#define TOP__INTH2GND__MASK                                         0x00200000U
#define TOP__INTH2GND__READ(src)       (((u_int32_t)(src) & 0x00200000U) >> 21)
#define TOP__INTH2GND__WRITE(src)      (((u_int32_t)(src) << 21) & 0x00200000U)
#define TOP__INTH2GND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((u_int32_t)(src) <<\
                    21) & 0x00200000U)
#define TOP__INTH2GND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00200000U)))
#define TOP__INTH2GND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(1) << 21)
#define TOP__INTH2GND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((u_int32_t)(0) << 21)

/* macros for field int2pad */
#define TOP__INT2PAD__SHIFT                                                  22
#define TOP__INT2PAD__WIDTH                                                   1
#define TOP__INT2PAD__MASK                                          0x00400000U
#define TOP__INT2PAD__READ(src)        (((u_int32_t)(src) & 0x00400000U) >> 22)
#define TOP__INT2PAD__WRITE(src)       (((u_int32_t)(src) << 22) & 0x00400000U)
#define TOP__INT2PAD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((u_int32_t)(src) <<\
                    22) & 0x00400000U)
#define TOP__INT2PAD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 22) & ~0x00400000U)))
#define TOP__INT2PAD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(1) << 22)
#define TOP__INT2PAD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((u_int32_t)(0) << 22)

/* macros for field int2gnd */
#define TOP__INT2GND__SHIFT                                                  23
#define TOP__INT2GND__WIDTH                                                   1
#define TOP__INT2GND__MASK                                          0x00800000U
#define TOP__INT2GND__READ(src)        (((u_int32_t)(src) & 0x00800000U) >> 23)
#define TOP__INT2GND__WRITE(src)       (((u_int32_t)(src) << 23) & 0x00800000U)
#define TOP__INT2GND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((u_int32_t)(src) <<\
                    23) & 0x00800000U)
#define TOP__INT2GND__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 23) & ~0x00800000U)))
#define TOP__INT2GND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(1) << 23)
#define TOP__INT2GND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((u_int32_t)(0) << 23)

/* macros for field enBTclk */
#define TOP__ENBTCLK__SHIFT                                                  24
#define TOP__ENBTCLK__WIDTH                                                   1
#define TOP__ENBTCLK__MASK                                          0x01000000U
#define TOP__ENBTCLK__READ(src)        (((u_int32_t)(src) & 0x01000000U) >> 24)
#define TOP__ENBTCLK__WRITE(src)       (((u_int32_t)(src) << 24) & 0x01000000U)
#define TOP__ENBTCLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TOP__ENBTCLK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TOP__ENBTCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TOP__ENBTCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field pwdPALclk */
#define TOP__PWDPALCLK__SHIFT                                                25
#define TOP__PWDPALCLK__WIDTH                                                 1
#define TOP__PWDPALCLK__MASK                                        0x02000000U
#define TOP__PWDPALCLK__READ(src)      (((u_int32_t)(src) & 0x02000000U) >> 25)
#define TOP__PWDPALCLK__WRITE(src)     (((u_int32_t)(src) << 25) & 0x02000000U)
#define TOP__PWDPALCLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define TOP__PWDPALCLK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define TOP__PWDPALCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define TOP__PWDPALCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field inv_clk320_adc */
#define TOP__INV_CLK320_ADC__SHIFT                                           26
#define TOP__INV_CLK320_ADC__WIDTH                                            1
#define TOP__INV_CLK320_ADC__MASK                                   0x04000000U
#define TOP__INV_CLK320_ADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
#define TOP__INV_CLK320_ADC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 26) & 0x04000000U)
#define TOP__INV_CLK320_ADC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((u_int32_t)(src) <<\
                    26) & 0x04000000U)
#define TOP__INV_CLK320_ADC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x04000000U)))
#define TOP__INV_CLK320_ADC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(1) << 26)
#define TOP__INV_CLK320_ADC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((u_int32_t)(0) << 26)

/* macros for field flip_refclk40 */
#define TOP__FLIP_REFCLK40__SHIFT                                            27
#define TOP__FLIP_REFCLK40__WIDTH                                             1
#define TOP__FLIP_REFCLK40__MASK                                    0x08000000U
#define TOP__FLIP_REFCLK40__READ(src)  (((u_int32_t)(src) & 0x08000000U) >> 27)
#define TOP__FLIP_REFCLK40__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U)
#define TOP__FLIP_REFCLK40__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((u_int32_t)(src) <<\
                    27) & 0x08000000U)
#define TOP__FLIP_REFCLK40__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 27) & ~0x08000000U)))
#define TOP__FLIP_REFCLK40__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(1) << 27)
#define TOP__FLIP_REFCLK40__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((u_int32_t)(0) << 27)

/* macros for field flip_pllclk320 */
#define TOP__FLIP_PLLCLK320__SHIFT                                           28
#define TOP__FLIP_PLLCLK320__WIDTH                                            1
#define TOP__FLIP_PLLCLK320__MASK                                   0x10000000U
#define TOP__FLIP_PLLCLK320__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
#define TOP__FLIP_PLLCLK320__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 28) & 0x10000000U)
#define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TOP__FLIP_PLLCLK320__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TOP__FLIP_PLLCLK320__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TOP__FLIP_PLLCLK320__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field flip_pllclk160 */
#define TOP__FLIP_PLLCLK160__SHIFT                                           29
#define TOP__FLIP_PLLCLK160__WIDTH                                            1
#define TOP__FLIP_PLLCLK160__MASK                                   0x20000000U
#define TOP__FLIP_PLLCLK160__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
#define TOP__FLIP_PLLCLK160__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define TOP__FLIP_PLLCLK160__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define TOP__FLIP_PLLCLK160__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define TOP__FLIP_PLLCLK160__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field clk_sel */
#define TOP__CLK_SEL__SHIFT                                                  30
#define TOP__CLK_SEL__WIDTH                                                   2
#define TOP__CLK_SEL__MASK                                          0xc0000000U
#define TOP__CLK_SEL__READ(src)        (((u_int32_t)(src) & 0xc0000000U) >> 30)
#define TOP__CLK_SEL__WRITE(src)       (((u_int32_t)(src) << 30) & 0xc0000000U)
#define TOP__CLK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((u_int32_t)(src) <<\
                    30) & 0xc0000000U)
#define TOP__CLK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define TOP__TYPE                                                     u_int32_t
#define TOP__READ                                                   0xffffffffU
#define TOP__WRITE                                                  0xffffffffU

#endif /* __TOP_MACRO__ */


/* macros for radio65_reg_map.ch0_TOP */
#define INST_RADIO65_REG_MAP__CH0_TOP__NUM                                    1

/* macros for BlueprintGlobalNameSpace::TOP2 */
#ifndef __TOP2_MACRO__
#define __TOP2_MACRO__

/* macros for field rst_warm_int_l */
#define TOP2__RST_WARM_INT_L__SHIFT                                           0
#define TOP2__RST_WARM_INT_L__WIDTH                                           1
#define TOP2__RST_WARM_INT_L__MASK                                  0x00000001U
#define TOP2__RST_WARM_INT_L__READ(src)          (u_int32_t)(src) & 0x00000001U
#define TOP2__RST_WARM_INT_L__WRITE(src)       ((u_int32_t)(src) & 0x00000001U)
#define TOP2__RST_WARM_INT_L__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define TOP2__RST_WARM_INT_L__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define TOP2__RST_WARM_INT_L__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define TOP2__RST_WARM_INT_L__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field rst_warm_ovr */
#define TOP2__RST_WARM_OVR__SHIFT                                             1
#define TOP2__RST_WARM_OVR__WIDTH                                             1
#define TOP2__RST_WARM_OVR__MASK                                    0x00000002U
#define TOP2__RST_WARM_OVR__READ(src)   (((u_int32_t)(src) & 0x00000002U) >> 1)
#define TOP2__RST_WARM_OVR__WRITE(src)  (((u_int32_t)(src) << 1) & 0x00000002U)
#define TOP2__RST_WARM_OVR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define TOP2__RST_WARM_OVR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define TOP2__RST_WARM_OVR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define TOP2__RST_WARM_OVR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field global_clk_en */
#define TOP2__GLOBAL_CLK_EN__SHIFT                                            2
#define TOP2__GLOBAL_CLK_EN__WIDTH                                            1
#define TOP2__GLOBAL_CLK_EN__MASK                                   0x00000004U
#define TOP2__GLOBAL_CLK_EN__READ(src)  (((u_int32_t)(src) & 0x00000004U) >> 2)
#define TOP2__GLOBAL_CLK_EN__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
#define TOP2__GLOBAL_CLK_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define TOP2__GLOBAL_CLK_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define TOP2__GLOBAL_CLK_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define TOP2__GLOBAL_CLK_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field local_clkmoda */
#define TOP2__LOCAL_CLKMODA__SHIFT                                            3
#define TOP2__LOCAL_CLKMODA__WIDTH                                            1
#define TOP2__LOCAL_CLKMODA__MASK                                   0x00000008U
#define TOP2__LOCAL_CLKMODA__READ(src)  (((u_int32_t)(src) & 0x00000008U) >> 3)
#define TOP2__LOCAL_CLKMODA__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
#define TOP2__LOCAL_CLKMODA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define TOP2__LOCAL_CLKMODA__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define TOP2__LOCAL_CLKMODA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define TOP2__LOCAL_CLKMODA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field pllbypass */
#define TOP2__PLLBYPASS__SHIFT                                                4
#define TOP2__PLLBYPASS__WIDTH                                                1
#define TOP2__PLLBYPASS__MASK                                       0x00000010U
#define TOP2__PLLBYPASS__READ(src)      (((u_int32_t)(src) & 0x00000010U) >> 4)
#define TOP2__PLLBYPASS__WRITE(src)     (((u_int32_t)(src) << 4) & 0x00000010U)
#define TOP2__PLLBYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define TOP2__PLLBYPASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define TOP2__PLLBYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define TOP2__PLLBYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field local_pllbypass */
#define TOP2__LOCAL_PLLBYPASS__SHIFT                                          5
#define TOP2__LOCAL_PLLBYPASS__WIDTH                                          1
#define TOP2__LOCAL_PLLBYPASS__MASK                                 0x00000020U
#define TOP2__LOCAL_PLLBYPASS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define TOP2__LOCAL_PLLBYPASS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define TOP2__LOCAL_PLLBYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define TOP2__LOCAL_PLLBYPASS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define TOP2__LOCAL_PLLBYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define TOP2__LOCAL_PLLBYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field testtxiq_enbypass_b */
#define TOP2__TESTTXIQ_ENBYPASS_B__SHIFT                                      6
#define TOP2__TESTTXIQ_ENBYPASS_B__WIDTH                                      3
#define TOP2__TESTTXIQ_ENBYPASS_B__MASK                             0x000001c0U
#define TOP2__TESTTXIQ_ENBYPASS_B__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000001c0U) >> 6)
#define TOP2__TESTTXIQ_ENBYPASS_B__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x000001c0U)
#define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000001c0U) | (((u_int32_t)(src) <<\
                    6) & 0x000001c0U)
#define TOP2__TESTTXIQ_ENBYPASS_B__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x000001c0U)))

/* macros for field testtxiq_rctrl */
#define TOP2__TESTTXIQ_RCTRL__SHIFT                                           9
#define TOP2__TESTTXIQ_RCTRL__WIDTH                                           3
#define TOP2__TESTTXIQ_RCTRL__MASK                                  0x00000e00U
#define TOP2__TESTTXIQ_RCTRL__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9)
#define TOP2__TESTTXIQ_RCTRL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000e00U)
#define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((u_int32_t)(src) <<\
                    9) & 0x00000e00U)
#define TOP2__TESTTXIQ_RCTRL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field testtxiq_enloopback */
#define TOP2__TESTTXIQ_ENLOOPBACK__SHIFT                                     12
#define TOP2__TESTTXIQ_ENLOOPBACK__WIDTH                                      3
#define TOP2__TESTTXIQ_ENLOOPBACK__MASK                             0x00007000U
#define TOP2__TESTTXIQ_ENLOOPBACK__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00007000U) >> 12)
#define TOP2__TESTTXIQ_ENLOOPBACK__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00007000U)
#define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((u_int32_t)(src) <<\
                    12) & 0x00007000U)
#define TOP2__TESTTXIQ_ENLOOPBACK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field testtxiq_pwd */
#define TOP2__TESTTXIQ_PWD__SHIFT                                            15
#define TOP2__TESTTXIQ_PWD__WIDTH                                             3
#define TOP2__TESTTXIQ_PWD__MASK                                    0x00038000U
#define TOP2__TESTTXIQ_PWD__READ(src)  (((u_int32_t)(src) & 0x00038000U) >> 15)
#define TOP2__TESTTXIQ_PWD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
#define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00038000U) | (((u_int32_t)(src) <<\
                    15) & 0x00038000U)
#define TOP2__TESTTXIQ_PWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00038000U)))

/* macros for field dacpwd */
#define TOP2__DACPWD__SHIFT                                                  18
#define TOP2__DACPWD__WIDTH                                                   3
#define TOP2__DACPWD__MASK                                          0x001c0000U
#define TOP2__DACPWD__READ(src)        (((u_int32_t)(src) & 0x001c0000U) >> 18)
#define TOP2__DACPWD__WRITE(src)       (((u_int32_t)(src) << 18) & 0x001c0000U)
#define TOP2__DACPWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001c0000U) | (((u_int32_t)(src) <<\
                    18) & 0x001c0000U)
#define TOP2__DACPWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 18) & ~0x001c0000U)))

/* macros for field adcpwd */
#define TOP2__ADCPWD__SHIFT                                                  21
#define TOP2__ADCPWD__WIDTH                                                   3
#define TOP2__ADCPWD__MASK                                          0x00e00000U
#define TOP2__ADCPWD__READ(src)        (((u_int32_t)(src) & 0x00e00000U) >> 21)
#define TOP2__ADCPWD__WRITE(src)       (((u_int32_t)(src) << 21) & 0x00e00000U)
#define TOP2__ADCPWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00e00000U) | (((u_int32_t)(src) <<\
                    21) & 0x00e00000U)
#define TOP2__ADCPWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 21) & ~0x00e00000U)))

/* macros for field local_addacpwd */
#define TOP2__LOCAL_ADDACPWD__SHIFT                                          24
#define TOP2__LOCAL_ADDACPWD__WIDTH                                           1
#define TOP2__LOCAL_ADDACPWD__MASK                                  0x01000000U
#define TOP2__LOCAL_ADDACPWD__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define TOP2__LOCAL_ADDACPWD__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define TOP2__LOCAL_ADDACPWD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define TOP2__LOCAL_ADDACPWD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define TOP2__LOCAL_ADDACPWD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field adc_clk_sel */
#define TOP2__ADC_CLK_SEL__SHIFT                                             25
#define TOP2__ADC_CLK_SEL__WIDTH                                              4
#define TOP2__ADC_CLK_SEL__MASK                                     0x1e000000U
#define TOP2__ADC_CLK_SEL__READ(src)   (((u_int32_t)(src) & 0x1e000000U) >> 25)
#define TOP2__ADC_CLK_SEL__WRITE(src)  (((u_int32_t)(src) << 25) & 0x1e000000U)
#define TOP2__ADC_CLK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1e000000U) | (((u_int32_t)(src) <<\
                    25) & 0x1e000000U)
#define TOP2__ADC_CLK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x1e000000U)))

/* macros for field dac_clk_sel */
#define TOP2__DAC_CLK_SEL__SHIFT                                             29
#define TOP2__DAC_CLK_SEL__WIDTH                                              3
#define TOP2__DAC_CLK_SEL__MASK                                     0xe0000000U
#define TOP2__DAC_CLK_SEL__READ(src)   (((u_int32_t)(src) & 0xe0000000U) >> 29)
#define TOP2__DAC_CLK_SEL__WRITE(src)  (((u_int32_t)(src) << 29) & 0xe0000000U)
#define TOP2__DAC_CLK_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xe0000000U) | (((u_int32_t)(src) <<\
                    29) & 0xe0000000U)
#define TOP2__DAC_CLK_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0xe0000000U)))
#define TOP2__TYPE                                                    u_int32_t
#define TOP2__READ                                                  0xffffffffU
#define TOP2__WRITE                                                 0xffffffffU

#endif /* __TOP2_MACRO__ */


/* macros for radio65_reg_map.ch0_TOP2 */
#define INST_RADIO65_REG_MAP__CH0_TOP2__NUM                                   1

/* macros for BlueprintGlobalNameSpace::TOP3 */
#ifndef __TOP3_MACRO__
#define __TOP3_MACRO__

/* macros for field spare */
#define TOP3__SPARE__SHIFT                                                    0
#define TOP3__SPARE__WIDTH                                                   16
#define TOP3__SPARE__MASK                                           0x0000ffffU
#define TOP3__SPARE__READ(src)                   (u_int32_t)(src) & 0x0000ffffU
#define TOP3__SPARE__WRITE(src)                ((u_int32_t)(src) & 0x0000ffffU)
#define TOP3__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((u_int32_t)(src) &\
                    0x0000ffffU)
#define TOP3__SPARE__VERIFY(src)         (!(((u_int32_t)(src) & ~0x0000ffffU)))

/* macros for field rbias_out */
#define TOP3__RBIAS_OUT__SHIFT                                               16
#define TOP3__RBIAS_OUT__WIDTH                                                6
#define TOP3__RBIAS_OUT__MASK                                       0x003f0000U
#define TOP3__RBIAS_OUT__READ(src)     (((u_int32_t)(src) & 0x003f0000U) >> 16)

/* macros for field rbias */
#define TOP3__RBIAS__SHIFT                                                   22
#define TOP3__RBIAS__WIDTH                                                    6
#define TOP3__RBIAS__MASK                                           0x0fc00000U
#define TOP3__RBIAS__READ(src)         (((u_int32_t)(src) & 0x0fc00000U) >> 22)
#define TOP3__RBIAS__WRITE(src)        (((u_int32_t)(src) << 22) & 0x0fc00000U)
#define TOP3__RBIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
                    22) & 0x0fc00000U)
#define TOP3__RBIAS__VERIFY(src) (!((((u_int32_t)(src) << 22) & ~0x0fc00000U)))

/* macros for field localrbias */
#define TOP3__LOCALRBIAS__SHIFT                                              28
#define TOP3__LOCALRBIAS__WIDTH                                               1
#define TOP3__LOCALRBIAS__MASK                                      0x10000000U
#define TOP3__LOCALRBIAS__READ(src)    (((u_int32_t)(src) & 0x10000000U) >> 28)
#define TOP3__LOCALRBIAS__WRITE(src)   (((u_int32_t)(src) << 28) & 0x10000000U)
#define TOP3__LOCALRBIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define TOP3__LOCALRBIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define TOP3__LOCALRBIAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define TOP3__LOCALRBIAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field bbpll_atbvreg */
#define TOP3__BBPLL_ATBVREG__SHIFT                                           29
#define TOP3__BBPLL_ATBVREG__WIDTH                                            1
#define TOP3__BBPLL_ATBVREG__MASK                                   0x20000000U
#define TOP3__BBPLL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
#define TOP3__BBPLL_ATBVREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 29) & 0x20000000U)
#define TOP3__BBPLL_ATBVREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define TOP3__BBPLL_ATBVREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define TOP3__BBPLL_ATBVREG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define TOP3__BBPLL_ATBVREG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field bbpll_selvreg */
#define TOP3__BBPLL_SELVREG__SHIFT                                           30
#define TOP3__BBPLL_SELVREG__WIDTH                                            1
#define TOP3__BBPLL_SELVREG__MASK                                   0x40000000U
#define TOP3__BBPLL_SELVREG__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
#define TOP3__BBPLL_SELVREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define TOP3__BBPLL_SELVREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define TOP3__BBPLL_SELVREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define TOP3__BBPLL_SELVREG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define TOP3__BBPLL_SELVREG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field bbpll_pwdvreg */
#define TOP3__BBPLL_PWDVREG__SHIFT                                           31
#define TOP3__BBPLL_PWDVREG__WIDTH                                            1
#define TOP3__BBPLL_PWDVREG__MASK                                   0x80000000U
#define TOP3__BBPLL_PWDVREG__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
#define TOP3__BBPLL_PWDVREG__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 31) & 0x80000000U)
#define TOP3__BBPLL_PWDVREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define TOP3__BBPLL_PWDVREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define TOP3__BBPLL_PWDVREG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define TOP3__BBPLL_PWDVREG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define TOP3__TYPE                                                    u_int32_t
#define TOP3__READ                                                  0xffffffffU
#define TOP3__WRITE                                                 0xffffffffU

#endif /* __TOP3_MACRO__ */


/* macros for radio65_reg_map.ch0_TOP3 */
#define INST_RADIO65_REG_MAP__CH0_TOP3__NUM                                   1

/* macros for BlueprintGlobalNameSpace::THERM */
#ifndef __THERM_MACRO__
#define __THERM_MACRO__

/* macros for field spare */
#define THERM__SPARE__SHIFT                                                   0
#define THERM__SPARE__WIDTH                                                   6
#define THERM__SPARE__MASK                                          0x0000003fU
#define THERM__SPARE__READ(src)                  (u_int32_t)(src) & 0x0000003fU
#define THERM__SPARE__WRITE(src)               ((u_int32_t)(src) & 0x0000003fU)
#define THERM__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((u_int32_t)(src) &\
                    0x0000003fU)
#define THERM__SPARE__VERIFY(src)        (!(((u_int32_t)(src) & ~0x0000003fU)))

/* macros for field rst_warm_l_therm */
#define THERM__RST_WARM_L_THERM__SHIFT                                        6
#define THERM__RST_WARM_L_THERM__WIDTH                                        1
#define THERM__RST_WARM_L_THERM__MASK                               0x00000040U
#define THERM__RST_WARM_L_THERM__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define THERM__RST_WARM_L_THERM__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define THERM__RST_WARM_L_THERM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define THERM__RST_WARM_L_THERM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define THERM__RST_WARM_L_THERM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define THERM__RST_WARM_L_THERM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field sar_adc_done */
#define THERM__SAR_ADC_DONE__SHIFT                                            7
#define THERM__SAR_ADC_DONE__WIDTH                                            1
#define THERM__SAR_ADC_DONE__MASK                                   0x00000080U
#define THERM__SAR_ADC_DONE__READ(src)  (((u_int32_t)(src) & 0x00000080U) >> 7)
#define THERM__SAR_ADC_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define THERM__SAR_ADC_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field sar_adc_out */
#define THERM__SAR_ADC_OUT__SHIFT                                             8
#define THERM__SAR_ADC_OUT__WIDTH                                             8
#define THERM__SAR_ADC_OUT__MASK                                    0x0000ff00U
#define THERM__SAR_ADC_OUT__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)

/* macros for field sar_dactest_code */
#define THERM__SAR_DACTEST_CODE__SHIFT                                       16
#define THERM__SAR_DACTEST_CODE__WIDTH                                        8
#define THERM__SAR_DACTEST_CODE__MASK                               0x00ff0000U
#define THERM__SAR_DACTEST_CODE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define THERM__SAR_DACTEST_CODE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define THERM__SAR_DACTEST_CODE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field sar_dactest_en */
#define THERM__SAR_DACTEST_EN__SHIFT                                         24
#define THERM__SAR_DACTEST_EN__WIDTH                                          1
#define THERM__SAR_DACTEST_EN__MASK                                 0x01000000U
#define THERM__SAR_DACTEST_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x01000000U) >> 24)
#define THERM__SAR_DACTEST_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x01000000U)
#define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((u_int32_t)(src) <<\
                    24) & 0x01000000U)
#define THERM__SAR_DACTEST_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x01000000U)))
#define THERM__SAR_DACTEST_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(1) << 24)
#define THERM__SAR_DACTEST_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((u_int32_t)(0) << 24)

/* macros for field sar_adccal_en */
#define THERM__SAR_ADCCAL_EN__SHIFT                                          25
#define THERM__SAR_ADCCAL_EN__WIDTH                                           1
#define THERM__SAR_ADCCAL_EN__MASK                                  0x02000000U
#define THERM__SAR_ADCCAL_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x02000000U) >> 25)
#define THERM__SAR_ADCCAL_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 25) & 0x02000000U)
#define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((u_int32_t)(src) <<\
                    25) & 0x02000000U)
#define THERM__SAR_ADCCAL_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 25) & ~0x02000000U)))
#define THERM__SAR_ADCCAL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(1) << 25)
#define THERM__SAR_ADCCAL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((u_int32_t)(0) << 25)

/* macros for field thermsel */
#define THERM__THERMSEL__SHIFT                                               26
#define THERM__THERMSEL__WIDTH                                                2
#define THERM__THERMSEL__MASK                                       0x0c000000U
#define THERM__THERMSEL__READ(src)     (((u_int32_t)(src) & 0x0c000000U) >> 26)
#define THERM__THERMSEL__WRITE(src)    (((u_int32_t)(src) << 26) & 0x0c000000U)
#define THERM__THERMSEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((u_int32_t)(src) <<\
                    26) & 0x0c000000U)
#define THERM__THERMSEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 26) & ~0x0c000000U)))

/* macros for field sar_slow_en */
#define THERM__SAR_SLOW_EN__SHIFT                                            28
#define THERM__SAR_SLOW_EN__WIDTH                                             1
#define THERM__SAR_SLOW_EN__MASK                                    0x10000000U
#define THERM__SAR_SLOW_EN__READ(src)  (((u_int32_t)(src) & 0x10000000U) >> 28)
#define THERM__SAR_SLOW_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
#define THERM__SAR_SLOW_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((u_int32_t)(src) <<\
                    28) & 0x10000000U)
#define THERM__SAR_SLOW_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 28) & ~0x10000000U)))
#define THERM__SAR_SLOW_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(1) << 28)
#define THERM__SAR_SLOW_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((u_int32_t)(0) << 28)

/* macros for field thermstart */
#define THERM__THERMSTART__SHIFT                                             29
#define THERM__THERMSTART__WIDTH                                              1
#define THERM__THERMSTART__MASK                                     0x20000000U
#define THERM__THERMSTART__READ(src)   (((u_int32_t)(src) & 0x20000000U) >> 29)
#define THERM__THERMSTART__WRITE(src)  (((u_int32_t)(src) << 29) & 0x20000000U)
#define THERM__THERMSTART__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((u_int32_t)(src) <<\
                    29) & 0x20000000U)
#define THERM__THERMSTART__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 29) & ~0x20000000U)))
#define THERM__THERMSTART__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(1) << 29)
#define THERM__THERMSTART__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((u_int32_t)(0) << 29)

/* macros for field sar_autopwd_en */
#define THERM__SAR_AUTOPWD_EN__SHIFT                                         30
#define THERM__SAR_AUTOPWD_EN__WIDTH                                          1
#define THERM__SAR_AUTOPWD_EN__MASK                                 0x40000000U
#define THERM__SAR_AUTOPWD_EN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x40000000U) >> 30)
#define THERM__SAR_AUTOPWD_EN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 30) & 0x40000000U)
#define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((u_int32_t)(src) <<\
                    30) & 0x40000000U)
#define THERM__SAR_AUTOPWD_EN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 30) & ~0x40000000U)))
#define THERM__SAR_AUTOPWD_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(1) << 30)
#define THERM__SAR_AUTOPWD_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((u_int32_t)(0) << 30)

/* macros for field local_therm */
#define THERM__LOCAL_THERM__SHIFT                                            31
#define THERM__LOCAL_THERM__WIDTH                                             1
#define THERM__LOCAL_THERM__MASK                                    0x80000000U
#define THERM__LOCAL_THERM__READ(src)  (((u_int32_t)(src) & 0x80000000U) >> 31)
#define THERM__LOCAL_THERM__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
#define THERM__LOCAL_THERM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((u_int32_t)(src) <<\
                    31) & 0x80000000U)
#define THERM__LOCAL_THERM__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 31) & ~0x80000000U)))
#define THERM__LOCAL_THERM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define THERM__LOCAL_THERM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define THERM__TYPE                                                   u_int32_t
#define THERM__READ                                                 0xffffffffU
#define THERM__WRITE                                                0xffffffffU

#endif /* __THERM_MACRO__ */


/* macros for radio65_reg_map.ch0_THERM */
#define INST_RADIO65_REG_MAP__CH0_THERM__NUM                                  1

/* macros for BlueprintGlobalNameSpace::XTAL */
#ifndef __XTAL_MACRO__
#define __XTAL_MACRO__

/* macros for field SPARE */
#define XTAL__SPARE__SHIFT                                                    0
#define XTAL__SPARE__WIDTH                                                    4
#define XTAL__SPARE__MASK                                           0x0000000fU
#define XTAL__SPARE__READ(src)                   (u_int32_t)(src) & 0x0000000fU
#define XTAL__SPARE__WRITE(src)                ((u_int32_t)(src) & 0x0000000fU)
#define XTAL__SPARE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define XTAL__SPARE__VERIFY(src)         (!(((u_int32_t)(src) & ~0x0000000fU)))

/* macros for field swregclk_edge_sel */
#define XTAL__SWREGCLK_EDGE_SEL__SHIFT                                        4
#define XTAL__SWREGCLK_EDGE_SEL__WIDTH                                        1
#define XTAL__SWREGCLK_EDGE_SEL__MASK                               0x00000010U
#define XTAL__SWREGCLK_EDGE_SEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define XTAL__SWREGCLK_EDGE_SEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define XTAL__SWREGCLK_EDGE_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define XTAL__SWREGCLK_EDGE_SEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define XTAL__SWREGCLK_EDGE_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define XTAL__SWREGCLK_EDGE_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field pwd_swregclk */
#define XTAL__PWD_SWREGCLK__SHIFT                                             5
#define XTAL__PWD_SWREGCLK__WIDTH                                             1
#define XTAL__PWD_SWREGCLK__MASK                                    0x00000020U
#define XTAL__PWD_SWREGCLK__READ(src)   (((u_int32_t)(src) & 0x00000020U) >> 5)
#define XTAL__PWD_SWREGCLK__WRITE(src)  (((u_int32_t)(src) << 5) & 0x00000020U)
#define XTAL__PWD_SWREGCLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define XTAL__PWD_SWREGCLK__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define XTAL__PWD_SWREGCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define XTAL__PWD_SWREGCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field local_xtal */
#define XTAL__LOCAL_XTAL__SHIFT                                               6
#define XTAL__LOCAL_XTAL__WIDTH                                               1
#define XTAL__LOCAL_XTAL__MASK                                      0x00000040U
#define XTAL__LOCAL_XTAL__READ(src)     (((u_int32_t)(src) & 0x00000040U) >> 6)
#define XTAL__LOCAL_XTAL__WRITE(src)    (((u_int32_t)(src) << 6) & 0x00000040U)
#define XTAL__LOCAL_XTAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define XTAL__LOCAL_XTAL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define XTAL__LOCAL_XTAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define XTAL__LOCAL_XTAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field xtal_pwdclkin */
#define XTAL__XTAL_PWDCLKIN__SHIFT                                            7
#define XTAL__XTAL_PWDCLKIN__WIDTH                                            1
#define XTAL__XTAL_PWDCLKIN__MASK                                   0x00000080U
#define XTAL__XTAL_PWDCLKIN__READ(src)  (((u_int32_t)(src) & 0x00000080U) >> 7)
#define XTAL__XTAL_PWDCLKIN__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
#define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define XTAL__XTAL_PWDCLKIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define XTAL__XTAL_PWDCLKIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define XTAL__XTAL_PWDCLKIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field xtal_oscon */
#define XTAL__XTAL_OSCON__SHIFT                                               8
#define XTAL__XTAL_OSCON__WIDTH                                               1
#define XTAL__XTAL_OSCON__MASK                                      0x00000100U
#define XTAL__XTAL_OSCON__READ(src)     (((u_int32_t)(src) & 0x00000100U) >> 8)
#define XTAL__XTAL_OSCON__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000100U)
#define XTAL__XTAL_OSCON__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define XTAL__XTAL_OSCON__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define XTAL__XTAL_OSCON__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define XTAL__XTAL_OSCON__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field xtal_atbvreg */
#define XTAL__XTAL_ATBVREG__SHIFT                                             9
#define XTAL__XTAL_ATBVREG__WIDTH                                             1
#define XTAL__XTAL_ATBVREG__MASK                                    0x00000200U
#define XTAL__XTAL_ATBVREG__READ(src)   (((u_int32_t)(src) & 0x00000200U) >> 9)
#define XTAL__XTAL_ATBVREG__WRITE(src)  (((u_int32_t)(src) << 9) & 0x00000200U)
#define XTAL__XTAL_ATBVREG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define XTAL__XTAL_ATBVREG__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define XTAL__XTAL_ATBVREG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define XTAL__XTAL_ATBVREG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field xtal_Lbias2x */
#define XTAL__XTAL_LBIAS2X__SHIFT                                            10
#define XTAL__XTAL_LBIAS2X__WIDTH                                             1
#define XTAL__XTAL_LBIAS2X__MASK                                    0x00000400U
#define XTAL__XTAL_LBIAS2X__READ(src)  (((u_int32_t)(src) & 0x00000400U) >> 10)
#define XTAL__XTAL_LBIAS2X__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
#define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define XTAL__XTAL_LBIAS2X__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define XTAL__XTAL_LBIAS2X__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define XTAL__XTAL_LBIAS2X__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field xtal_bias2x */
#define XTAL__XTAL_BIAS2X__SHIFT                                             11
#define XTAL__XTAL_BIAS2X__WIDTH                                              1
#define XTAL__XTAL_BIAS2X__MASK                                     0x00000800U
#define XTAL__XTAL_BIAS2X__READ(src)   (((u_int32_t)(src) & 0x00000800U) >> 11)
#define XTAL__XTAL_BIAS2X__WRITE(src)  (((u_int32_t)(src) << 11) & 0x00000800U)
#define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define XTAL__XTAL_BIAS2X__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define XTAL__XTAL_BIAS2X__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define XTAL__XTAL_BIAS2X__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field xtal_pwdclkD */
#define XTAL__XTAL_PWDCLKD__SHIFT                                            12
#define XTAL__XTAL_PWDCLKD__WIDTH                                             1
#define XTAL__XTAL_PWDCLKD__MASK                                    0x00001000U
#define XTAL__XTAL_PWDCLKD__READ(src)  (((u_int32_t)(src) & 0x00001000U) >> 12)
#define XTAL__XTAL_PWDCLKD__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
#define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define XTAL__XTAL_PWDCLKD__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define XTAL__XTAL_PWDCLKD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define XTAL__XTAL_PWDCLKD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field xtal_localbias */
#define XTAL__XTAL_LOCALBIAS__SHIFT                                          13
#define XTAL__XTAL_LOCALBIAS__WIDTH                                           1
#define XTAL__XTAL_LOCALBIAS__MASK                                  0x00002000U
#define XTAL__XTAL_LOCALBIAS__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define XTAL__XTAL_LOCALBIAS__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define XTAL__XTAL_LOCALBIAS__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define XTAL__XTAL_LOCALBIAS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define XTAL__XTAL_LOCALBIAS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field xtal_shortXin */
#define XTAL__XTAL_SHORTXIN__SHIFT                                           14
#define XTAL__XTAL_SHORTXIN__WIDTH                                            1
#define XTAL__XTAL_SHORTXIN__MASK                                   0x00004000U
#define XTAL__XTAL_SHORTXIN__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14)
#define XTAL__XTAL_SHORTXIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define XTAL__XTAL_SHORTXIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define XTAL__XTAL_SHORTXIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define XTAL__XTAL_SHORTXIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field xtal_drvstr */
#define XTAL__XTAL_DRVSTR__SHIFT                                             15
#define XTAL__XTAL_DRVSTR__WIDTH                                              2
#define XTAL__XTAL_DRVSTR__MASK                                     0x00018000U
#define XTAL__XTAL_DRVSTR__READ(src)   (((u_int32_t)(src) & 0x00018000U) >> 15)
#define XTAL__XTAL_DRVSTR__WRITE(src)  (((u_int32_t)(src) << 15) & 0x00018000U)
#define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00018000U) | (((u_int32_t)(src) <<\
                    15) & 0x00018000U)
#define XTAL__XTAL_DRVSTR__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00018000U)))

/* macros for field xtal_capoutdac */
#define XTAL__XTAL_CAPOUTDAC__SHIFT                                          17
#define XTAL__XTAL_CAPOUTDAC__WIDTH                                           7
#define XTAL__XTAL_CAPOUTDAC__MASK                                  0x00fe0000U
#define XTAL__XTAL_CAPOUTDAC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00fe0000U) >> 17)
#define XTAL__XTAL_CAPOUTDAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 17) & 0x00fe0000U)
#define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
                    17) & 0x00fe0000U)
#define XTAL__XTAL_CAPOUTDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 17) & ~0x00fe0000U)))

/* macros for field xtal_capindac */
#define XTAL__XTAL_CAPINDAC__SHIFT                                           24
#define XTAL__XTAL_CAPINDAC__WIDTH                                            7
#define XTAL__XTAL_CAPINDAC__MASK                                   0x7f000000U
#define XTAL__XTAL_CAPINDAC__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24)
#define XTAL__XTAL_CAPINDAC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x7f000000U)
#define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define XTAL__XTAL_CAPINDAC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))

/* macros for field tcxodet */
#define XTAL__TCXODET__SHIFT                                                 31
#define XTAL__TCXODET__WIDTH                                                  1
#define XTAL__TCXODET__MASK                                         0x80000000U
#define XTAL__TCXODET__READ(src)       (((u_int32_t)(src) & 0x80000000U) >> 31)
#define XTAL__TCXODET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(1) << 31)
#define XTAL__TCXODET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((u_int32_t)(0) << 31)
#define XTAL__TYPE                                                    u_int32_t
#define XTAL__READ                                                  0xffffffffU
#define XTAL__WRITE                                                 0xffffffffU

#endif /* __XTAL_MACRO__ */


/* macros for radio65_reg_map.ch0_XTAL */
#define INST_RADIO65_REG_MAP__CH0_XTAL__NUM                                   1

/* macros for BlueprintGlobalNameSpace::rbist_cntrl_type */
#ifndef __RBIST_CNTRL_TYPE_MACRO__
#define __RBIST_CNTRL_TYPE_MACRO__

/* macros for field ate_tonegen_dc_enable */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SHIFT                        0
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WIDTH                        1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MASK               0x00000001U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000001U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000001U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((u_int32_t)(src) &\
                    0x00000001U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000001U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(1)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (u_int32_t)(0)

/* macros for field ate_tonegen_tone0_enable */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SHIFT                     1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WIDTH                     1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MASK            0x00000002U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000002U) >> 1)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 1) & 0x00000002U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((u_int32_t)(src) <<\
                    1) & 0x00000002U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 1) & ~0x00000002U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(1) << 1)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((u_int32_t)(0) << 1)

/* macros for field ate_tonegen_tone1_enable */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SHIFT                     2
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WIDTH                     1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MASK            0x00000004U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000004U) >> 2)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 2) & 0x00000004U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((u_int32_t)(src) <<\
                    2) & 0x00000004U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 2) & ~0x00000004U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(1) << 2)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((u_int32_t)(0) << 2)

/* macros for field ate_tonegen_lftone0_enable */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SHIFT                   3
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WIDTH                   1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MASK          0x00000008U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000008U) >> 3)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 3) & 0x00000008U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((u_int32_t)(src) <<\
                    3) & 0x00000008U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 3) & ~0x00000008U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(1) << 3)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((u_int32_t)(0) << 3)

/* macros for field ate_tonegen_linramp_enable_i */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SHIFT                 4
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WIDTH                 1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MASK        0x00000010U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field ate_tonegen_linramp_enable_q */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SHIFT                 5
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WIDTH                 1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MASK        0x00000020U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000020U) >> 5)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 5) & 0x00000020U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((u_int32_t)(src) <<\
                    5) & 0x00000020U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 5) & ~0x00000020U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(1) << 5)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((u_int32_t)(0) << 5)

/* macros for field ate_tonegen_prbs_enable_i */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SHIFT                    6
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WIDTH                    1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MASK           0x00000040U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000040U) >> 6)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 6) & 0x00000040U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((u_int32_t)(src) <<\
                    6) & 0x00000040U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 6) & ~0x00000040U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(1) << 6)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((u_int32_t)(0) << 6)

/* macros for field ate_tonegen_prbs_enable_q */
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SHIFT                    7
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WIDTH                    1
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MASK           0x00000080U
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000080U) >> 7)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 7) & 0x00000080U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((u_int32_t)(src) <<\
                    7) & 0x00000080U)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 7) & ~0x00000080U)))
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(1) << 7)
#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((u_int32_t)(0) << 7)

/* macros for field ate_cmac_dc_write_to_cancel */
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SHIFT                  8
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WIDTH                  1
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MASK         0x00000100U
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000100U) >> 8)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000100U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((u_int32_t)(src) <<\
                    8) & 0x00000100U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000100U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(1) << 8)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((u_int32_t)(0) << 8)

/* macros for field ate_cmac_dc_enable */
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SHIFT                           9
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WIDTH                           1
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MASK                  0x00000200U
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000200U) >> 9)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 9) & 0x00000200U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((u_int32_t)(src) <<\
                    9) & 0x00000200U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 9) & ~0x00000200U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(1) << 9)
#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((u_int32_t)(0) << 9)

/* macros for field ate_cmac_corr_enable */
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SHIFT                        10
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WIDTH                         1
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MASK                0x00000400U
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000400U) >> 10)
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 10) & 0x00000400U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((u_int32_t)(src) <<\
                    10) & 0x00000400U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 10) & ~0x00000400U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(1) << 10)
#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((u_int32_t)(0) << 10)

/* macros for field ate_cmac_power_enable */
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SHIFT                       11
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WIDTH                        1
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MASK               0x00000800U
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000800U) >> 11)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 11) & 0x00000800U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((u_int32_t)(src) <<\
                    11) & 0x00000800U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 11) & ~0x00000800U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(1) << 11)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((u_int32_t)(0) << 11)

/* macros for field ate_cmac_iq_enable */
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SHIFT                          12
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WIDTH                           1
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MASK                  0x00001000U
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001000U) >> 12)
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x00001000U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((u_int32_t)(src) <<\
                    12) & 0x00001000U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x00001000U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(1) << 12)
#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((u_int32_t)(0) << 12)

/* macros for field ate_cmac_i2q2_enable */
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SHIFT                        13
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WIDTH                         1
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MASK                0x00002000U
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00002000U) >> 13)
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 13) & 0x00002000U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((u_int32_t)(src) <<\
                    13) & 0x00002000U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 13) & ~0x00002000U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(1) << 13)
#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((u_int32_t)(0) << 13)

/* macros for field ate_cmac_power_hpf_enable */
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SHIFT                   14
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WIDTH                    1
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MASK           0x00004000U
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00004000U) >> 14)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 14) & 0x00004000U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((u_int32_t)(src) <<\
                    14) & 0x00004000U)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 14) & ~0x00004000U)))
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(1) << 14)
#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((u_int32_t)(0) << 14)

/* macros for field ate_rxdac_calibrate */
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SHIFT                         15
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WIDTH                          1
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MASK                 0x00008000U
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00008000U) >> 15)
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 15) & 0x00008000U)
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((u_int32_t)(src) <<\
                    15) & 0x00008000U)
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 15) & ~0x00008000U)))
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(1) << 15)
#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((u_int32_t)(0) << 15)

/* macros for field ate_rbist_enable */
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SHIFT                            16
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WIDTH                             1
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MASK                    0x00010000U
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00010000U) >> 16)
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00010000U)
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((u_int32_t)(src) <<\
                    16) & 0x00010000U)
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00010000U)))
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(1) << 16)
#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((u_int32_t)(0) << 16)
#define RBIST_CNTRL_TYPE__TYPE                                        u_int32_t
#define RBIST_CNTRL_TYPE__READ                                      0x0001ffffU
#define RBIST_CNTRL_TYPE__WRITE                                     0x0001ffffU

#endif /* __RBIST_CNTRL_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_rbist_cntrl */
#define INST_RADIO65_REG_MAP__CH0_RBIST_CNTRL__NUM                            1

/* macros for BlueprintGlobalNameSpace::tx_dc_offset_type */
#ifndef __TX_DC_OFFSET_TYPE_MACRO__
#define __TX_DC_OFFSET_TYPE_MACRO__

/* macros for field ate_tonegen_dc_i */
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__SHIFT                            0
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WIDTH                           11
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MASK                   0x000007ffU
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000007ffU
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000007ffU)
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((u_int32_t)(src) &\
                    0x000007ffU)
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field ate_tonegen_dc_q */
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__SHIFT                           16
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WIDTH                           11
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MASK                   0x07ff0000U
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x07ff0000U)
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x07ff0000U)
#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x07ff0000U)))
#define TX_DC_OFFSET_TYPE__TYPE                                       u_int32_t
#define TX_DC_OFFSET_TYPE__READ                                     0x07ff07ffU
#define TX_DC_OFFSET_TYPE__WRITE                                    0x07ff07ffU

#endif /* __TX_DC_OFFSET_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_tx_dc_offset */
#define INST_RADIO65_REG_MAP__CH0_TX_DC_OFFSET__NUM                           1

/* macros for BlueprintGlobalNameSpace::tx_tonegen_type */
#ifndef __TX_TONEGEN_TYPE_MACRO__
#define __TX_TONEGEN_TYPE_MACRO__

/* macros for field ate_tonegen_tone_freq */
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__SHIFT                         0
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WIDTH                         7
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MASK                0x0000007fU
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000007fU
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000007fU)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((u_int32_t)(src) &\
                    0x0000007fU)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field ate_tonegen_tone_A_exp */
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__SHIFT                        8
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WIDTH                        4
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MASK               0x00000f00U
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000f00U) >> 8)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00000f00U)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00000f00U)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field ate_tonegen_tone_A_man */
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__SHIFT                       16
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WIDTH                        8
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MASK               0x00ff0000U
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x00ff0000U)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x00ff0000U)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field ate_tonegen_tone_tau_k */
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__SHIFT                       24
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WIDTH                        7
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MASK               0x7f000000U
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x7f000000U) >> 24)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x7f000000U)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x7f000000U)
#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x7f000000U)))
#define TX_TONEGEN_TYPE__TYPE                                         u_int32_t
#define TX_TONEGEN_TYPE__READ                                       0x7fff0f7fU
#define TX_TONEGEN_TYPE__WRITE                                      0x7fff0f7fU

#endif /* __TX_TONEGEN_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_tx_tonegen0 */
#define INST_RADIO65_REG_MAP__CH0_TX_TONEGEN0__NUM                            1

/* macros for radio65_reg_map.ch0_tx_tonegen1 */
#define INST_RADIO65_REG_MAP__CH0_TX_TONEGEN1__NUM                            1

/* macros for radio65_reg_map.ch0_tx_lftonegen0 */
#define INST_RADIO65_REG_MAP__CH0_TX_LFTONEGEN0__NUM                          1

/* macros for BlueprintGlobalNameSpace::tx_linear_ramp_type */
#ifndef __TX_LINEAR_RAMP_TYPE_MACRO__
#define __TX_LINEAR_RAMP_TYPE_MACRO__

/* macros for field ate_tonegen_linramp_init */
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__SHIFT                  0
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WIDTH                 11
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MASK         0x000007ffU
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000007ffU
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000007ffU)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((u_int32_t)(src) &\
                    0x000007ffU)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field ate_tonegen_linramp_dwell */
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__SHIFT                12
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WIDTH                10
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MASK        0x003ff000U
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x003ff000U) >> 12)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 12) & 0x003ff000U)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003ff000U) | (((u_int32_t)(src) <<\
                    12) & 0x003ff000U)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 12) & ~0x003ff000U)))

/* macros for field ate_tonegen_linramp_step */
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__SHIFT                 24
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WIDTH                  6
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MASK         0x3f000000U
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x3f000000U) >> 24)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x3f000000U)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x3f000000U)
#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x3f000000U)))
#define TX_LINEAR_RAMP_TYPE__TYPE                                     u_int32_t
#define TX_LINEAR_RAMP_TYPE__READ                                   0x3f3ff7ffU
#define TX_LINEAR_RAMP_TYPE__WRITE                                  0x3f3ff7ffU

#endif /* __TX_LINEAR_RAMP_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_tx_linear_ramp_i */
#define INST_RADIO65_REG_MAP__CH0_TX_LINEAR_RAMP_I__NUM                       1

/* macros for radio65_reg_map.ch0_tx_linear_ramp_q */
#define INST_RADIO65_REG_MAP__CH0_TX_LINEAR_RAMP_Q__NUM                       1

/* macros for BlueprintGlobalNameSpace::tx_prbs_mag_type */
#ifndef __TX_PRBS_MAG_TYPE_MACRO__
#define __TX_PRBS_MAG_TYPE_MACRO__

/* macros for field ate_tonegen_prbs_magnitude_i */
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__SHIFT                 0
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WIDTH                10
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MASK        0x000003ffU
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field ate_tonegen_prbs_magnitude_q */
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__SHIFT                16
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WIDTH                10
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MASK        0x03ff0000U
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03ff0000U) >> 16)
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x03ff0000U)
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x03ff0000U)
#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x03ff0000U)))
#define TX_PRBS_MAG_TYPE__TYPE                                        u_int32_t
#define TX_PRBS_MAG_TYPE__READ                                      0x03ff03ffU
#define TX_PRBS_MAG_TYPE__WRITE                                     0x03ff03ffU

#endif /* __TX_PRBS_MAG_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_tx_prbs_mag */
#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_MAG__NUM                            1

/* macros for BlueprintGlobalNameSpace::tx_prbs_seed_type */
#ifndef __TX_PRBS_SEED_TYPE_MACRO__
#define __TX_PRBS_SEED_TYPE_MACRO__

/* macros for field ate_tonegen_prbs_seed */
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__SHIFT                       0
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WIDTH                      31
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MASK              0x7fffffffU
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__READ(src) \
                    (u_int32_t)(src)\
                    & 0x7fffffffU
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x7fffffffU)
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x7fffffffU) | ((u_int32_t)(src) &\
                    0x7fffffffU)
#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x7fffffffU)))
#define TX_PRBS_SEED_TYPE__TYPE                                       u_int32_t
#define TX_PRBS_SEED_TYPE__READ                                     0x7fffffffU
#define TX_PRBS_SEED_TYPE__WRITE                                    0x7fffffffU

#endif /* __TX_PRBS_SEED_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_tx_prbs_seed_i */
#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_SEED_I__NUM                         1

/* macros for radio65_reg_map.ch0_tx_prbs_seed_q */
#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_SEED_Q__NUM                         1

/* macros for BlueprintGlobalNameSpace::cmac_dc_cancel_type */
#ifndef __CMAC_DC_CANCEL_TYPE_MACRO__
#define __CMAC_DC_CANCEL_TYPE_MACRO__

/* macros for field ate_cmac_dc_cancel_i */
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__SHIFT                      0
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WIDTH                     10
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MASK             0x000003ffU
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__READ(src) \
                    (u_int32_t)(src)\
                    & 0x000003ffU
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x000003ffU)
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000003ffU) | ((u_int32_t)(src) &\
                    0x000003ffU)
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x000003ffU)))

/* macros for field ate_cmac_dc_cancel_q */
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__SHIFT                     16
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WIDTH                     10
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MASK             0x03ff0000U
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x03ff0000U) >> 16)
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x03ff0000U)
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
                    16) & 0x03ff0000U)
#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x03ff0000U)))
#define CMAC_DC_CANCEL_TYPE__TYPE                                     u_int32_t
#define CMAC_DC_CANCEL_TYPE__READ                                   0x03ff03ffU
#define CMAC_DC_CANCEL_TYPE__WRITE                                  0x03ff03ffU

#endif /* __CMAC_DC_CANCEL_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_dc_cancel */
#define INST_RADIO65_REG_MAP__CH0_CMAC_DC_CANCEL__NUM                         1

/* macros for BlueprintGlobalNameSpace::cmac_dc_offset_type */
#ifndef __CMAC_DC_OFFSET_TYPE_MACRO__
#define __CMAC_DC_OFFSET_TYPE_MACRO__

/* macros for field ate_cmac_dc_cycles */
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__SHIFT                        0
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WIDTH                        4
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MASK               0x0000000fU
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))
#define CMAC_DC_OFFSET_TYPE__TYPE                                     u_int32_t
#define CMAC_DC_OFFSET_TYPE__READ                                   0x0000000fU
#define CMAC_DC_OFFSET_TYPE__WRITE                                  0x0000000fU

#endif /* __CMAC_DC_OFFSET_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_dc_offset */
#define INST_RADIO65_REG_MAP__CH0_CMAC_DC_OFFSET__NUM                         1

/* macros for BlueprintGlobalNameSpace::cmac_corr_type */
#ifndef __CMAC_CORR_TYPE_MACRO__
#define __CMAC_CORR_TYPE_MACRO__

/* macros for field ate_cmac_corr_cycles */
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__SHIFT                           0
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WIDTH                           5
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MASK                  0x0000001fU
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field ate_cmac_corr_freq */
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__SHIFT                             8
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WIDTH                             6
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MASK                    0x00003f00U
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))
#define CMAC_CORR_TYPE__TYPE                                          u_int32_t
#define CMAC_CORR_TYPE__READ                                        0x00003f1fU
#define CMAC_CORR_TYPE__WRITE                                       0x00003f1fU

#endif /* __CMAC_CORR_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_corr */
#define INST_RADIO65_REG_MAP__CH0_CMAC_CORR__NUM                              1

/* macros for BlueprintGlobalNameSpace::cmac_power_type */
#ifndef __CMAC_POWER_TYPE_MACRO__
#define __CMAC_POWER_TYPE_MACRO__

/* macros for field ate_cmac_power_cycles */
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__SHIFT                         0
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WIDTH                         4
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MASK                0x0000000fU
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))
#define CMAC_POWER_TYPE__TYPE                                         u_int32_t
#define CMAC_POWER_TYPE__READ                                       0x0000000fU
#define CMAC_POWER_TYPE__WRITE                                      0x0000000fU

#endif /* __CMAC_POWER_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_power */
#define INST_RADIO65_REG_MAP__CH0_CMAC_POWER__NUM                             1

/* macros for BlueprintGlobalNameSpace::cmac_cross_corr_type */
#ifndef __CMAC_CROSS_CORR_TYPE_MACRO__
#define __CMAC_CROSS_CORR_TYPE_MACRO__

/* macros for field ate_cmac_iq_cycles */
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__SHIFT                       0
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WIDTH                       4
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MASK              0x0000000fU
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))
#define CMAC_CROSS_CORR_TYPE__TYPE                                    u_int32_t
#define CMAC_CROSS_CORR_TYPE__READ                                  0x0000000fU
#define CMAC_CROSS_CORR_TYPE__WRITE                                 0x0000000fU

#endif /* __CMAC_CROSS_CORR_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_cross_corr */
#define INST_RADIO65_REG_MAP__CH0_CMAC_CROSS_CORR__NUM                        1

/* macros for BlueprintGlobalNameSpace::cmac_i2q2_type */
#ifndef __CMAC_I2Q2_TYPE_MACRO__
#define __CMAC_I2Q2_TYPE_MACRO__

/* macros for field ate_cmac_i2q2_cycles */
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__SHIFT                           0
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WIDTH                           4
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MASK                  0x0000000fU
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))
#define CMAC_I2Q2_TYPE__TYPE                                          u_int32_t
#define CMAC_I2Q2_TYPE__READ                                        0x0000000fU
#define CMAC_I2Q2_TYPE__WRITE                                       0x0000000fU

#endif /* __CMAC_I2Q2_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_i2q2 */
#define INST_RADIO65_REG_MAP__CH0_CMAC_I2Q2__NUM                              1

/* macros for BlueprintGlobalNameSpace::cmac_power_hpf_type */
#ifndef __CMAC_POWER_HPF_TYPE_MACRO__
#define __CMAC_POWER_HPF_TYPE_MACRO__

/* macros for field ate_cmac_power_hpf_cycles */
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__SHIFT                 0
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WIDTH                 4
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MASK        0x0000000fU
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000000fU
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000000fU)
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((u_int32_t)(src) &\
                    0x0000000fU)
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field ate_cmac_power_hpf_wait */
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__SHIFT                   4
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WIDTH                   4
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MASK          0x000000f0U
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000000f0U) >> 4)
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x000000f0U)
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((u_int32_t)(src) <<\
                    4) & 0x000000f0U)
#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x000000f0U)))
#define CMAC_POWER_HPF_TYPE__TYPE                                     u_int32_t
#define CMAC_POWER_HPF_TYPE__READ                                   0x000000ffU
#define CMAC_POWER_HPF_TYPE__WRITE                                  0x000000ffU

#endif /* __CMAC_POWER_HPF_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_power_hpf */
#define INST_RADIO65_REG_MAP__CH0_CMAC_POWER_HPF__NUM                         1

/* macros for BlueprintGlobalNameSpace::rxdac_set1_type */
#ifndef __RXDAC_SET1_TYPE_MACRO__
#define __RXDAC_SET1_TYPE_MACRO__

/* macros for field ate_rxdac_mux */
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__SHIFT                                 0
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WIDTH                                 2
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MASK                        0x00000003U
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__READ(src) \
                    (u_int32_t)(src)\
                    & 0x00000003U
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x00000003U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((u_int32_t)(src) &\
                    0x00000003U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x00000003U)))

/* macros for field ate_rxdac_hi_gain */
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SHIFT                             4
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WIDTH                             1
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MASK                    0x00000010U
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00000010U) >> 4)
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 4) & 0x00000010U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((u_int32_t)(src) <<\
                    4) & 0x00000010U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 4) & ~0x00000010U)))
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(1) << 4)
#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((u_int32_t)(0) << 4)

/* macros for field ate_rxdac_cal_wait */
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__SHIFT                            8
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WIDTH                            6
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MASK                   0x00003f00U
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00003f00U) >> 8)
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00003f00U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00003f00U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00003f00U)))

/* macros for field ate_rxdac_cal_measure_time */
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__SHIFT                   16
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WIDTH                    4
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MASK           0x000f0000U
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x000f0000U) >> 16)
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x000f0000U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x000f0000U)
#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x000f0000U)))
#define RXDAC_SET1_TYPE__TYPE                                         u_int32_t
#define RXDAC_SET1_TYPE__READ                                       0x000f3f13U
#define RXDAC_SET1_TYPE__WRITE                                      0x000f3f13U

#endif /* __RXDAC_SET1_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_rxdac_set1 */
#define INST_RADIO65_REG_MAP__CH0_RXDAC_SET1__NUM                             1

/* macros for BlueprintGlobalNameSpace::rxdac_set2_type */
#ifndef __RXDAC_SET2_TYPE_MACRO__
#define __RXDAC_SET2_TYPE_MACRO__

/* macros for field ate_rxdac_i_hi */
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__SHIFT                                0
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WIDTH                                5
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MASK                       0x0000001fU
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field ate_rxdac_q_hi */
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__SHIFT                                8
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WIDTH                                5
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MASK                       0x00001f00U
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00001f00U)
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00001f00U)
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00001f00U)))

/* macros for field ate_rxdac_i_low */
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__SHIFT                              16
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WIDTH                               5
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MASK                      0x001f0000U
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x001f0000U) >> 16)
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 16) & 0x001f0000U)
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001f0000U) | (((u_int32_t)(src) <<\
                    16) & 0x001f0000U)
#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 16) & ~0x001f0000U)))

/* macros for field ate_rxdac_q_low */
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__SHIFT                              24
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WIDTH                               5
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MASK                      0x1f000000U
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x1f000000U) >> 24)
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 24) & 0x1f000000U)
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x1f000000U) | (((u_int32_t)(src) <<\
                    24) & 0x1f000000U)
#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 24) & ~0x1f000000U)))
#define RXDAC_SET2_TYPE__TYPE                                         u_int32_t
#define RXDAC_SET2_TYPE__READ                                       0x1f1f1f1fU
#define RXDAC_SET2_TYPE__WRITE                                      0x1f1f1f1fU

#endif /* __RXDAC_SET2_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_rxdac_set2 */
#define INST_RADIO65_REG_MAP__CH0_RXDAC_SET2__NUM                             1

/* macros for BlueprintGlobalNameSpace::rxdac_long_shift_type */
#ifndef __RXDAC_LONG_SHIFT_TYPE_MACRO__
#define __RXDAC_LONG_SHIFT_TYPE_MACRO__

/* macros for field ate_rxdac_i_static */
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__SHIFT                      0
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WIDTH                      5
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MASK             0x0000001fU
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__READ(src) \
                    (u_int32_t)(src)\
                    & 0x0000001fU
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0x0000001fU)
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((u_int32_t)(src) &\
                    0x0000001fU)
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field ate_rxdac_q_static */
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__SHIFT                      8
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WIDTH                      5
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MASK             0x00001f00U
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__READ(src) \
                    (((u_int32_t)(src)\
                    & 0x00001f00U) >> 8)
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WRITE(src) \
                    (((u_int32_t)(src)\
                    << 8) & 0x00001f00U)
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((u_int32_t)(src) <<\
                    8) & 0x00001f00U)
#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__VERIFY(src) \
                    (!((((u_int32_t)(src)\
                    << 8) & ~0x00001f00U)))
#define RXDAC_LONG_SHIFT_TYPE__TYPE                                   u_int32_t
#define RXDAC_LONG_SHIFT_TYPE__READ                                 0x00001f1fU
#define RXDAC_LONG_SHIFT_TYPE__WRITE                                0x00001f1fU

#endif /* __RXDAC_LONG_SHIFT_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_rxdac_long_shift */
#define INST_RADIO65_REG_MAP__CH0_RXDAC_LONG_SHIFT__NUM                       1

/* macros for BlueprintGlobalNameSpace::cmac_results_type */
#ifndef __CMAC_RESULTS_TYPE_MACRO__
#define __CMAC_RESULTS_TYPE_MACRO__

/* macros for field ate_cmac_results */
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__SHIFT                            0
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WIDTH                           32
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MASK                   0xffffffffU
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__READ(src) \
                    (u_int32_t)(src)\
                    & 0xffffffffU
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WRITE(src) \
                    ((u_int32_t)(src)\
                    & 0xffffffffU)
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((u_int32_t)(src) &\
                    0xffffffffU)
#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__VERIFY(src) \
                    (!(((u_int32_t)(src)\
                    & ~0xffffffffU)))
#define CMAC_RESULTS_TYPE__TYPE                                       u_int32_t
#define CMAC_RESULTS_TYPE__READ                                     0xffffffffU
#define CMAC_RESULTS_TYPE__WRITE                                    0xffffffffU

#endif /* __CMAC_RESULTS_TYPE_MACRO__ */


/* macros for radio65_reg_map.ch0_cmac_results_i */
#define INST_RADIO65_REG_MAP__CH0_CMAC_RESULTS_I__NUM                         1

/* macros for radio65_reg_map.ch0_cmac_results_q */
#define INST_RADIO65_REG_MAP__CH0_CMAC_RESULTS_Q__NUM                         1

/* macros for radio65_reg_map.ch1_RXRF_BIAS1 */
#define INST_RADIO65_REG_MAP__CH1_RXRF_BIAS1__NUM                             1

/* macros for radio65_reg_map.ch1_RXRF_BIAS2 */
#define INST_RADIO65_REG_MAP__CH1_RXRF_BIAS2__NUM                             1

/* macros for radio65_reg_map.ch1_RXRF_GAINSTAGES */
#define INST_RADIO65_REG_MAP__CH1_RXRF_GAINSTAGES__NUM                        1

/* macros for radio65_reg_map.ch1_RXRF_AGC */
#define INST_RADIO65_REG_MAP__CH1_RXRF_AGC__NUM                               1

/* macros for radio65_reg_map.ch1_TXRF1 */
#define INST_RADIO65_REG_MAP__CH1_TXRF1__NUM                                  1

/* macros for radio65_reg_map.ch1_TXRF2 */
#define INST_RADIO65_REG_MAP__CH1_TXRF2__NUM                                  1

/* macros for radio65_reg_map.ch1_TXRF3 */
#define INST_RADIO65_REG_MAP__CH1_TXRF3__NUM                                  1

/* macros for radio65_reg_map.ch1_TXRF4 */
#define INST_RADIO65_REG_MAP__CH1_TXRF4__NUM                                  1

/* macros for radio65_reg_map.ch1_TXRF5 */
#define INST_RADIO65_REG_MAP__CH1_TXRF5__NUM                                  1

/* macros for radio65_reg_map.ch1_TXRF6 */
#define INST_RADIO65_REG_MAP__CH1_TXRF6__NUM                                  1

/* macros for radio65_reg_map.ch1_RXTX1 */
#define INST_RADIO65_REG_MAP__CH1_RXTX1__NUM                                  1

/* macros for radio65_reg_map.ch1_RXTX2 */
#define INST_RADIO65_REG_MAP__CH1_RXTX2__NUM                                  1

/* macros for radio65_reg_map.ch1_RXTX3 */
#define INST_RADIO65_REG_MAP__CH1_RXTX3__NUM                                  1

/* macros for radio65_reg_map.ch1_RXTX4 */
#define INST_RADIO65_REG_MAP__CH1_RXTX4__NUM                                  1

/* macros for radio65_reg_map.ch1_BB1 */
#define INST_RADIO65_REG_MAP__CH1_BB1__NUM                                    1

/* macros for radio65_reg_map.ch1_BB2 */
#define INST_RADIO65_REG_MAP__CH1_BB2__NUM                                    1

/* macros for radio65_reg_map.ch1_BB3 */
#define INST_RADIO65_REG_MAP__CH1_BB3__NUM                                    1

/* macros for radio65_reg_map.ch1_rbist_cntrl */
#define INST_RADIO65_REG_MAP__CH1_RBIST_CNTRL__NUM                            1

/* macros for radio65_reg_map.ch1_tx_dc_offset */
#define INST_RADIO65_REG_MAP__CH1_TX_DC_OFFSET__NUM                           1

/* macros for radio65_reg_map.ch1_tx_tonegen0 */
#define INST_RADIO65_REG_MAP__CH1_TX_TONEGEN0__NUM                            1

/* macros for radio65_reg_map.ch1_tx_tonegen1 */
#define INST_RADIO65_REG_MAP__CH1_TX_TONEGEN1__NUM                            1

/* macros for radio65_reg_map.ch1_tx_lftonegen0 */
#define INST_RADIO65_REG_MAP__CH1_TX_LFTONEGEN0__NUM                          1

/* macros for radio65_reg_map.ch1_tx_linear_ramp_i */
#define INST_RADIO65_REG_MAP__CH1_TX_LINEAR_RAMP_I__NUM                       1

/* macros for radio65_reg_map.ch1_tx_linear_ramp_q */
#define INST_RADIO65_REG_MAP__CH1_TX_LINEAR_RAMP_Q__NUM                       1

/* macros for radio65_reg_map.ch1_tx_prbs_mag */
#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_MAG__NUM                            1

/* macros for radio65_reg_map.ch1_tx_prbs_seed_i */
#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_SEED_I__NUM                         1

/* macros for radio65_reg_map.ch1_tx_prbs_seed_q */
#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_SEED_Q__NUM                         1

/* macros for radio65_reg_map.ch1_cmac_dc_cancel */
#define INST_RADIO65_REG_MAP__CH1_CMAC_DC_CANCEL__NUM                         1

/* macros for radio65_reg_map.ch1_cmac_dc_offset */
#define INST_RADIO65_REG_MAP__CH1_CMAC_DC_OFFSET__NUM                         1

/* macros for radio65_reg_map.ch1_cmac_corr */
#define INST_RADIO65_REG_MAP__CH1_CMAC_CORR__NUM                              1

/* macros for radio65_reg_map.ch1_cmac_power */
#define INST_RADIO65_REG_MAP__CH1_CMAC_POWER__NUM                             1

/* macros for radio65_reg_map.ch1_cmac_cross_corr */
#define INST_RADIO65_REG_MAP__CH1_CMAC_CROSS_CORR__NUM                        1

/* macros for radio65_reg_map.ch1_cmac_i2q2 */
#define INST_RADIO65_REG_MAP__CH1_CMAC_I2Q2__NUM                              1

/* macros for radio65_reg_map.ch1_cmac_power_hpf */
#define INST_RADIO65_REG_MAP__CH1_CMAC_POWER_HPF__NUM                         1

/* macros for radio65_reg_map.ch1_rxdac_set1 */
#define INST_RADIO65_REG_MAP__CH1_RXDAC_SET1__NUM                             1

/* macros for radio65_reg_map.ch1_rxdac_set2 */
#define INST_RADIO65_REG_MAP__CH1_RXDAC_SET2__NUM                             1

/* macros for radio65_reg_map.ch1_rxdac_long_shift */
#define INST_RADIO65_REG_MAP__CH1_RXDAC_LONG_SHIFT__NUM                       1

/* macros for radio65_reg_map.ch1_cmac_results_i */
#define INST_RADIO65_REG_MAP__CH1_CMAC_RESULTS_I__NUM                         1

/* macros for radio65_reg_map.ch1_cmac_results_q */
#define INST_RADIO65_REG_MAP__CH1_CMAC_RESULTS_Q__NUM                         1

/* macros for radio65_reg_map.ch2_RXRF_BIAS1 */
#define INST_RADIO65_REG_MAP__CH2_RXRF_BIAS1__NUM                             1

/* macros for radio65_reg_map.ch2_RXRF_BIAS2 */
#define INST_RADIO65_REG_MAP__CH2_RXRF_BIAS2__NUM                             1

/* macros for radio65_reg_map.ch2_RXRF_GAINSTAGES */
#define INST_RADIO65_REG_MAP__CH2_RXRF_GAINSTAGES__NUM                        1

/* macros for radio65_reg_map.ch2_RXRF_AGC */
#define INST_RADIO65_REG_MAP__CH2_RXRF_AGC__NUM                               1

/* macros for radio65_reg_map.ch2_TXRF1 */
#define INST_RADIO65_REG_MAP__CH2_TXRF1__NUM                                  1

/* macros for radio65_reg_map.ch2_TXRF2 */
#define INST_RADIO65_REG_MAP__CH2_TXRF2__NUM                                  1

/* macros for radio65_reg_map.ch2_TXRF3 */
#define INST_RADIO65_REG_MAP__CH2_TXRF3__NUM                                  1

/* macros for radio65_reg_map.ch2_TXRF4 */
#define INST_RADIO65_REG_MAP__CH2_TXRF4__NUM                                  1

/* macros for radio65_reg_map.ch2_TXRF5 */
#define INST_RADIO65_REG_MAP__CH2_TXRF5__NUM                                  1

/* macros for radio65_reg_map.ch2_TXRF6 */
#define INST_RADIO65_REG_MAP__CH2_TXRF6__NUM                                  1

/* macros for radio65_reg_map.ch2_RXTX1 */
#define INST_RADIO65_REG_MAP__CH2_RXTX1__NUM                                  1

/* macros for radio65_reg_map.ch2_RXTX2 */
#define INST_RADIO65_REG_MAP__CH2_RXTX2__NUM                                  1

/* macros for radio65_reg_map.ch2_RXTX3 */
#define INST_RADIO65_REG_MAP__CH2_RXTX3__NUM                                  1

/* macros for radio65_reg_map.ch2_RXTX4 */
#define INST_RADIO65_REG_MAP__CH2_RXTX4__NUM                                  1

/* macros for radio65_reg_map.ch2_BB1 */
#define INST_RADIO65_REG_MAP__CH2_BB1__NUM                                    1

/* macros for radio65_reg_map.ch2_BB2 */
#define INST_RADIO65_REG_MAP__CH2_BB2__NUM                                    1

/* macros for radio65_reg_map.ch2_BB3 */
#define INST_RADIO65_REG_MAP__CH2_BB3__NUM                                    1

/* macros for radio65_reg_map.ch2_rbist_cntrl */
#define INST_RADIO65_REG_MAP__CH2_RBIST_CNTRL__NUM                            1

/* macros for radio65_reg_map.ch2_tx_dc_offset */
#define INST_RADIO65_REG_MAP__CH2_TX_DC_OFFSET__NUM                           1

/* macros for radio65_reg_map.ch2_tx_tonegen0 */
#define INST_RADIO65_REG_MAP__CH2_TX_TONEGEN0__NUM                            1

/* macros for radio65_reg_map.ch2_tx_tonegen1 */
#define INST_RADIO65_REG_MAP__CH2_TX_TONEGEN1__NUM                            1

/* macros for radio65_reg_map.ch2_tx_lftonegen0 */
#define INST_RADIO65_REG_MAP__CH2_TX_LFTONEGEN0__NUM                          1

/* macros for radio65_reg_map.ch2_tx_linear_ramp_i */
#define INST_RADIO65_REG_MAP__CH2_TX_LINEAR_RAMP_I__NUM                       1

/* macros for radio65_reg_map.ch2_tx_linear_ramp_q */
#define INST_RADIO65_REG_MAP__CH2_TX_LINEAR_RAMP_Q__NUM                       1

/* macros for radio65_reg_map.ch2_tx_prbs_mag */
#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_MAG__NUM                            1

/* macros for radio65_reg_map.ch2_tx_prbs_seed_i */
#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_SEED_I__NUM                         1

/* macros for radio65_reg_map.ch2_tx_prbs_seed_q */
#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_SEED_Q__NUM                         1

/* macros for radio65_reg_map.ch2_cmac_dc_cancel */
#define INST_RADIO65_REG_MAP__CH2_CMAC_DC_CANCEL__NUM                         1

/* macros for radio65_reg_map.ch2_cmac_dc_offset */
#define INST_RADIO65_REG_MAP__CH2_CMAC_DC_OFFSET__NUM                         1

/* macros for radio65_reg_map.ch2_cmac_corr */
#define INST_RADIO65_REG_MAP__CH2_CMAC_CORR__NUM                              1

/* macros for radio65_reg_map.ch2_cmac_power */
#define INST_RADIO65_REG_MAP__CH2_CMAC_POWER__NUM                             1

/* macros for radio65_reg_map.ch2_cmac_cross_corr */
#define INST_RADIO65_REG_MAP__CH2_CMAC_CROSS_CORR__NUM                        1

/* macros for radio65_reg_map.ch2_cmac_i2q2 */
#define INST_RADIO65_REG_MAP__CH2_CMAC_I2Q2__NUM                              1

/* macros for radio65_reg_map.ch2_cmac_power_hpf */
#define INST_RADIO65_REG_MAP__CH2_CMAC_POWER_HPF__NUM                         1

/* macros for radio65_reg_map.ch2_rxdac_set1 */
#define INST_RADIO65_REG_MAP__CH2_RXDAC_SET1__NUM                             1

/* macros for radio65_reg_map.ch2_rxdac_set2 */
#define INST_RADIO65_REG_MAP__CH2_RXDAC_SET2__NUM                             1

/* macros for radio65_reg_map.ch2_rxdac_long_shift */
#define INST_RADIO65_REG_MAP__CH2_RXDAC_LONG_SHIFT__NUM                       1

/* macros for radio65_reg_map.ch2_cmac_results_i */
#define INST_RADIO65_REG_MAP__CH2_CMAC_RESULTS_I__NUM                         1

/* macros for radio65_reg_map.ch2_cmac_results_q */
#define INST_RADIO65_REG_MAP__CH2_CMAC_RESULTS_Q__NUM                         1
#define RFILE_INST_MAC_DMA_REG_MAP__NUM                                       1
#define RFILE_INST_MAC_QCU_REG_MAP__NUM                                       1
#define RFILE_INST_MAC_DCU_REG_MAP__NUM                                       1
#define RFILE_INST_RTC_REG_MAP__NUM                                           1
#define RFILE_INST_RTC_SYNC_REG_MAP__NUM                                      1
#define RFILE_INST_MAC_PCU_REG_MAP__NUM                                       1
#define RFILE_INST_BB_REG_MAP__NUM                                            1
#define RFILE_INST_MAC_PCU_BUF_REG_MAP__NUM                                   1
#define RFILE_INST_SVD_REG_MAP__NUM                                           1
#define RFILE_INST_RADIO65_REG_MAP__NUM                                       1

#define SCORPION_REG_MAP__VERSION \
                    "/cad/local/lib/perl/Pinfo.pm\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl\n\
                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl"
#endif /* __REG_SCORPION_REG_MAP_MACRO_H__ */
